JPH036037A - Semiconductor testing apparatus - Google Patents

Semiconductor testing apparatus

Info

Publication number
JPH036037A
JPH036037A JP14060489A JP14060489A JPH036037A JP H036037 A JPH036037 A JP H036037A JP 14060489 A JP14060489 A JP 14060489A JP 14060489 A JP14060489 A JP 14060489A JP H036037 A JPH036037 A JP H036037A
Authority
JP
Japan
Prior art keywords
test
production line
semiconductor
wafer
measured data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14060489A
Other languages
Japanese (ja)
Other versions
JPH0719824B2 (en
Inventor
Nobuaki Abe
阿部 伸昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP1140604A priority Critical patent/JPH0719824B2/en
Publication of JPH036037A publication Critical patent/JPH036037A/en
Publication of JPH0719824B2 publication Critical patent/JPH0719824B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To judge process capacity of a production line by adding a control apparatus which includes the following: a storage part to which a measured data is input; a computation part to which this stored data is input and which computes a process capacity index corresponding to a preset standard value. CONSTITUTION:When a test start signal is sent out from a probing apparatus 2, measuring conditions are transferred from a CPU 6 to a measuring part 7 and a power supply 8 used to apply a bias; a test signal ST is supplied to a first chip under test of a wafer 3; its electrical characteristic is tested. This measured data SD is transferred to a control apparatus 5 from the CPU 6; a process capacity index of a production line regarding a standard width for each item is computed at a computation part 10 on the basis of the measured data SD which has been stored in a storage part 9. When its result cannot satisfy the preset control standard, a control signal SC is supplied to the probing apparatus 2 from the computation part 10; a test of the chip on the wafer 3 is stopped automatically. Thereby, abnormality of a lot can be predicted; change in the production line can be predicted; it is possible to prevent a drop in the yield and to predict and maintain the quality.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体の試験装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor testing device.

〔従来の技術〕[Conventional technology]

最近の半導体装置の製造工程における試験の増大に伴い
、その効率の向上が重要となってきた。
With the recent increase in testing in the manufacturing process of semiconductor devices, improving the efficiency has become important.

第2図は従来の半導体試験装置の一例のブロック図であ
る。
FIG. 2 is a block diagram of an example of a conventional semiconductor testing device.

半導体試験装置11.は、ブロービング装置2のウェー
ハステージ4に載置された被試験ウェーハ3のチップに
テスト信号STを与え測定データSDを入力する測定部
7と、データSD及び規格値を比較・演算するC’PU
6を有する試験回路部1と、入出力信号SIOを送受す
る入出力機器12とを有していた。
Semiconductor test equipment 11. A measuring section 7 applies a test signal ST to the chips of the wafer under test 3 placed on the wafer stage 4 of the blowing device 2 and inputs measurement data SD, and C' compares and calculates the data SD and standard values. P.U.
6, and an input/output device 12 for transmitting and receiving an input/output signal SIO.

この場合のチップの試験は、予め設定されたテスト条件
や規格のもとに作られたテストプログラムにより自動的
に順次テスト信号STを供給し、ウェーハ3のチップか
ら得られた測定データSDを規格値と照合し、チップの
良否を自動的に判断していた。
In this case, the chip test is performed by automatically sequentially supplying test signals ST using a test program created based on preset test conditions and standards, and measuring data SD obtained from the chips on wafer 3 according to the standards. It automatically judged whether the chip was good or bad by comparing it with the value.

また製造ロッドの品質管理は、サンプリングした測定デ
ータSDの解析によって別に行われていた。
In addition, quality control of manufactured rods was separately performed by analyzing sampled measurement data SD.

第3図及び第4図は半導体装置の品質管理を説明するた
めの特性分布図及びロッド管理図である。
3 and 4 are a characteristic distribution diagram and a rod control diagram for explaining quality control of semiconductor devices.

工程能力指数Cpは、製造ラインが規格を満足する製品
を出しているかを示す品質管理上の判断基準で第(1)
式で表わされる。
The process capability index Cp is the first quality control criterion that indicates whether the manufacturing line is producing products that meet specifications.
It is expressed by the formula.

一般に規格幅Tは標準偏差δの8倍以上であれば工程能
力は十分と云われている。
Generally, it is said that the process capability is sufficient if the standard width T is 8 times or more the standard deviation δ.

その時の工程能力指数Cpは1.33となり、小さいほ
ど好ましくない。
The process capability index Cp at that time is 1.33, and the smaller the value, the less preferable it is.

Cp = T/ < 6δP)・・・(1)また、工程
能力指数CPKも工程平均マ及びばらつき6δPを総合
評価するために用いられる判断基準で第(2)式及び(
3)式に表わされる。
Cp = T/ < 6δP)...(1) Also, the process capability index CPK is a judgment criterion used to comprehensively evaluate the process average and variation 6δP, and is calculated using equation (2) and (
3) Expressed by the formula.

CPK= C(1−K ) xT) / 6δP・・・
(2)K= (IM−xi )/ (T/2>=13)
第3ノに示す特性分布図の場合の工程能力指数CPは1
.86.Cpには0.7で、cpxが悪く、ロッドは不
良で製造ラインは悪いと判断される。
CPK=C(1-K)xT)/6δP...
(2) K= (IM-xi)/ (T/2>=13)
In the case of the characteristic distribution diagram shown in No. 3, the process capability index CP is 1
.. 86. Cp is 0.7, which indicates that cpx is bad, the rod is defective, and the manufacturing line is bad.

また第4図に示すように、第9の製造ロッドL9゛は不
良ロッドであるが、それ以前の第6のロッド上6以降か
らロッド平均値Xの折線が下方管理限界線LCLに向う
傾向にあるので、ロッドL6.L7で製造ロッド異常発
生傾向のアラームを出していた。
Furthermore, as shown in Fig. 4, the ninth manufactured rod L9' is a defective rod, but the broken line of the rod average value Since there is, rod L6. An alarm was being issued at L7 indicating a tendency for production rod abnormalities to occur.

これらの場合、試験を含めた関連製造ラインは一時停止
され、品質管理上の対策後、製造ラインが再稼働する。
In these cases, the related production lines, including testing, will be temporarily suspended and the production lines will be restarted after quality control measures have been taken.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体試験装置は、被試験半導体の測定
値が規格に入っているが否がの試験と、被試験ロッドの
品質管理を別途に行っていたため、半導体装置の製造工
程の品質管理上の工程能力が十分に把握されていないの
で、特性値が規格値内に入っている場合は製造ラインの
変動による規格内での特性変動に気付かず、対策が後手
となり、突然の大量不良発生による歩留の低下を生じる
という欠点があった。
The conventional semiconductor test equipment described above separately tests whether the measured values of the semiconductor under test meet the specifications and performs quality control of the rod under test. Because the process capability of the process is not fully understood, if the characteristic values are within the standard values, changes in the characteristics within the standard due to changes in the production line are not noticed, countermeasures are delayed, and the problem is caused by the sudden occurrence of a large number of defects. This had the disadvantage of causing a decrease in yield.

本発明の目的は、製造ラインの工程能力を判定できる半
導体試験装置を提供することにある。
An object of the present invention is to provide a semiconductor testing device that can determine the process capability of a manufacturing line.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体試験装置は、連続する製造ロッドの被試
験半導体装置を順次接続して電気的特性を測定する試験
回路部を有する半導体試験装置において、前記試験回路
部の出力する前記被試験半導体装置の測定データを入力
して記憶する記憶部と、該記憶部の記憶データを入力し
予め設定した規格値に対応して製造ラインの工程能力指
数を計算する演算部とを含む制御装置を付加して構成さ
れている。
The semiconductor testing apparatus of the present invention includes a test circuit section that sequentially connects semiconductor devices under test of continuous manufacturing rods to measure electrical characteristics, and the semiconductor test device outputs the semiconductor devices under test from the test circuit section. A control device is added that includes a storage unit that inputs and stores measurement data of the storage unit, and a calculation unit that inputs the data stored in the storage unit and calculates a process capability index of the manufacturing line in accordance with preset standard values. It is composed of

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

半導体試験装置11は、第2図の入出力機器12の代り
に試験回路部1からの測定データsDを受けてブロービ
ング装置2に制御信号S。を供給する制御装置5を付加
したことが異る意思外は従来の半導体試験装置 11 
、と同様である。
The semiconductor test device 11 receives measurement data sD from the test circuit section 1 instead of the input/output device 12 in FIG. 2 and sends a control signal S to the probing device 2. The difference is that a control device 5 is added to supply the conventional semiconductor test equipment 11
, is the same as .

制御装置5は、測定データSDを記憶する記憶部つと、
予め設定した規格値幅Tに対応して製造ライン工程能力
指数CP及びCPKを計算する演算部10を有している
The control device 5 includes a storage unit that stores measurement data SD;
It has an arithmetic unit 10 that calculates manufacturing line process capability indices CP and CPK in accordance with a preset standard value range T.

次に、装置11の動作を説明する。Next, the operation of the device 11 will be explained.

まず、ブロービング装置2のウェーハステージ4に自動
的に被試験ウェーハ3が載置される。
First, the wafer 3 to be tested is automatically placed on the wafer stage 4 of the blowing device 2 .

次に、ブロービング装置2がらテスト駕始信号が発せら
れるとCPU6から測定部7とバイアスを印加する電源
8に測定条件が転送され、ウェーハ4の最初の被試験チ
ップにテスト信号S↑が供給されて、その電気的特性が
試験される。
Next, when a test start signal is issued from the blowing device 2, the measurement conditions are transferred from the CPU 6 to the measurement unit 7 and the power supply 8 that applies bias, and the test signal S↑ is supplied to the first chip under test on the wafer 4. and its electrical properties are tested.

この時、試験された測定データsDはCPU6から制御
装置5へ転送される。
At this time, the tested measurement data sD is transferred from the CPU 6 to the control device 5.

CPU6は、試験結果の良否信号をブロービング装置2
に送り、ブロービング装置2のプローブは次の被試験チ
ップに接続を移す。
The CPU 6 sends a pass/fail signal of the test result to the blowing device 2.
The probe of the probing device 2 transfers the connection to the next chip under test.

制御装置5への測定データSoの転送は、サンプリング
上必要な抜取数だけ行われる。
The measurement data So is transferred to the control device 5 as many times as necessary for sampling.

制御装置5では、記憶部9に記憶された測定データSD
をもとに項目毎に規格幅に対する製造ラインの工程能力
指数Cp、Cpにを第(1)及び第(2)式により演算
部10で計算する。
In the control device 5, the measurement data SD stored in the storage section 9
Based on this, the calculation unit 10 calculates the process capability indexes Cp and Cp of the production line for each standard width using equations (1) and (2).

その結果が予め設定された管理基準を満足しない場合は
、演算部]20からブロービング装置2へ制御信号SC
が供給されてウェーハ3のチップの試験を自動的に停止
する。
If the result does not satisfy the preset management criteria, a control signal SC is sent from the calculation unit] 20 to the brobing device 2.
is supplied to automatically stop testing the chips on wafer 3.

それと同時に制御装置5はアラームを発し、ロッド異常
を知らせる。
At the same time, the control device 5 issues an alarm to notify the rod of abnormality.

従って、前述の第3図に示したように、従来は規格不良
が少いので試験が続行されていたロッドでも、cpx不
良の判定で自動的にアラームが発せられ、大量のロッド
不良が発生する前に予防的に試験を中止できる効果があ
る。
Therefore, as shown in Figure 3 above, even for rods for which testing was continued because there were few standard defects, an alarm is automatically issued when a CPX defect is determined, resulting in a large number of rod defects. This has the effect of allowing the test to be stopped preemptively.

また、第1図の記憶部9に、過去のロッドのマのデータ
を順次記憶して第4図に示したような判定をすれば、ロ
ッドの傾向管理が行える効果がある。
Moreover, if past rod data is sequentially stored in the storage unit 9 of FIG. 1 and determinations as shown in FIG. 4 are made, rod trends can be managed.

上述の実施例で、被試験半導体装置として被試験ウェー
ハのチップに適用したが、試験対象として特性選別試験
をする半導体装置に適用してもよい。
In the above-described embodiments, the present invention is applied to a chip of a wafer under test as a semiconductor device under test, but it may also be applied to a semiconductor device subjected to a characteristic selection test as a test object.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、記憶・演算部を有する制
御装置を付加することにより、被試験半導体装置の測定
データを抜取り、ロッドの不良率及び製造ラインの工程
能力指数、さらに記憶装置へ記憶された過去のロッドの
測定値による傾向管理を実施できるので、ロッドの異常
予測や製造ラインの変動予測を行ない、歩留低下の防止
及び品質予知保全が可能となる効果がある。
As explained above, the present invention adds a control device having a memory/calculation unit to extract measurement data of a semiconductor device under test, and stores the defective rate of rods and the process capability index of the manufacturing line in a storage device. Since it is possible to carry out trend management based on past measured values of rods, it is possible to predict rod abnormalities and fluctuations in the production line, thereby making it possible to prevent yield decline and perform quality predictive maintenance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は従来
の半導体試験装置の一例のブロック図、第3図及び第4
図は半導体装置の品質管理を説明するための特性分布図
及びロッド管理図である。 1・・・試験回路部、2・・・ブロービング装置、3・
・・被試験ウェーハ、4・・・ウェーハステージ、5・
・・制御装置、6・・・CPU、7・・・測定部、9・
・・記憶部、10・・・演算部、SC・・・制御信号、
SO・・・測定データ、8丁・・・テスト信号。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of a conventional semiconductor testing device, and FIGS.
The figures are a characteristic distribution diagram and a rod control diagram for explaining quality control of semiconductor devices. 1... Test circuit section, 2... Blobbing device, 3...
...Wafer under test, 4...Wafer stage, 5.
・・Control device, 6・CPU, 7・Measurement unit, 9・
...Storage unit, 10...Calculation unit, SC...Control signal,
SO...Measurement data, 8 pieces...Test signal.

Claims (1)

【特許請求の範囲】[Claims] 連続する製造ロッドの被試験半導体装置を順次接続して
電気的特性を測定する試験回路部を有する半導体試験装
置において、前記試験回路部の出力する前記被試験半導
体装置の測定データを入力して記憶する記憶部と、該記
憶部の記憶データを入力し予め設定した規格値に対応し
て製造ラインの工程能力指数を計算する演算部とを含む
制御装置を付加したことを特徴とする半導体試験装置。
In a semiconductor testing device having a test circuit section that sequentially connects semiconductor devices under test of continuous production rods and measures electrical characteristics, inputting and storing measurement data of the semiconductor device under test output from the test circuit section. A semiconductor testing device comprising: a storage section for inputting data stored in the storage section; and an arithmetic section for inputting data stored in the storage section and calculating a process capability index of a production line in accordance with preset standard values. .
JP1140604A 1989-06-02 1989-06-02 Semiconductor test equipment Expired - Fee Related JPH0719824B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1140604A JPH0719824B2 (en) 1989-06-02 1989-06-02 Semiconductor test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1140604A JPH0719824B2 (en) 1989-06-02 1989-06-02 Semiconductor test equipment

Publications (2)

Publication Number Publication Date
JPH036037A true JPH036037A (en) 1991-01-11
JPH0719824B2 JPH0719824B2 (en) 1995-03-06

Family

ID=15272573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1140604A Expired - Fee Related JPH0719824B2 (en) 1989-06-02 1989-06-02 Semiconductor test equipment

Country Status (1)

Country Link
JP (1) JPH0719824B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04343443A (en) * 1991-05-21 1992-11-30 Nec Yamagata Ltd Semiconductor device test system
US5542404A (en) * 1994-02-04 1996-08-06 Honda Giken Kogyo Kabushiki Kaisha Trouble detection system for internal combustion engine
JP2019144104A (en) * 2018-02-21 2019-08-29 セイコーエプソン株式会社 Electronic component conveyance device and electronic component inspection device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154639A (en) * 1985-12-26 1987-07-09 Sharp Corp Semiconductor selector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154639A (en) * 1985-12-26 1987-07-09 Sharp Corp Semiconductor selector

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04343443A (en) * 1991-05-21 1992-11-30 Nec Yamagata Ltd Semiconductor device test system
US5542404A (en) * 1994-02-04 1996-08-06 Honda Giken Kogyo Kabushiki Kaisha Trouble detection system for internal combustion engine
JP2019144104A (en) * 2018-02-21 2019-08-29 セイコーエプソン株式会社 Electronic component conveyance device and electronic component inspection device

Also Published As

Publication number Publication date
JPH0719824B2 (en) 1995-03-06

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