JPH0360062A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0360062A
JPH0360062A JP1195519A JP19551989A JPH0360062A JP H0360062 A JPH0360062 A JP H0360062A JP 1195519 A JP1195519 A JP 1195519A JP 19551989 A JP19551989 A JP 19551989A JP H0360062 A JPH0360062 A JP H0360062A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
integrated circuit
circuit device
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1195519A
Other languages
Japanese (ja)
Inventor
Sei Tanaka
聖 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1195519A priority Critical patent/JPH0360062A/en
Publication of JPH0360062A publication Critical patent/JPH0360062A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Abstract

PURPOSE:To enhance a package density by laminating a plurality of semiconductor chips and enclosing them in one package. CONSTITUTION:A second semiconductor chip 12 is laminated on a first semiconductor chip 11. In the first semiconductor chip 11, a pad 13 for connecting said chip 11 with the second semiconductor chip 12 is arranged and these are connected by a bonding wire 15. The connection of the first semiconductor chip 11 and a conductive film 14 is made with a conventional bonding wire in this constitution. By this constitution, a larger-scale semiconductor integrated device can be composed without changing a package area of a conventional semiconductor integrated circuit device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に半導体集積回
路の実装構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a mounting structure of a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

従来の半導体集積回路装置では、パッケージ内の半導体
チップはひとつのもので構成されている。In a conventional semiconductor integrated circuit device, a single semiconductor chip is included in the package.

例えば第３図に示す様に、半導体チップ３１は、パッケ
ージ内にパッド３３．導電膜３２をポンディングワイヤ
３４でポンディングされ封入されているにすぎない。For example, as shown in FIG. 3, a semiconductor chip 31 has pads 33. The conductive film 32 is simply bonded and sealed with a bonding wire 34.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述した従来の半導体集積回路装置では、回路規模が大
きくなると、半導体チップの大きさが大きくなり、プリ
ント基板の実装面積も大きくなってしまうので、その半
導体集積回路装置を使用した装置の大きさが大きくなっ
てしまうという欠点がある。In the conventional semiconductor integrated circuit device mentioned above, as the circuit scale increases, the size of the semiconductor chip increases and the mounting area of the printed circuit board also increases, so the size of the device using the semiconductor integrated circuit device increases. The disadvantage is that it becomes large.

また、従来の半導体集積回路装置のパッケージ内の半導
体集積回路素子の配置では、単数の半導体チップを置く
他に、複数の半導体チップを横に並べて置くものもあっ
た。この場合も、実装面積が大となる欠点があった。Furthermore, in the conventional arrangement of semiconductor integrated circuit elements in the package of a semiconductor integrated circuit device, in addition to placing a single semiconductor chip, there are also cases in which a plurality of semiconductor chips are placed side by side. In this case as well, there was a drawback that the mounting area was large.

本発明の目的は、前記欠点が解決され、実装密度を上げ
るようにした半導体集積回路装置を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which the above drawbacks are solved and the packaging density is increased.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路装置の構成は、複数の半導体チ
ップを互いに積み重ね、ひとつのパッケージ内に封入し
たことを特徴とする特〔実施例〕 次に本発明について図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a semiconductor integrated circuit device of the present invention is characterized in that a plurality of semiconductor chips are stacked on top of each other and sealed in one package. [Embodiment] Next, the present invention will be described with reference to the drawings.

第１図（Ａ）、第１図（Ｂ）は本発明の一実施例の半導
体集積回路装置を示す平面図、断面図である。FIG. 1(A) and FIG. 1(B) are a plan view and a sectional view showing a semiconductor integrated circuit device according to an embodiment of the present invention.

第１図（Ａ）　、　（Ｂ）において、本実施例は、第１
の半導体チップ１１の上に、第２の半導体チップ１２を
積み重ね、第１の半導体チップ１１内に、第２の半導体
チップ１２との接続の為のバッド１３を設け、ポンディ
ング・ワイヤ１５により接続する。In FIGS. 1(A) and 1(B), this example shows the first
A second semiconductor chip 12 is stacked on top of the semiconductor chip 11, and a pad 13 for connection with the second semiconductor chip 12 is provided inside the first semiconductor chip 11, and the connection is made with a bonding wire 15. do.

第１の半導体チップ１１と導電膜１４との接続は、従来
通りのポンディング・ワイヤの構成となる。The connection between the first semiconductor chip 11 and the conductive film 14 is a conventional bonding wire configuration.

前記構成により、従来の半導体集積回路装置の実装面積
を変えることなく、より大規模な半導体集積回路装置が
構成できる。さらに、例えば上に積み重ねる第２の半導
体チップ１２を既存の半導体チップ、下に積み重ねられ
る第１の半導体チップ１１を新規開発した周辺装置の半
導体チップを使用することにより、下に積み重ねられる
半導体チップ１１だけを設計するだけで済むので、開発
期間が短かくなり、半導体集積回路装置の信頼性は、上
に積み重ねる半導体チップと下に積み重ねられる半導体
チップを両方開発したものより、高くなる。With the above configuration, a larger scale semiconductor integrated circuit device can be constructed without changing the mounting area of a conventional semiconductor integrated circuit device. Further, for example, by using an existing semiconductor chip as the second semiconductor chip 12 to be stacked on top and a semiconductor chip of a newly developed peripheral device as the first semiconductor chip 11 to be stacked on the bottom, the semiconductor chips 11 to be stacked on the bottom may be used. Since it is only necessary to design only one semiconductor chip, the development period is shortened, and the reliability of the semiconductor integrated circuit device is higher than one in which both semiconductor chips are stacked on top and semiconductor chips are stacked on the bottom.

第２図は本発明の他の実施例の半導体集積回路装置の製
法を示す斜視図である。第２図において、本実施例は、
単一の半導体チップ２１，２２．２３を積み重ねて半導
体チップ２４．２５を構成している。FIG. 2 is a perspective view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. In FIG. 2, this example shows the following:
Semiconductor chips 24, 25 are constructed by stacking single semiconductor chips 21, 22, 23.

例えば、半導体チップ２１をＲＡＭ　（ランダム・アク
セス・メモリ）素子、半導体チップ２２を周辺回路素子
、半導体チップ２３をＲＯＭ（！Ｊ−ド・オンリ・メモ
リ）素子とした場合、異なった２つの半導体集積回路装
置２３を構成するには、半導体チップ２４．２５のよう
に、半導体チップ２２の上に積み重ねる半導体チップ２
１，２３を選択するだけで良く、半導体チップ２２を共
通で使用することができる利点があり、開発期間の短縮
の効果がある。For example, if the semiconductor chip 21 is a RAM (random access memory) element, the semiconductor chip 22 is a peripheral circuit element, and the semiconductor chip 23 is a ROM (!J-de-only memory) element, two different semiconductor integrated To configure the circuit device 23, the semiconductor chips 2 are stacked on top of the semiconductor chip 22, such as semiconductor chips 24 and 25.
It is only necessary to select 1 and 23, and there is an advantage that the semiconductor chip 22 can be used in common, which has the effect of shortening the development period.

次に、上に積み重ねる半導体チップ２１を既作の信頼性
の高い半導体チップ、例えばハードマクロやＲＡＭ、Ｒ
ＯＭ素子、下に積み重ねられる半導体チップ２２を新規
開発の周辺装置の半導体チップにすることにより、作成
された半導体チップの信頼性の向上を図れる。Next, the semiconductor chip 21 to be stacked on top is replaced with an existing highly reliable semiconductor chip, such as a hard macro, RAM, R
By using the OM element and the semiconductor chip 22 stacked below as a semiconductor chip for a newly developed peripheral device, it is possible to improve the reliability of the manufactured semiconductor chip.

例えば上に積み重ねる半導体チップ２１をスタンタート
セル方式、ゲートアレ一方式、又はフルカスタム方式で
設計された半導体チップ、下に積み重ねられる半導体チ
ップ２２をゲートアレ一方式、スタンダード・セル方式
、又はフルカスタム方式で設計された半導体チップとし
て、半導体チップ２４を構成する。この様に設計方式の
異なった半導体チップを組み合わせて構成することも可
能である。For example, the semiconductor chips 21 stacked on top are designed using a standart cell method, a single gate array method, or a full custom method, and the semiconductor chips 22 stacked below are designed using a single gate array method, a standard cell method, or a full custom method. The semiconductor chip 24 is configured as a designed semiconductor chip. In this way, it is also possible to construct a structure by combining semiconductor chips with different design methods.

また、設計プロセスの異なった半導体チップを組み合せ
て構成することも可能である この他に、半導体集積回路装置の実装面積の大きさに応
じて、積み重ねる半導体チップの積み重ね段数を３段、
４段とすることも可能である。It is also possible to combine semiconductor chips with different design processes.In addition, depending on the size of the mounting area of the semiconductor integrated circuit device, the number of stacked semiconductor chips can be increased to three,
It is also possible to have four stages.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、複数の半導体チップを
積み重ねた構造をもつ半導体集積回路装置にすることに
より、半導体集積回路装置の実装面積を変えることなく
、集積度を高める効果があり、また開発期間が短縮し、
製品の信頼性が向上する効果もある。As explained above, the present invention has the effect of increasing the degree of integration without changing the mounting area of the semiconductor integrated circuit device by creating a semiconductor integrated circuit device having a structure in which a plurality of semiconductor chips are stacked. Development period is shortened,
This also has the effect of improving product reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（Ａ）は、本発明の一実施例の半導体集積回路装
置を示す平面図、第１図（Ｂ）は第１図（Ａ）の断面図
、第２図は本発明の他の実施例の半導体集積回路の製法
を示す斜視図、第３図は従来の半導体集積回路の断面図
である。 １１．１２，２１，２２，２３，２，１，２５゜３１・
・・・・・半導体チップ、１３．３３・・・・・・パッ
ド、１４．３２・・・・・・導電膜、１５．３４・・・
・・・ポンディングワイヤ。FIG. 1(A) is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 1(B) is a sectional view of FIG. 1(A), and FIG. 2 is a plan view showing a semiconductor integrated circuit device according to an embodiment of the present invention. A perspective view showing a method of manufacturing a semiconductor integrated circuit according to an embodiment, and FIG. 3 is a sectional view of a conventional semiconductor integrated circuit. 11.12,21,22,23,2,1,25°31・
... Semiconductor chip, 13.33 ... Pad, 14.32 ... Conductive film, 15.34 ...
...Ponding wire.

Claims (1)

【特許請求の範囲】[Claims] 複数の半導体チップを互いに積み重ね、ひとつのパッケ
ージ内に封入したことを特徴とする半導体集積回路装置
。A semiconductor integrated circuit device characterized by multiple semiconductor chips stacked on top of each other and sealed in a single package.
JP1195519A 1989-07-27 1989-07-27 Semiconductor integrated circuit device Pending JPH0360062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1195519A JPH0360062A (en) 1989-07-27 1989-07-27 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1195519A JPH0360062A (en) 1989-07-27 1989-07-27 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0360062A true JPH0360062A (en) 1991-03-15

Family

ID=16342437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1195519A Pending JPH0360062A (en) 1989-07-27 1989-07-27 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0360062A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009152616A (en) * 2001-03-02 2009-07-09 Qualcomm Inc Mixed analog and digital integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009152616A (en) * 2001-03-02 2009-07-09 Qualcomm Inc Mixed analog and digital integrated circuit

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