JPH0359900A - Semiconductor memory element - Google Patents

Abstract

PURPOSE:To measure an accurate timing at the time of writing only by means of a tester by providing a monitor terminal which can observe the difference of timing for a RAM circuit having two clock inputs. CONSTITUTION:First and second clock input terminals 1 and 2, and the RAM circuit 14 which leaks a register where data is set by an input from the first clock input terminal 1 to an address and in which a write pulse is generated by the input from the second clock input terminal 2 are provided. The monitor output terminal 7 for monitoring an input waveform from the first and second clock input terminals 1 and 2 is provided and wiring is executed in such a way that transmission time of a signal from the first clock input terminal 1 to the monitor output terminal 7, and that of the signal from the second clock input terminal 2 to the monitor output terminal 7 become equal. Thus, the timing can be measured without using an oscillograph.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and more particularly to performance measurement of RAM circuits having multiple clock inputs.

[Prior Art] In general, when measuring the characteristics of semiconductor memory elements, especially when measuring the AC characteristics of high-speed RAM circuits, it is necessary to accurately measure the time skew of test signals from a tester (tester). It is necessary to match the setting value. At this time, the tester itself can match within a certain accuracy range, but in practice, the test signal from the tester that is actually output at the point where the device under test interfaces with the tester (contact pin) is used as an oscilloscope. etc., and skew adjustment was performed.

[Problems to be Solved by the Invention] In the conventional semiconductor memory device described above, an oscillograph or the like is required when skewing the tester, and the waveform is observed by directly contacting the oscillograph probe with the contact pin. There is a need. However, in recent years, with the increase in the number of bins in devices, the spacing between contacts and pins has become narrower, and it has become difficult to bring the tip of the probe into contact with only specific contacts and bins. There are also problems with contact bottle breakage and oscillograph preparation.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a semiconductor memory element that can perform timing measurement without using an oscilloscope or the like.

[Differences between the Invention and the Prior Art] The present invention differs from the conventional semiconductor memory device described above in that it is provided with an output circuit for observing a clock signal within the memory device.

[Means for Solving the Problems] A semiconductor memory device of the present invention has first and second clock input terminals, and a register in which data is set by input from the first clock input terminal, so as to prevent address leakage. and a monitor output for monitoring input waveforms from the first and second clock input terminals in a semiconductor memory device including a RAM circuit in which a write pulse is generated by input from the second clock input terminal. terminal, and the propagation time of the signal from the first clock input terminal to the monitor output terminal of the first half is equal to the propagation time of the signal from the second clock input terminal of the first half to the monitor output terminal of the first half. Features.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. A clock signal (referred to as clock A) input from clock input terminal 1 is sent to address register 13 and read data register 16 via line 01, gate circuit 9, line 105, clock driver 11, and line 109. Ru. Further, a clock signal (referred to as clock B) inputted from the clock input terminal 2 is connected to a line 102, a gate circuit 10,
It is sent to the write pulse generation circuit 12 through line 107. A write enable signal is input from the write enable input terminal 3 and sent to the write pulse generation circuit 12 through a line 103.

The write pulse generation circuit 12 generates a write pulse based on the first clock input B and the write enable signal.

In this operation, as shown in FIG. 2, when the write enable signal has a value of "1", a write pulse is generated at a predetermined timing in response to the falling edge of the clock B from the clock input terminal 2. The write pulse is line 11
0 to the RAM circuit 14. RAM circuit 14
The address of is input from the address input terminal 5, and the address of
1 and is sent to the address register 13. Address register 13 receives clock A input via line 109.
sets the address by and sends it to the RAM circuit 14 on line 112. At the time of reading, the RAM circuit 14 receives the 7 address signal from the ζ line 112 and sends read data corresponding to the address from the line 114. Read data register 16 sets read data sent out on line 114 by clock A from line 109;
It is sent to read data output 8 through line 115. Further, during writing, a write pulse generated by the write pulse generation circuit 12 is inputted to the RAM circuit 14 from the line 110, and data is written to the address inputted from the line 112.

The write data at this time is input to the RAM circuit 14 from the write data input 6 through the line 113.

Output of gate circuit 9 (clock A) and gate circuit 1
The output of 0 (clock B) is connected to line 106 and line 1, respectively.
08 to the selector 16. The selector 15 receives the switching signal from the switching signal input terminal 4 via the line 104.
Either the line 106 or the line 10B is selected depending on the value "0" or "1" of the switching signal, and the signal is sent from the line 116 to the monitor output terminal 7. Here, from clock input terminal 1 to monitor output terminal 7
The line 1 is arranged so that the signal propagation time of the path from the clock input terminal 2 to the monitor output terminal 7 is equal to that of the path from the clock input terminal 2 to the monitor output terminal 7.
01 and the line 102 and the line 106 and the line 108 are wired to have the same length, respectively.

The operation of one embodiment of the present invention having the above configuration will be described in further detail. Usually, the address set-up time (t5A) is measured using a dedicated tester (tester) at the timing shown in FIG. 2, for example. In this embodiment, the time from when clock A is input to the clock input terminal to when clock B is input to clock input terminal 2 is defined as tSA. To accurately measure tSA, it is necessary to accurately know the timing of clock A and clock B (however, only the difference between the two clocks is sufficient).

For this purpose, monitor terminal 7 is used. That is, at a certain timing (for example, clock A is set to 5 NS).

The clock B is set to 7NS), and the propagation time (T1) of the signal from the clock input terminal 1 to the monitor output terminal 7 is measured using a tester. Similarly, the propagation time (T2) of the signal from the clock input terminal 2 to the monitor output terminal 7 is measured. As explained earlier, the signal propagation time of the path from clock input terminal 1 to monitor output terminal 7 and the path from clock input terminal 2 to monitor output terminal 7 are equal, so
T2-TI is the difference in setting timing (7NS in this example)
-5NS=2NS). Therefore, if the timing of the measurement system including the tester is accurate, the measured value will be T2.
-T 1 = 2NS, and the measured tsAO
The value is equal to the true tSA. If the timing of the measurement system including the tester is off, for example, T2-TI
= 1.8NS, the true tsA value is 2NS-
This means that the value deviates from the measured value by 1,8NS=0°2NS. Therefore, the true tsA value is the measured tSA value +
It is determined by 0.2NS. Note that the address hold time (t) (IA) can also be determined in the same manner.

Note that instead of using the switching signal input terminal 4 of the selector 15 as an input terminal, a flip-flop whose value can be set using a shift path can be used. In this case, there is an advantage that the number of signal terminals is reduced by one bin.

[Effect of the invention] As explained above, the present invention provides clock A and clock B.
In a RAM circuit that has two clock inputs, by having a monitor terminal that can observe the difference in timing, it is possible to accurately measure write timing (tSA, tHA, etc.) using only a tester without using an oscilloscope. I can do it. Additionally, if an oscilloscope is used in combination, the timing skew between clocks can be accurately adjusted by observing the monitor output (not necessarily on the contact bin).

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the timing when measuring the write timing of the RAM circuit in FIG. 1. 1.2... Clock input terminal, 7...
...Monitor output terminal, 9,]O...Gate circuit, 11...Clock driver, 12...
...Write pulse generation circuit, 13...
・Address register, 14...◆...RAM circuit, 15...Selector, 16...Read data register.

Claims (1)

[Claims] First and second clock input terminals and a register in which data is set by the input from the first clock input terminal are used as address inputs, and a write pulse is generated by the input from the second clock input terminal. A semiconductor memory device equipped with a RAM circuit that has a monitor output terminal for monitoring input waveforms from the first and second clock input terminals, and has a monitor output terminal for monitoring input waveforms from the first and second clock input terminals. A semiconductor memory device characterized in that the propagation time of a signal from the second clock input terminal to the monitor output terminal is equal to the propagation time of the signal from the second clock input terminal to the monitor output terminal.