JPH02285600A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To measure an exact address access time without using an oscillograph, etc., by providing an output terminal to observe a clock signal in a memory device. CONSTITUTION:In a RAM circuit equipped with two clock inputs such as an address clock and a data clock, a monitor terminal 6 is provided to observe the difference of timing between the two clocks. For a route from a clock input terminal 1 to the monitor output terminal 6 and a route from a clock input terminal 2 to the monitor output terminal 6, the lengths of lines 101, 102, 104 and 106 are respectively made equal so that a delay time can be equal. Thus, the exact address access time can be measured only by a tester without using the oscillograph, etc. Further, it can be also possible to exactly match timing skew between the clocks by using the ocillograph as well and observing a monitor output.

Description

[Detailed Description of the Invention] [Industrial Field of Application] [Prior Art] In general, when measuring the characteristics of semiconductor memory devices, especially when measuring the address access time (tAA) of high-speed RAM circuits, it is common to use a tester. It is necessary to properly match the time skew of the test signal with the set value. At this time, the tester itself can match the accuracy within a certain range, but in practice, the test signal from the tester that is actually output is used as an oscilloscope at the point where the non-measuring device interfaces with the tester (contact bin). etc., and skew adjustment was performed.

[Problems to be Solved by the Invention] In the conventional semiconductor memory device described above, an oscillograph or the like is required when performing skew adjustment of the tester, and the probe of the oscillograph is brought into direct contact with the contact pin of the tester to measure the waveform. It is necessary to observe. In recent years, with the increase in the number of bins in devices, the spacing between contact bins has become narrower, making it difficult to bring the tip of the broach into contact with only a specific contact pin. There is also the problem of damage to the contact pins.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a semiconductor memory device that can accurately measure address access time without using an oscilloscope or the like.

[Differences between the present invention and the prior art] The present invention differs from the conventional semiconductor memory device described above in that it is provided with an output terminal for observing a clock signal within the memory device.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes first and second clock input terminals, a register to which input data is set by the first clock is used as an address input, and the second
a semiconductor memory device comprising a RAM circuit that outputs read data from a register reset by a clock, the semiconductor memory device having a monitor output terminal for monitoring waveforms of the first and second clocks; The delay time of the signal path from the first clock input terminal to the monitor output terminal and the delay time of the signal path from the second clock input terminal to the monitor output terminal are set to be equal.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The address clock signal input from the clock input terminal is sent to the address register 12 via the line 101 → gate circuit 8 → line 103 → clock driver 10 → line 108.
It is connected to the.

Similarly, the data clock signal input from the clock input terminal 2 is connected to the data register 13 via the line 102 → gate circuit 9 → line 105 → clock driver 11 → line 109.

The address of the RAM circuit 14 is input from the address input terminal 4 and is connected to the address register 12 by a line 110. An address clock signal is set in the address register 12 via line 108, and the address fetched from terminal 4 is sent to RAM circuit 14 via line 112.

On the other hand, inputs other than addresses such as write data, write pulses, write inhibit signals, etc. are sent from input terminal 5 to line 111.
The data is sent directly to the RAM circuit 14 via. The output data sent from the RAM circuit 14 is sent to the data output terminal 7 via a line 113 → data register 13 → line 115.
It is connected to the. The read data sent to the data register 13 is taken in by the data clock signal from the line 109 and sent out from the data output terminal 7. Further, the clock signals input to the gate circuits 8 and 9 are connected to the selector 15 via a line 104 and a line 106. The switching signal 3 is input to the selector 15 via the line 107, and either the line 104 or the line 106 is selected depending on the value "0" or "1" of the switching signal 3, and the signal is input via the line 114. and is output from the monitor output terminal 6.

In addition, the line 101 and the line 10 are connected so that the delay time of the path from the clock input terminal 1 to the monitor output terminal 6 and the path from the clock input terminal 2 to the monitor output terminal 6 are equal.
2, and the lines 104 and 106 are each of equal length.

With the above configuration, the operation of an embodiment of the present invention will be described in more detail. Usually, the address access time (tAA) is measured using a dedicated test device (tester) at the timing shown in FIG. 2, for example. Here, the minimum time from when the address clock is input to clock input terminal 1 to when the data clock is input to clock input terminal 2 is defined as address access time tAA. To accurately measure tAA, it is necessary to accurately know the timing of the address clock and data clock (however, only the difference between the two clocks may be used). For this purpose, monitor terminal 6 is used.

In other words, at a certain timing (for example, if the address clock is
NS, data clock is set to 8NS), and the delay time (T1) from clock input terminal 1 to monitor output terminal 6 is set.
Measure with a tester. Next, the delay time (T2) from the clock input terminal 2 to the monitor output terminal 6 is similarly measured. Here, as explained earlier, clock input terminal 1
→ Since the delay time of the path of monitor output terminal 6 and the path of clock input terminal 2 → monitor output terminal 6 is equal, T2T
1 is the difference in setting timing (8NS-5NS in this example)
=3NS). That is, if the timing of the measurement system including the tester is accurate, T2-T1 should be 3NS. In this case, the measured tAA is the true tA
Equal to A. In addition, if the timing is off, for example, T
If 2-'r 1 =2.8NS, then the actual speed is 0°2NS faster than the set value. Therefore (true tA
A)=(measured tAA)-(0,2NS) Note that instead of using the switching signal 3 of the selector 15 as an input terminal in FIG. 1, a flip-flop whose value can be set using a shift path can also be used. In this case, the signal terminal is 1
It has the advantage of requiring fewer pins.

[Effects of the Invention] As explained above, the present invention provides a RAM circuit that has two clock inputs, an address clock and a data clock, by providing a monitor terminal that can observe the difference in timing between the two clocks, thereby making it possible to use an oscilloscope, etc. Accurate address access time t using a tester without using
AA can be measured. Furthermore, by observing the monitor output using an oscilloscope (not necessarily on the contact pin), it is possible to accurately match the timing skew between clocks.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a RAM circuit in FIG.
FIG. 3 is a diagram showing timing during AA measurement. 1...2φ・6...8.9 10゜12・13・14゗15φ Address clock input terminal, data clock input terminal, monitor output terminal, gate circuit, clock driver, address register, data register, RAM circuit, selector. Patent applicant: NEC Corporation

Claims (1)

[Claims] A RAM circuit is provided with first and second clock input terminals, uses a register to which input data is set by the first clock as an address input, and outputs read data from the register which is reset by the second clock. A semiconductor memory device comprising a monitor output terminal for monitoring waveforms of the first and second clocks, and a delay time of a signal path from the first clock input terminal to the monitor output terminal. and a delay time of a signal path from the second clock input terminal to the monitor output terminal are set to be equal.