JPH0359896A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten test time by selectively outputting one of output data of a memory array, and the outputs of coincidence/dissidence detection circuits of n-number of sub-arrays and all the sub-arrays. CONSTITUTION:N-number of first coincidence/dissidence detection circuits 50-1 to 50-n which read m-number of data written into respective sub-arrays 30-1 to 30-n and which detect coincidence/dissidence among m-number of data, and one second coincidence/dissidence detection circuit 60 which reads nXm-number of data written into all the sub-arrays 30-1 to 30-n and which detects coincidence/dissidence among nXm-number of data are provided. Furthermore, output means (buffer) 80-1 to 80-n which selectively output output data of the memory array, the outputs of n-number of first coincidence/dissidence detection circuits and the output of the second coincidence/dissidence detection circuit are provided. Thus, test time can be shortened and test cost can be reduced without making circuit constitution complicated.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention has a built-in test circuit that has a redundant circuit for relieving defective memory cells and has an on-chip test function (self-test function) for determining pass/fail. Dynamic RAM (
The invention relates to semiconductor memory devices such as random access memory (random access memory) and the like.

(Prior Art) Conventionally, as a technology in this field, there has been a technology as shown in FIG. 2, for example. The configuration will be explained below using figures.

FIG. 2 is a schematic block diagram showing an example of the configuration of a conventional semiconductor memory device with a built-in test circuit.

In this semiconductor storage device, in order to prevent delays in access time and increase in power consumption due to large memory capacity,
A memory array 10 for data storage is formed by being divided into a plurality of (n>subarrays) ○-1 to 10-n. Each sub-array 101 to 10-n has a plurality (m> data outputs D1 to D0), and in addition to a memory cell array 11, a row decoder 12, and a column decoder 13, a redundant circuit 14
They each have The redundancy circuit 14 is for relieving defective memory cells, and is composed of a plurality of redundant memory cells, a decoder for selecting them, and the like.

Data outputs Dl to D of each subarray l0-1 to 10-n
, are connected to the decoder 16 via input/output circuits 15-1 to 15-n, and are also connected to a test circuit 20 for on-chip testing.

The decoder 6 is a circuit that decodes the data output Hx (Dt to D,) from each of the input/output circuits 15-1 to 15-n and selects one of them.

The test circuit 20 includes a match/mismatch detection circuit 2 that detects whether all data outputs HX (Dt to D,) from all input/output circuits 15-1 to 5-n match, and a test A switch circuit 2 that switches the output of either the decoder 16 or the match/mismatch detection circuit 2 based on the signal.
It is composed of 2. The output of the switch circuit 22 is
It is output via the output buffer 23 in the form of an output signal Dout.

Note that a write circuit (not shown) is connected to the input/output circuits 15-1 to 15-n.

Next, the manufacturing method, operation, etc. will be explained.

In manufacturing a semiconductor memory device, on a semiconductor wafer, the memory array 10 shown in FIG. 2, input/output circuits 5-1 to 15-n,
After forming the decoder 16, output buffer 23, etc., probing is performed to detect defective memory cells, and a relief program process for each redundant circuit 4 is performed.

That is, during probing, a memory tester is used to write data to one memory cell array in each subarray 10-1 to 10-n via input/output circuits 151 to 15-n. Then, the written data is transferred to, for example, the input/output circuits 15-1 to 15-n and the decoder 16.
The data is read through the switch E@22 and the output buffer 23, and compared with an expected value by a tester to detect the presence or absence of a defective memory cell and a defective address. For example, subarray 1
If a defective memory cell exists in 0-1, the redundant memory cell location in the redundant circuit 14 corresponding to the defective address is cut with a laser beam or the like, and the defective memory cell is replaced with a redundant memory cell for repair. program processing).

Thereafter, the manufacturing of the semiconductor memory device is completed through a predetermined process. After manufacturing is completed, on-chip testing is performed to determine the quality of the product. In this case, the switch circuit 22 is switched to the match/mismatch detection circuit 2 side by a test signal from the outside (not shown).

Then, the data written to all sub-arrays ↑0-1 to 10-n is sequentially sent via the input/output circuits 15-1 to 15-n, and
The data output nX (Dt to D.) is input to the match/mismatch detection circuit 21. - The match/mismatch detection circuit 21 detects match/mismatch among all input data and outputs the detection result. The detection result is output to the outside in the form of an output signal Dout via the switch circuit 22 and the output buffer 23, so that it is possible to determine the quality of the product. By performing such an on-chip test, it is possible to simplify the test device, shorten the test time, and reduce the test cost.

Note that during normal reading, all input/output circuits 15-
One of the data outputs nX (D1 to D,) from 1 to 15-n is selected by the decoder 16, and the switch 22
and is output to the outside via the output buffer 23.

(Problems to be Solved by the Invention) However, the semiconductor memory device having the above configuration has the following problems.

Since a conventional semiconductor memory device has a built-in test circuit 20, it has the advantage that it can easily determine whether the product is good or bad after it is completed. However, during on-chip testing, the match/mismatch detection circuit 21
Match/mismatch detection is performed for all data outputs n×(Di~D,) at once, so which subarray 10-E~■○
It is not possible to determine whether -n includes a defective memory cell.

In other words, subarrays 1°-1 to 1°-1 with defective memory cells
10-n cannot be specified. Therefore, since it is not possible to determine the defective address required for the redundant circuit 14 relief program, the on-chip test function cannot be used during probing, and a memory tester must be used to determine the acceptability of all memory cells in the memory array 10. I had to.

Therefore, in terms of shortening test time and reducing test costs, it has not been possible to achieve sufficient technical satisfaction, and it is difficult to find an accurate solution without complicating the circuit configuration or increasing the chip size. A means was needed.

The present invention provides a semiconductor memory device that solves the problems of the prior art, which are still insufficient in terms of shortening test time and reducing test costs.

(Means for Solving the Problems) In order to solve the above problems, the present invention comprises a redundant circuit for relieving defective memory cells and n (plural) subarrays each having m (plural) data outputs. In the semiconductor memory device, the test circuit is configured as follows: It is a commandment. That is, the test circuit includes at least n first coincidence/mismatch detection circuits that read m pieces of data written in each of the subarrays and detect coincidence/mismatch between the m pieces of data, respectively; one second match/mismatch detection circuit that reads n×m pieces of data written in all the subarrays and detects matches/mismatches between the n×m pieces of data; and output data of the memory array. , an output means for selectively outputting any one of the outputs of the n-th I-th coincidence/mismatch detection circuits and the outputs of the second coincidence/mismatch detection circuits.

(Operation) According to the present invention, since the semiconductor memory device is configured as described above, the first coincidence/mismatch detection circuit detects coincidence/mismatch of data output from each subarray, and detects coincidence/mismatch of data output from each subarray. It is possible to determine whether a defective memory cell exists. The second match/mismatch detection circuit detects match/mismatch between all data outputs from each subarray, making it possible to determine the quality of the entire memory array. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic block diagram of a semiconductor memory device showing an embodiment of the present invention.

This semiconductor memory device is composed of, for example, a large-capacity dynamic RAM (random access memory), and is divided into n subarrays 30-1 to 30-.
A memory array 30 for data storage consisting of n is provided. Each sub-array 30-1 to 30-n has m data outputs D1 to D, and includes a memory cell array 31 consisting of a plurality of memory cells and sense amplifiers, and a row decoder that selects rows and columns of the memory cell array 31. 32, a column decoder 13, and a redundant circuit 34 having a redundant memory cell, a redundant decoder, etc., respectively.

Data outputs D1 to D of each subarray 30-1 to 30-n
m is connected to the decoder 36 via input/output circuits 35-1 to 35-0, and is also connected to a test circuit 40 for on-chip testing.

The decoder 36 is a circuit that decodes the data output nX (Dt to D,) from each of the input/output circuits 35-l to 35-n and selects one of them.

The circuits 1 to 40 are each input/output circuit 35-1 to 35-n.
n match/mismatch detection circuits B50-1 to 1 for detecting whether the data outputs Dl to Do match each other.
50-n and Kawauchi's coincidence/mismatch detection circuit that detects whether all data outputs n×(D1 to D,) from all input/output circuits 35-1 to 35-n match. 60 and a switch circuit 70. switch circuit 70
is the decoder 36 based on the test signals TSI and TS2.
, the output of the coincidence/mismatch detection circuit Elt 50-n, or the output of the coincidence/mismatch detection circuit 70. For example, when the test signal TSI is at the "H" level, the output of the match/mismatch detection circuit 50-n is the "H" level, and when the test signal TS2 is at the "H" level, the output of the match/mismatch detection circuit 70 is the test signal TSI. TS2
When the signal is at the "L" level, the output of the decoder 36 is selected.

Each output signal of the match/mismatch detection circuit 50-5O-(n-1) and the switch circuit 70 has an output signal. 1
~Output buffer 80- for outputting each Don
1 to 80-n are connected.

Note that a write circuit (not shown) is connected to the input/output circuits 35-1 to 35-n.

FIG. 3 shows the match/mismatch detection circuit 50- in FIG.
1 to 50-n, 60, and a partial circuit diagram showing a configuration example of a switch circuit 70. FIG.

Each of the coincidence/mismatch detection circuits 50-1 to 50-n is composed of the same circuit. For example, the match/mismatch detection circuit 50-1 includes inverters 51, 5256a 56b,
P-channel type MOS transistors (hereinafter referred to as PMO3) 53a, 53b, N-channel type MOS transistors (hereinafter referred to as NMO3) >54a, 54b, 55a, 5
5b, and an Ex-NOR gate (hereinafter referred to as Ex-NOR) having a two-man powered Nand gate (hereinafter referred to as NAND) 57, etc.

In this Ex-NOR, data outputs D1 to D from the input/output circuit 35-1 are all "1 ++" or all "II"
This is a circuit in which the output is "1'° during OII, and the output is 0% at other times.

The match/mismatch detection circuit 60 includes inverters 61, 62, .
66a, 66b, PMO863a, 63b, NMO36
4a, 64b, 65a, 65b, and 2-person NAND
It is composed of Ex/NOR with 67 etc. This E
The x-NOR outputs II I ++ when the data output n×(Di-D,) from all input/output circuits 35-l to 35-n is all ↓ or all “0”, and outputs otherwise. is II O++.

The switch circuit 70 includes inverters 71 to 73, a two-man powered NOR gate (hereinafter referred to as NOR) 74, and a PMO3.
Analog switch 75 consisting of parallel connection of and NMO3
~77.

This switch circuit 70 is configured such that the test signal TSI is
When the test signal TS2 is at the "H" level, the analog switch 75 is turned on and conduction is established between the match/mismatch detection circuit 50-n and the output buffer 80-n, and when the test signal TS2 is at the "H" level, the analog switch 76 is turned on and the match/mismatch detection circuit 50-n is turned on. Conductivity is established between the mismatch detection circuit 60 and the output buffer 80-n. Further, when the test signals TS1 and TS2 are "L", the analog switch 77 is turned on via the N0R 74, and conduction is established between the decoder 36 and the output buffer 80-n.

Next, the operation will be explained.

First, when processing a relief program during probing, the test signal TSI is set to II HI+ level and the switch circuit 70 is set to match/mismatch detection circuit 50-n (j
Switch to ljJ. Then, by a write circuit (not shown), the 7
Write the same data of 11 ++ or 110 ++.

Next, write the written data to each subarray 30-1-30-
Each of the read data outputs D□ to D are successively read out. is sent from the input/output circuits B55-1 to 35-n. Then,
Each match/mismatch detection circuit 50-1 to 50-n detects whether or not each data output D1 to D, n match, and when they match (when there is no defective memory cell), +111+
is output, and when there is a mismatch (when there is a defective memory cell), ○''' is output.

These outputs are output from output buffers 80-1 to 80-(n-1
) are output in the form of output signals Do 1 to Don 1, and the switch circuit 70 and the output buffer 8
Output signal via 0-n. It is output in the form of n. Therefore, each output signal. By detecting the logic state of the sub-arrays 30-- and 30-- that have defective memory cells,
Judgments from 1 to 30-n can be made. Therefore, for subarrays 30-1 to 30-n having defective memory cells, defective addresses are detected using a memory tester or the like, and redundant memory cells in the redundant circuit 34 corresponding to the defective addresses are detected using a laser beam or the like. If the defective memory cell is replaced with a redundant memory cell, the test time and test cost can be reduced.

When performing a pass/fail determination after the completion of manufacturing of a semiconductor memory device, the test signal TS2 is set to "H" level and the switch circuit 70 is switched to the match/mismatch detection circuit 60 side. Data output n
x(Dt~Dffi>). Then, the match/mismatch detection circuit 60 outputs all data Hx(Dt~D,)
Detect matches/mismatches between This detection result is output in the form of an output signal Don via the switch &670 and the output buffer 80-n. Therefore, the output signal Do
By detecting the logical state of n, it is possible to easily and accurately determine the quality of the product.

In addition, in the case of normal read operation, test signals TS1 and T
S2 is set to "'L'° level and the switch circuit 70 is switched to the decoder 36 side. Then, all input/output circuits 35-1
~35-n read data output nX (D1~
- in D□) is selected by the decoder 36 and output to the outside via the switch 7o and the output buffer 80-n.

As described above, in this embodiment, the test circuit 4 has a redundant circuit 34 in addition to the test function for determining the quality of the product after it is completed.
Since a test function that allows on-chip testing in units has been added, the on-chip test function can be used even when determining a defective address during probing, thereby shortening test time and reducing test cost. Furthermore, since it is only necessary to add match/mismatch detection circuits 50-1 to 50-n, etc., the semiconductor memory device can be tested on-chip without complicating the circuit configuration or increasing the chip size. can be provided.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(a) In the above embodiment, the output means is composed of the switch circuit 70 and the output buffers 80-1 to 80-n. It is also possible to reduce power consumption by activating 8O-(n-1>.Similarly, the match/mismatch detection circuit 50-■~ 50-n, 60
By activating the configuration, it is possible to improve lower power consumption.

(b) Match/mismatch detection circuits 50-1 to 50-n,
60 may be constructed from other circuits such as an exclusive OR (Ex.OR), or the switch circuit 70 may be constructed from other circuits such as a gate circuit.

(C) The above semiconductor memory device has a static RA
It can also be applied to other semiconductor memories such as M.

(Effects of the Invention) As described above in detail, according to the present invention, the test circuit is provided with the first match/mismatch detection circuit, so the circuit configuration is not complicated, and the chip size can be significantly reduced. The on-chip test function can be used even when determining a defective address during probing without increasing the size, thereby making it possible to shorten test time and reduce test cost.

[Brief explanation of drawings]

FIG. 1 is a schematic structural block diagram of a semiconductor memory device showing an embodiment of the present invention, FIG. 2 is a schematic structural block diagram of a conventional semiconductor memory device, and FIG. 3 is a partial circuit diagram of the construction drawing. . 30... Memory array, 30-1 to 30-n.
...Sub array, 31...Memory cell array, 34...Redundant circuit, 40...Test circuit, 50-1 to 50-n, 60... ... Match/mismatch detection circuit, 7゜...Switch circuit, 8
0-t~80-n... times output buffer.

Claims (1)

[Claims] A memory array consisting of n (plural) subarrays each having a redundant circuit for relieving defective memory cells and m (plural) data outputs, and Read the data and match/match the data
and a test circuit for detecting a mismatch, the test circuit reading the m pieces of data written in each of the subarrays and detecting a match/mismatch between the m pieces of data, respectively.
a first match/mismatch detection circuit; and a first match/mismatch detection circuit that reads out the n×m data written to all the subarrays and detects match/mismatch between the n×m data.
one of the output data of the memory array, the output of the n first match/mismatch detection circuits, and the output of the second match/mismatch detection circuit; What is claimed is: 1. A semiconductor memory device comprising: output means for selectively outputting one of the two.