JPH0359730U - - Google Patents
Info
- Publication number
- JPH0359730U JPH0359730U JP11966189U JP11966189U JPH0359730U JP H0359730 U JPH0359730 U JP H0359730U JP 11966189 U JP11966189 U JP 11966189U JP 11966189 U JP11966189 U JP 11966189U JP H0359730 U JPH0359730 U JP H0359730U
- Authority
- JP
- Japan
- Prior art keywords
- display
- search
- inhibiting
- synthesizer tuner
- pll circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002401 inhibitory effect Effects 0.000 claims 2
- 208000003580 polydactyly Diseases 0.000 claims 1
- 230000003321 amplification Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Circuits Of Receivers In General (AREA)
Description
第1図及び第2図の考案のシンセサイザチユー
ナの表示装置の実施例を示し、第1図はブロツク
図、第2図は要部のフローチヤートである。
主な符合の説明、2……フロントエンド、3…
…PLL回路、4……中間周波数増幅回路、6…
…受信感度検出手段、7……マイクロコンピユー
タ、8……表示器、8a……整数部、8b……少
数部、9……サーチ釦。
An embodiment of the display device of the synthesizer tuner of the invention shown in FIGS. 1 and 2 is shown, with FIG. 1 being a block diagram and FIG. 2 being a flowchart of the main parts. Explanation of main codes, 2...Front end, 3...
...PLL circuit, 4...Intermediate frequency amplification circuit, 6...
...Reception sensitivity detection means, 7...Microcomputer, 8...Display unit, 8a...Integer part, 8b...decimal part, 9...Search button.
Claims (1)
な放送局の周波数をサーチするように構成したシ
ンセサイザチユーナにおいて、 サーチ中は受信周波数を表示する複数の桁のう
ち最下位の桁の表示を禁止する表示禁止手段を設
けたことを特徴とするシンセサイザチユーナの表
示装置。[Claim for Utility Model Registration] In a synthesizer tuner configured to search for receivable broadcasting station frequencies by sequentially changing the frequency division ratio of the PLL circuit, during the search, multiple digits indicating the received frequency are displayed. A display device for a synthesizer tuner, characterized in that a display inhibiting means is provided for inhibiting display of the lowest digit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989119661U JP2502064Y2 (en) | 1989-10-16 | 1989-10-16 | Synthesizer tuner |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989119661U JP2502064Y2 (en) | 1989-10-16 | 1989-10-16 | Synthesizer tuner |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0359730U true JPH0359730U (en) | 1991-06-12 |
JP2502064Y2 JP2502064Y2 (en) | 1996-06-19 |
Family
ID=31667772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989119661U Expired - Lifetime JP2502064Y2 (en) | 1989-10-16 | 1989-10-16 | Synthesizer tuner |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2502064Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5862921A (en) * | 1981-10-09 | 1983-04-14 | Nec Corp | Broadcasting receiver |
JPS6193883U (en) * | 1984-11-26 | 1986-06-17 |
-
1989
- 1989-10-16 JP JP1989119661U patent/JP2502064Y2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5862921A (en) * | 1981-10-09 | 1983-04-14 | Nec Corp | Broadcasting receiver |
JPS6193883U (en) * | 1984-11-26 | 1986-06-17 |
Also Published As
Publication number | Publication date |
---|---|
JP2502064Y2 (en) | 1996-06-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |