JPH0358407A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0358407A JPH0358407A JP19494989A JP19494989A JPH0358407A JP H0358407 A JPH0358407 A JP H0358407A JP 19494989 A JP19494989 A JP 19494989A JP 19494989 A JP19494989 A JP 19494989A JP H0358407 A JPH0358407 A JP H0358407A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- code
- chips
- arrangement information
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000000694 effects Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野〕
本発明は多品種小量生産の半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device of a wide variety of products in small quantities.
し従来の技術〕
近年LSIの集積規模が膨大になり、特に論理回路では
カスタム化が進行し、システムーオンーチップと言われ
る水準に到達している。BACKGROUND ART In recent years, the scale of integration of LSIs has become enormous, and customization of logic circuits in particular has progressed, reaching a level called system-on-chip.
このように多品種小量生産が進んでくると、1品種1ロ
ットで生産することさえ、ロフトサイズが極めて小さく
なり、コス1・の上昇を招いている。As high-mix, low-volume production progresses, the loft size becomes extremely small even when one product is produced in one lot, leading to an increase in cost.
主として研究開発の手段とされていた、一枚の半導体基
板(ウエーハ)に複数の異なるチップを混在させる方式
が、つぎのような方法で生産現場でも検討されているが
、日の目を見るに至っていない。The method of mixing multiple different chips on a single semiconductor substrate (wafer), which was primarily considered as a research and development method, is being considered at production sites using the following method, but it has not yet seen the light of day. .
第lの方法はあらかじめ決定してあるチップの配列を選
ぶ。The first method selects a predetermined chip arrangement.
第2の方法はチップ毎に品種コードをパターニングして
おき、これを認識しながら生産する。The second method is to pattern a type code for each chip and produce it while recognizing this pattern.
第3の方法はウエーハの番号からホストコンピュータで
生産管理する。The third method is to use a host computer to manage production based on wafer numbers.
前項に述べた品種混載にはつぎのような問題があった.
第l゛の固定したチップ配列では、生産量をフレキシブ
ルにコントロールできない。The mixed product stocking described in the previous section had the following problems. With the l'th fixed chip arrangement, the production volume cannot be flexibly controlled.
第2のチップの品種コードをその都度識別しなければな
らないのでは、極端な生産能率の低下をもたらす。If the type code of the second chip must be identified each time, production efficiency will be extremely reduced.
第3のホストコンピュータに頼るのは、ホストコンピュ
ータの情報処理負荷を増して、実用的・経済的範囲を逸
脱してしまう。Relying on a third host computer increases the information processing load on the host computer and goes beyond the practical and economical range.
本発明の半導体装置の製造方法は、半導体基板上に異な
ったチップが混在する半導体装置の製造方法において、
少なくと61チップにチップの品種コードを示す英数字
または記号を記すことにより生産管理を行なうものであ
る。The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which different chips are mixed on a semiconductor substrate.
Production control is performed by marking at least 61 chips with alphanumeric characters or symbols indicating the chip type code.
L実施例〕
本発明の一実施例について、第1図および第2図を参照
して説明する.
例えば品種コード001.002、003、004、0
05の5種類のチップをそれぞれ2:4:3:2:1の
比率で生産すると想定する。L Embodiment] An embodiment of the present invention will be described with reference to FIGS. 1 and 2. For example, product code 001.002, 003, 004, 0
It is assumed that five types of chips of 05 are produced at a ratio of 2:4:3:2:1, respectively.
チップNo.l〜2にはコード001の、チップNO.
3〜6にはコード002の、チップNo7〜9にはコー
ド003の、チツ7N 0 . 1 0〜l1にはコー
ド004の、チッ7N1).12にはコードO 0 5
の品種が割り当てられている。Chip no. Chip No. 1-2 has code 001.
Code 002 for chips No. 3-6, code 003 for chips No. 7-9, chip 7N 0 . 1 0-l1 has code 004, 7N1). 12 has code O 0 5
varieties have been assigned.
この配列情報が第1図の半導体基板lの配列情報チップ
2(チップNo.O)に記録されている。This array information is recorded on the array information chip 2 (chip No. O) of the semiconductor substrate 1 in FIG.
配列情報記録チップ2には、第2図のように配列情報記
録チップ表示マーク3とチップ毎の品種コード4が記録
されている。On the array information recording chip 2, as shown in FIG. 2, an array information recording chip display mark 3 and a type code 4 for each chip are recorded.
記録の方法としては、フ才トレジスI・工程で焼き付け
るほか、レーザーマーカーで刻印することもできる。As a recording method, in addition to printing using the Fusei Tregis I process, it can also be engraved with a laser marker.
各工程ではまずチップ0の情報を読み取り、それぞれチ
ップの品種コードに対応した加工を施して次工程に送る
ことになる。In each process, information on chip 0 is first read, each chip is processed in accordance with its type code, and then sent to the next process.
同様に、選別や検査などのテスト工程もチップ毎にプロ
グラムしておくことができる。Similarly, test processes such as sorting and inspection can be programmed for each chip.
ここでは品種コードを数字としたが、英数字などの文字
を用いることもできる。Here, the product code is a number, but alphanumeric characters can also be used.
さらにガードバー、プリフィックスキャラクタとチェッ
クキャラクタとを含むバーコードの縮小版で代用するこ
ともできる。Furthermore, a reduced version of the barcode including guard bars, prefix characters and check characters may be substituted.
(発明の効果〕
半導体基板(ウェーハ)上に複数の異なる品種のチップ
を混在させて製造する方法として、その配列情報を特定
のチップに記録しておくことにより、ホストコンピュー
タの情報負荷を最小限に抑制して、ウェーハナッ1内の
チップ配列の自由度を確保することができる。(Effects of the invention) As a method for manufacturing chips of different types on a semiconductor substrate (wafer), by recording the arrangement information on a specific chip, the information load on the host computer is minimized. The degree of freedom in chip arrangement within the wafer nut 1 can be ensured by suppressing the number of chips.
第1図は本発明の一実施例の半導体基板《ウェーハ〉を
示す平面図、第2図はその中の配列情報記録チップを示
す平面図。
1・・・半導体基板(ウェーハ)、2・・・配列情報記
録チップ、3・・・配列情報記録チップ表示マーク、4
・・・品種コード。FIG. 1 is a plan view showing a semiconductor substrate (wafer) according to an embodiment of the present invention, and FIG. 2 is a plan view showing an array information recording chip therein. 1... Semiconductor substrate (wafer), 2... Array information recording chip, 3... Array information recording chip display mark, 4
... Variety code.
Claims (1)
製造方法において、少なくとも1チップにチップの品種
コードを示す英数字または記号を記して、チップの配列
を記録することを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which different chips are mixed on a semiconductor substrate, characterized in that alphanumeric characters or symbols indicating a chip type code are written on at least one chip to record the arrangement of the chips. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19494989A JPH0358407A (en) | 1989-07-26 | 1989-07-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19494989A JPH0358407A (en) | 1989-07-26 | 1989-07-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0358407A true JPH0358407A (en) | 1991-03-13 |
Family
ID=16333009
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19494989A Pending JPH0358407A (en) | 1989-07-26 | 1989-07-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0358407A (en) |
-
1989
- 1989-07-26 JP JP19494989A patent/JPH0358407A/en active Pending
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