JPH0358241A - Debug tool - Google Patents

Abstract

PURPOSE:To operate an address coincidence detecting function by a small number of logical iC by allowing an external RAM for outputting the corresponding latch selection data at the time when it is brought to access by one of plural specific addresses to have a coincidence detecting function. CONSTITUTION:In an external RAM 5, prescribed latch selection data is written in advance in an area brought to access by a specific address, and when it is brought to access by a specific address in the course of executing an actual program, the corresponding latch selection data is read out, therefore, it is decided to be a coincidence. In the case of coincidence, a microcomputer inside RAM is also brought to access simultaneously by its specific address, and display data 6 is read out therefrom, therefore, it is inputted to a selected latch 4. The same thing is executed with regard to each specific address, and when the contents of all the latches are displayed, when a program is normal, the display data corresponding to all the specific addresses are displayed. In such a way, debug of a microcomputer software can be executed by a small number of logical iC.

Description

[Detailed Description of the Invention] [Already Required] The purpose of this invention is to enable the address matching detection function to be realized with a small number of logical ICs in relation to the debugging program of microcomputer software, and to detect multiple specific addresses used in microcomputer programs. a plurality of latches each holding a plurality of display data read from an internal memory by a plurality of latches; an external memory that outputs corresponding latch selection data when accessed at one of the plurality of specific addresses; A decoder for decoding and selecting a latch from among the plurality of latches to take in the display data, and an address designation switch for instructing the microcomputer to the specific address are provided.

(Industrial application field) The present invention relates to a microcomputer software debugging tool.

Whether or not a microcomputer program (simply referred to as microcomputer software) operates normally can be determined by whether or not it actually passes through some specific addresses when the program is executed.

The debug tool allows this determination to be made visually.

[Prior Art] FIG. 3 shows an example of a conventional debug tool. In the figure, 1 is a microcomputer (hereinafter abbreviated as microcomputer), 2 is an address coincidence detection circuit, 3 is a specific address designation switch, and 4 is a display data latch circuit.

In this debug tool, when the microcomputer 1 selects a specific address specified by the switch 3 while executing an instruction, a match signal is generated since the address is also input to the match detection circuit 2. This coincidence signal is used as a latch signal of the latch circuit 4, and at this time, the display data of the specific address outputted by the microcomputer 1 is latched. Therefore, by displaying the contents of the latch 4, it is possible to visually determine whether or not the specific address designated by the switch 3 has been correctly passed.

[Problem to be solved by the invention]

However, the configuration shown in FIG. 3 requires several logical iCs per address, so if a plurality of points are set as specific addresses to be checked, several tens of logical iCs are required.

The present invention uses external RAM (random access memory)
The aim is to reduce the number of required iCs by providing a match detection function to the iC.

(Means for Solving the Problems) The present invention provides a plurality of latches each holding a plurality of display data read from an internal memory according to a plurality of specific addresses used in a microcomputer program, and ]・An external memory that outputs the corresponding latch selection data when accessed by one of the responses;
The present invention is characterized by comprising a decoder that decodes the latch selection data and selects a latch from among the plurality of latches to take in the display data, and an address designation switch that instructs the microcomputer to the specific address. .

[Operation] Predetermined latch selection data is written in advance in an area of external memory, that is, an external RAM, which can be accessed with a specific address, and this can be handled by accessing this with the specific address during actual program execution. Since the latch selection data is read out, it is assumed that they match (normal). If this is not the case, valid latch selection data will not be read out no matter how much access is made at an address other than the specific address, and in this case, the result will be invincible (abnormal).

If there is a match, the internal RAM of the microcomputer is also accessed at the same time using that specific address, and display data is read therefrom, so that it is taken into the selected latch.

If the same thing is done for each specific address and the contents of all the latches are displayed, if the program is normal, display data corresponding to all the specific addresses will be displayed.

On the other hand, when there is an abnormality, some specific addresses are not passed through, so the display data is missing, and from this it is possible to visually determine whether the program is normal or abnormal.

Since the external RAM used in such a debugging tool can perform 256 matches and detections even with 8 bits, the number of ICs used can be far smaller than in the past.

[Embodiment] Fig. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a microcomputer, l1 is its internal RAM, 3 is an address designation switch, and 4 1+ 4 Z+... are a plurality of A latch circuit, 5 an external dual baud (DP) RAM, and 6 a decoder.

DPRAM 5 has a physically separated write port ■ and read port ■. When accessed through port ■, external data (latch selection data in this case) can be written, and port ■ The internal data can be read by accessing with .

The microcomputer 1 has a special write program for writing latch selection data into the DPRAM 5, and writes unique latch selection data to a specific address indicated by the address designation switch 3. This latch selection data includes, for example, a plurality of address designation switches 3, and the specific addresses designated by each are A 1 , A 2 , A 2 , ?・・・
...When closed, latch 4 1+ 4 21...
... is used in order, and its latch number #1,
This is data representing #2, . . . . Decoder 6
decodes the latch selection data read out from the DPRAM 5, converts it into latch numbers #1, #2, . . . and selects one of the latches 442, .

After the microcomputer 1 executes the above-mentioned writing program,
Execute the program to be debugged. All addresses output from the microcomputer 1 while executing this program are input to the port 2 as read addresses of the DPRAM 5 (the port 2 is not used). As a result, read data is sequentially output from the DPRAM 5, but when decoded by the decoder 6, the latch 4 l+
4, 21, . . . can be selected only at the specific address to which the latch selection data is written by the above-mentioned write program.

To ensure this, unmatched data that does not allow any latch to be selected is written in advance to all addresses in the DPRAM 5, and then matched data that allows only a specific address to be selected is written. It's good to do this.

When running the program to be debugged, microcontroller 1
accesses internal RAMI1 like other programs. Since that address is the same as the read address for accessing DPRAM 5, for example, #erratch4
, to select a specific address A. The display data D, read from the internal RAMIl is taken into the #1 latch 41,
Further, the display data D2 read from the internal RAM II at the specific address A2 that selects the #2 latch 4 is the #2 latch 4. be taken into account.

Figure 2 is an explanatory diagram of this, showing #l data in DPRAM, #
2 data are #lrasochi4. , #2 latch 4.
This is latch selection data for selecting.

The same address A,,A, of internal RAM has #1 latch 4.
, #2 latch 4■ display data DD2 is stored. Note that this display data DD2 is not specially set for display, but is general data that is rewritten during operation.

In the configuration shown in Figure 1, is the internal RAMII microcontroller? Since the external logic IC is built in latch 4, 4■
, . . ., only the decoder 6 and the DPRAM 5. Here, if the decoder 6 is 8 bits, the DPRAM
5 can store latch selection data for 256 8-bit addresses. This address match detection function corresponds to several dozen logic ICs forming the match detection circuit 2 in FIG.

DPRAM 5 connects the address bus to microcomputer internal RAM 1.
I focused on the point that the read data is output to a physically separated data path even if it is shared with l, but it is possible to do the same thing even if you use normal RAM by separating the data path. be. Furthermore, the latch selection data can also be written using another microcomputer.

〔Effect of the invention〕

As described above, according to the present invention, there is an advantage that debugging of microcomputer software can be realized with a small number of logical iCs.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of a memory used in the present invention, and FIG. 3 is a diagram of a conventional debugging unit. In the figure, 1 is a microcomputer, l'l is an internal RAM
, 3 is the addressing switch, 4 is the latch, 5 is the external R
AM,6 is a decoder. Applicant Fujitsu Ten Ltd.

Claims (1)

[Claims] 1. A plurality of latches (4) each holding a plurality of display data read from an internal memory according to a plurality of specific addresses used in a microcomputer program.
an external memory (5) that outputs corresponding latch selection data when accessed by one of the plurality of specific addresses; and an external memory (5) that decodes the latch selection data and extracts the display data from among the plurality of latches. A debugging tool comprising: a decoder (6) for selecting a latch to be loaded; and an address designation switch (3) for instructing the microcomputer to the specific address.