JPH0358233A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To freely set the sequence, etc., of an interruption factor by setting an address bus and a data bus of a storage element as external terminals by a non-volatile and rewritable storage element for constituting a setting means for an interruption level, etc., so that the contents of the setting means in an interruption processing can be tested by using this external terminal. CONSTITUTION:A setting means 2 for setting an interruption level, a priority level, etc., to an interruption element from a logic circuit 4 for executing a logical operation required for an interruption control is constituted of a nonvolatile and rewritable storage element. Also, it is constituted so that an address bus and a data bus of this storage element are set as external terminals, so that the contents of the setting means 2 in an interruption processing can be tested by using this external terminal. In such a way, since a test function is added, it is possible flexibly with an interruption factor, and the sequence of the interruption factor, the level, etc., can be set freely.

Description

[Detailed Description of the Invention] [Summary] Regarding the interrupt control circuit, the order and level of interrupt factors can be set freely, the response can be flexibly handled, the test is easy and takes a short time, and the test can be easily performed using a microcontroller. The purpose of this circuit is to expand the scope of use and provide an interrupt control circuit that can respond to user specifications in a short period of time. In an interrupt control circuit in which an interrupt level, a priority level, etc. for an interrupt request are set by a setting means, the setting means is constituted by a nonvolatile rewritable memory element, and at least an address bus and a data bus of the memory element are configured. is an external terminal,
The external terminal is used to test the contents of the setting means in interrupt processing.

(Industrial Application Field) The present invention relates to an interrupt control circuit, and more particularly to an interrupt control circuit applied to a one-chip microcontroller.

In recent years, users have been requesting multifunctional L-chip microcontrollers, and it is necessary to adapt interrupt orders, levels, etc. to meet such requests, and to create them in a short period of time.

[Conventional technology]

In the interrupt control circuit of a conventional one-chip microcontroller, when an interrupt request is received, the interrupt processing is executed after saving the program counter and program status word, and when returning from the interrupt, the interruption point of the saved program is executed. information is being restored. Further, the delta penetration level is set by a register or the like.

[Problem to be solved by the invention]

However, in such conventional interrupt control circuits, the interrupt level etc. are set by hardware using a register, so the order and level of interrupt factors cannot be set freely. However, there was a problem in that it was not possible to respond flexibly.

Another problem is that testing (verification) of interrupt control is not easy and takes time. Therefore, the scope of use of the chip has been narrowed, and it has been difficult to produce chips according to user specifications in a short period of time.

Therefore, the present invention allows the order, level, etc. of interrupt factors to be set freely, allows for flexible response, is easy to test, takes a short time, and expands the scope of use of the microcontroller, allowing user specifications to be achieved in a short period of time. The purpose of the present invention is to provide an interrupt control circuit that can respond to interrupt requests.

[Means to solve the problem]

In order to achieve the above objectives, the interrupt control circuit according to the present invention interrupts the normal processing of the CPU and shifts to interrupt processing in response to an interrupt request, and also controls the interrupt level, priority level, etc. for the interrupt request. In the interrupt control circuit set by a setting means, the setting means is constituted by a non-volatile rewritable memory element, and at least an address bus and a data bus of the memory element are used as external terminals, and the interrupt control circuit is configured by using the external terminals. Care should be taken to ensure that the contents of the setting means in interrupt processing can be tested.

(Function) In the present invention, the setting means is constituted by a non-volatile rewritable storage element such as EFROM, and the interrupt level and priority level can be set freely. Further, the memory element is provided with an external terminal, and the setting contents of the setting means are externally tested by executing a test mode using this external terminal.

Therefore, it is possible to respond flexibly to interrupt factors, and test time is also shortened, expanding the scope of use of the microcontroller.

[Explanation of principle]

First, the principle of the present invention will be explained. FIG. 1 is a diagram explaining the principle of the present invention. In this figure, ■ is a selector that switches the signal input and address bus corresponding to an interrupt request, 2 is an EPROM cell (corresponding to a setting means) for setting and storing interrupt levels, priority levels, etc.;
4 is a selector that switches the read/write operation to the EPROM cell 2 and the signal path for normal operation; 4 is a logic circuit that performs logical operations necessary for interrupt control; and 5 is a logic circuit that outputs an interrupt control signal; 5 is an EPROM This is a selector that switches between sending and receiving read/write data from the cell 2 and the test mode. Note that the address bus and data bus of the EFROM cell 2 are external terminals.

In the above arrangement, first, setting of interrupt conditions such as interrupt level and priority level is performed by writing the contents to the EPROM cell 2, and this becomes a write operation and a read operation (checking of the written contents). Also, when an interrupt request is received, the operation of reading the above settings in response to this request is execution of an interrupt.
This is normal operation.

Read/write operations and normal operations to the EFROM cell 2 are performed in independent modes, and the bus during each operation is as follows.

(1) Read/write operation The address bus is selected by the selector 1, and the bus becomes the address bus - PROM cell 2 -> selector 3 -> selector 5 -> data.

As a result, the setting contents can be freely determined according to the specifications of the interrupt request from the user, and a flexible response can be achieved. Incidentally, since conventional systems have a hardware configuration, they do not have this degree of software flexibility.

(II) During normal operation, the signal input corresponding to the interrupt request is selected by the selector 1, resulting in a path of signal input - EFROM cell 2 - selector 3 - logic circuit 4 - signal output. As a result, in response to an external interrupt request, the corresponding interrupt setting is determined by the contents of the EPROM cell 2, and the logic circuit 4
performs logical operations necessary for interrupt control and sends it to the CPU side as a signal output.

On the other hand, when executing the test mode for verifying the interrupt control function, the address bus of EFROM cell 2,
Since the data bus is an external terminal, this external terminal is used to form a path of address bus → EPROM cell 2 → selector 3 → logic circuit 4 → selector 5 → data, thereby outputting to the CPU side. The interrupt level, etc. to be output is output as data to the outside. Therefore, the combination of interrupts can be checked easily and in a short time, and the amount of circuitry does not need to increase much.

As described above, the scope of use of the microcontroller is expanded, and an interrupt control circuit that meets user specifications can be provided in a short period of time.

(Example) Next, an embodiment of the present invention based on the above principle will be described.

FIG. 2 is a block diagram of an l-chip microcontroller 11 to which an interrupt control circuit according to the present invention is applied. In FIG. 2, 12 is a CPU, 13 is an interrupt control circuit, and the interrupt control circuit 13 is included in a part of the CPU block 14.
Interrupt request (IRQ) to CPU12
), priority level health input (Nl) and output (
No) and vector address (VA) output signals are exchanged.

The interrupt control circuit 13 also includes resources 15a to 15n (
For example, interrupt request signals from module blocks such as serial I/O and timers are input. on the other hand,
Boards 6 to 18 are connected to the interrupt control circuit 13, and serve as terminals for address input, data input/output, and read/write control. Further, a signal for controlling the test mode is input to the interrupt control circuit 13. Note that the address bus and data bus are dedicated buses.

FIG. 3 is a block diagram showing the detailed structure of the interrupt control circuit 13. In FIG. 3, 21 is a selector that selects an interrupt factor and an address bus, 22 is an interrupt priority sorting circuit constructed of EPROM cells, 23 is a selector, and 24 is a priority and a mask that masks the priority. The circuit includes a vector address decoder 25 that outputs a vector address, a selector 26, a data bus selector 27, a test mode controller 28, and a priority level decoder circuit 29 that decodes priority level 1, which is composed of EPROM cells. things, 30
31 is a selector, 3l is a priority level output control circuit, 32 and 33 are selectors, and 34 is a priority mask circuit, which are constructed of the same EFROM cells.

The interrupt priority sorting circuit 22, priority level decoder circuit 29 and priority mask circuit 34
is guarding the setting means 35.

In the above configuration, the effects of each operation will be explained.

First, setting means 3 consisting of EPROM cells from the outside.
Set the interrupt level, priority level, etc. to 5. Specifically, in the EPROM mode, the interrupt priority sorting circuit 22 and the priority level decoder circuit 2
The above data is written in the EPROM cells of 9 and the priority mask circuit 34 in advance. Next, the interrupt processing program is run. That is, the resource 15a
When the interrupt request from -15n becomes active, only the interrupt set above becomes active in the interrupt control circuit 13, the priority level and vector address at this time are output to the CPU 12, and the interrupt processing is executed. Ru.

The specific operation of the interrupt control circuit l3 is as follows. When each interrupt factor is input to the interrupt control circuit l3, it first passes through the selector 2l and then is rearranged by the interrupt priority sorting circuit 22 in the order of interrupt priority set in advance. and,
The output from the interrupt priority sorting circuit 22 is input to the mask circuit 24 via the selector 23, and it is only from the output of the mask circuit 24 that it becomes clear which interrupt has been permitted. A vector address is output from the vector address decoder 25 by the permitted interrupt, and a priority level is output from the priority level output control circuit 3l via the selector 26, the priority level decoder circuit 29, and the selector 3o. Further, the priority level is input from the priority level output control circuit 3l to the priority mask circuit 34 via the selector 33, and the output of the selector 32 disables interrupt factors other than the currently input interrupt. Interrupt processing is performed in this manner.

2] The two test mode is provided for checking the function of the interrupt control circuit 13 alone. Resource 15a-1
The interrupt request signal from 5n and the address bus can be switched manually from the external terminal, and the C from the data bus.
The hector address and priority level output to the PU 12 side are output from the data hash to the outside. This makes it possible to easily check the combination of interrupts in a short time, and also to reduce the increase in the amount of circuitry.

Specifically, it is as follows. First, the interrupt priority sort circuit 22, the priority level decoder circuit 29, and the priority mask circuit 34 are a matrix of EFROM cells, and these cells can be read/written in the EFROM mode. Now, by setting test mode during EFROM mode, IEPR
Using the address bus and data bus when writing OM,
Interrupt operation is performed directly from an external pin. The test mode procedure in this case is shown in the flowcharts of FIGS. 4 and 5.

Figure 4 shows test 1. First, P1 performs initial settings for transitioning to the test mode, P2 activates all outputs of the interrupt priority sorting circuit 22, and P3 activates external outputs. The priority level is artificially set manually from the address bus. The input destination is a priority level output control circuit 3l, which outputs the output of the vector address decoder 25 and the priority level from the priority level output control circuit 31 from the data bus. Check whether the priority level is as expected and verify its functionality. Next, at P, it is determined whether or not all priority levels have been verified to the last, and if they are not the last, the routine returns to P3 and is repeated.

FIG. 5 shows test 2. First, initial settings are made with PI+, all outputs of the priority mask circuit 34 are activated with p+2, and interrupt factor signals are simulated from the external address bus with PI3. type. The input destination is the interrupt priority sorting circuit 22 from the selector 2l, the output of the vector address decoder 25 and the priority level from the priority level output control circuit 31 are outputted from the data bus, and the P. Verify the priority order functionality. At PI, it is determined whether or not the verification of the last interrupt factor has been completed, and if it is not the last, the process returns to PI3.

By adding the above test function, as described in the explanation of the principle of the present invention, it is possible to check combinations of interrupts easily and in a short period of time.

As a result, the scope of use of the microcontroller 11 can be expanded to meet user specifications in a short period of time.

〔Effect of the invention〕

According to the present invention, it is possible to freely set the order, level, etc. of interrupt factors, and it is possible to respond flexibly to interrupts.

In addition, it is easy to test the interrupt setting conditions and the test time can be shortened, expanding the scope of use of the Chiseop microcontroller that includes the interrupt control circuit according to the present invention, and enabling user specifications in a short period of time. can be met.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIGS. 2 to 5 are diagrams showing an embodiment of the interrupt control circuit according to the present invention, and FIG. Figure 3 is a detailed diagram of the interrupt control circuit of the microcontroller, Figure 4 is a flowchart showing the processing procedure for test 1, and Figure 5 is a flowchart showing the processing procedure for test 2. be. 1, 3, 5, 2l, 23, 26, 30, 32, 33...
... Selector, 2 ... EPROM cell (setting means), 4 ... Logic circuit, 11 ... Microcontroller, 12 ...
...cpu, 13...interrupt control circuit, 14...cpu block, 15a-tsn...resource, 16-18...
...Boat, 22...Interrupt priority sorting circuit, 24...
...Mask circuit, 25...Vector address decoder, 27...
... Data bus selector, 28 ... Test mode controller, 29 ... Priority level decoder circuit, 31 ... Priority level output control circuit, 34 ... ... Briority mask circuit, 35... Setting means. 1. Flowchart showing the processing procedure of test 1 in the embodiment shown in FIG. 4.

Claims (1)

[Scope of Claims] An interrupt control circuit that interrupts normal processing of a CPU and shifts to interrupt processing in response to an interrupt request, and sets an interrupt level, priority level, etc. for the interrupt request by a setting means. , the setting means is constituted by a nonvolatile rewritable storage element, and at least an address bus and a data bus of the storage element are used as external terminals, and the contents of the setting means in interrupt processing are tested using the external terminals. An interrupt control circuit characterized in that it is configured to enable.