JPH0358206B2 - - Google Patents

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Publication number
JPH0358206B2
JPH0358206B2 JP26202984A JP26202984A JPH0358206B2 JP H0358206 B2 JPH0358206 B2 JP H0358206B2 JP 26202984 A JP26202984 A JP 26202984A JP 26202984 A JP26202984 A JP 26202984A JP H0358206 B2 JPH0358206 B2 JP H0358206B2
Authority
JP
Japan
Prior art keywords
converter
quantization
analog signal
bit
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP26202984A
Other languages
Japanese (ja)
Other versions
JPS61140222A (en
Inventor
Riichi Nakura
Naoshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP26202984A priority Critical patent/JPS61140222A/en
Publication of JPS61140222A publication Critical patent/JPS61140222A/en
Publication of JPH0358206B2 publication Critical patent/JPH0358206B2/ja
Granted legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はA/D変換回路に関し、特に切替によ
つて複数のアナログ信号の粗い量子化と一つのア
ナログ信号の精密量子化とに使用できるA/D変
換回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an A/D conversion circuit, and in particular can be used for coarse quantization of a plurality of analog signals and fine quantization of one analog signal by switching. It relates to an A/D conversion circuit.

〔従来の技術〕[Conventional technology]

アナログ信号を量子化してデイジタル信号とし
て伝送するデイジタル伝送方式は各方面で広く使
用されており、人工衛星から各種の観測データを
伝送する場合にも使用される。地球観測衛星のよ
うな人工衛星には複数の観測器が搭載され、これ
らで観測された観測データの中には、例えば3ビ
ツトの粗い量子化によつて伝送すればよい情報も
あれば、6ビツトの精密量子化を要する情報もあ
る。更に、これらの観測データは必ずしも同時に
観測して伝送されるわけではなく、衛星電力の制
約から時間的に交互に観測を行うように構成され
ている場合が少なくない。このような場合、同一
の伝送条件(例えば60Mb/s)により同じサン
プリング周波数(例えば10MHz)の6ビツトのデ
ータ1組((例えば光学センサによる観測デー
タ)、又は3ビツトのデータ2組(例えばマイク
ロ波合成開口レーダの観測データ)を伝送するこ
とができる。従来、このようなビツト数の異なる
量子化を行う場合には、それぞれに別々のA/D
変換器(6ビツト1台と3ビツト2台)を用意す
るか、又は、精密量子化を行うA/D変換器の出
力の上位ビツトのみを使用して粗い量子化にも使
用してA/D変換器を1台節約する(6ビツト,
3ビツト各1台)ことが行われている。
Digital transmission methods, which quantize analog signals and transmit them as digital signals, are widely used in various fields, and are also used when transmitting various observation data from artificial satellites. Artificial satellites such as earth observation satellites are equipped with multiple observation instruments, and some of the observation data obtained by these instruments can be transmitted using coarse quantization of, for example, 3 bits; Some information requires precise quantization of bits. Furthermore, these observation data are not necessarily observed and transmitted simultaneously, but are often configured to be observed alternately over time due to satellite power constraints. In such a case, one set of 6-bit data (for example, observation data from an optical sensor) or two sets of 3-bit data (for example, data from a micro- Conventionally, when performing quantization with different numbers of bits, a separate A/D was used for each.
Either prepare converters (one 6-bit and two 3-bit), or use only the upper bits of the output of the A/D converter that performs fine quantization and also use it for coarse quantization. Saves one D converter (6 bits,
3 bits each).

〔発明が解決すべき問題点〕[Problems to be solved by the invention]

上述の従来の構成においては、6ビツトの量子
化を行うときは3ビツトのA/D変換器を使用せ
ず、3ビツトの量子化を行うときは6ビツトの
A/D変換器を全く使用しないか下位3ビツト分
を無駄に動作させていることになり、制約の厳し
い衛星搭載用の機器にあつては、重量および消費
電力設計上に無駄があるという問題点がある。本
発明の目的は、複数のアナログ信号の粗い量子化
と一つのアナログ信号の精密量子化とに切替えて
使用でき、上述した重量および電力消費の無駄を
低減できるA/D変換回路を提供することであ
る。
In the conventional configuration described above, when performing 6-bit quantization, no 3-bit A/D converter is used, and when performing 3-bit quantization, no 6-bit A/D converter is used. Otherwise, the lower 3 bits will be wasted, and in the case of equipment mounted on a satellite, which has strict restrictions, there is a problem in terms of weight and power consumption design. An object of the present invention is to provide an A/D conversion circuit that can be used by switching between coarse quantization of a plurality of analog signals and fine quantization of one analog signal, and which can reduce the above-mentioned waste of weight and power consumption. It is.

〔問題を解決するための手段〕[Means to solve the problem]

本発明によるA/D変換回路は、アナログ信号
を量子化してデイジタル信号に変換する少なくと
も二つの第1及び第2のA/D変換器と、前記第
1のA/D変換器の出力をアナログ信号に変換し
て前記第1のA/D変換器の入力の第1のアナロ
グ信号との差信号を求める差信号発生手段と、前
記第2のA/D変換器を前記差信号の量子化と前
記第1のアナログ信号とは独立な第2のアナログ
信号の量子化とに切替え使用する切替手段とを備
えることによつて構成される。
The A/D conversion circuit according to the present invention includes at least two first and second A/D converters that quantize an analog signal and convert it into a digital signal, and converts the output of the first A/D converter into an analog signal. difference signal generating means for converting into a signal to obtain a difference signal between the first analog signal and the first analog signal input to the first A/D converter; and a switching means for switching between quantization of a second analog signal independent of the first analog signal.

〔実施例〕〔Example〕

次に図面を参照して本発明を詳細に説明する。
第1図は本発明の一実施例のブロツク図で、それ
ぞれ3ビツトの量子化を行う第1及び第2のA/
D変換器1及び2と、A/D変換器1のデイジタ
ル出力をアナログ値に変換するD/A変換器3
と、D/A変換器3の出力とA/D変換器1のア
ナログ信号入力の差を求める利得1(0dB)の差
動増幅器4と、第2のA/D変換器2の使い方を
切替える切替回路5とで構成されている。A/D
変換器1及び2はそれぞれ23−1=7個の比較器
6とエンコーダ7から構成された並列比較形の
A/D変換器で、切替回路5は入力回路と比較器
6の基準電圧と差動増幅器4の減算入力電圧とを
連動して切替えることにより、並列2回路の3ビ
ツトの粗い量子化と1回路の6ビツト精密量子化
とを切替えるよう構成されている。
Next, the present invention will be explained in detail with reference to the drawings.
FIG. 1 is a block diagram of an embodiment of the present invention, in which the first and second A/Rs each perform 3-bit quantization.
D converters 1 and 2, and a D/A converter 3 that converts the digital output of the A/D converter 1 into an analog value.
and a differential amplifier 4 with a gain of 1 (0 dB) to find the difference between the output of the D/A converter 3 and the analog signal input of the A/D converter 1, and the use of the second A/D converter 2 is switched. It is composed of a switching circuit 5. A/D
Converters 1 and 2 are parallel comparison type A/D converters each consisting of 2 3 -1=7 comparators 6 and encoders 7, and the switching circuit 5 is connected to the input circuit and the reference voltage of the comparator 6. By switching in conjunction with the subtraction input voltage of the differential amplifier 4, it is possible to switch between 3-bit coarse quantization using two parallel circuits and 6-bit precise quantization using one circuit.

第1図において、切替回路5が図に示すように
a側に接続されている場合には、第1のアナログ
信号101はA/D変換器1でnE0/8(nは1
〜7の正の整数)の7個のしきい値電圧によつて
8つの領域に分けられて3ビツトの出力A1,A2
A3に量子化され、第2のアナログ信号102は
差動増幅器4をそのまま通過してA/D変換器2
で同様に3ビツトの出力B1,B2,B3に量子化さ
れる。一方、切替回路5がb側に接続されている
場合には、A/D変換器1の出力はD/A変換器
3でアナログ信号103に変換されるが、その出
力はA/D変換器1の各領域の下限値、すなわち
0および7個のしきい値電圧となるように構成さ
れている。従つて、差動増幅器4でアナログ信号
101と103の差を求め、これをA/D変換器
2で更に3ビツトのデイジタル信号に量子化する
ことにより6ビツトの量子化が行われ、A1,A2
A3が上位3ビツトの出力に、B1,B2,B3が下位
3ビツトの出力となる。このとき、A/D変換器
2のしきい値電圧の間隔がA/D変換器1のしき
い値間隔の1/8となるように、切替回路5の抵抗
Rの値はR=7×((8r)に選ばれている。このよ
うな構成とすれば、3ビツト並列比較形を2段縦
続接続した6ビツトA/D変換器1台とほぼ同じ
構成と消費電力により、1アナログ情報の6ビツ
ト精密量子化と2アナログ信号の3ビツト粗量子
化の両方を切替えて処理することができ、重量お
よび消費電力の両面で無駄を除去できる効果があ
る。
In FIG. 1, when the switching circuit 5 is connected to the a side as shown in the figure, the first analog signal 101 is converted to nE 0 /8 (n is 1
The 3-bit outputs A 1 , A 2 ,
A3 , and the second analog signal 102 passes through the differential amplifier 4 as it is and is sent to the A/D converter 2.
Similarly, it is quantized into 3-bit outputs B 1 , B 2 , and B 3 . On the other hand, when the switching circuit 5 is connected to the b side, the output of the A/D converter 1 is converted to an analog signal 103 by the D/A converter 3; The lower limit value of each region is 1, that is, 0 and 7 threshold voltages. Therefore, the differential amplifier 4 calculates the difference between the analog signals 101 and 103, and the A/D converter 2 further quantizes this into a 3-bit digital signal, resulting in 6-bit quantization, and A 1 ,A 2 ,
A 3 becomes the output of the upper 3 bits, and B 1 , B 2 , and B 3 become the output of the lower 3 bits. At this time, the value of the resistance R of the switching circuit 5 is set to R=7× so that the interval between the threshold voltages of the A/D converter 2 is 1/8 of the threshold interval of the A/D converter 1. ((8r) is selected. With this configuration, one analog information It is possible to switch between 6-bit precise quantization of 2 analog signals and 3-bit coarse quantization of 2 analog signals, which has the effect of eliminating waste in terms of both weight and power consumption.

第2図は本発明の他の実施例のブロツク図であ
り、第1図と同一の回路は同一の参照番号で示し
てある。この回路の第1図との相違点は、切替回
路8がA/D変換器2の入力回路のみを切替え、
D/A変換器3の出力103とA/D変換器1の
入力101の差を求める差動増幅器9が16dB(8
倍)の電圧利得を持ち、A/D変換器2が常に同
一条件で動作するように構成されていることであ
つて、第1図と同様に使用でき同様の効果が得ら
れることは明らかである。
FIG. 2 is a block diagram of another embodiment of the invention, in which circuits that are the same as in FIG. 1 are designated by the same reference numerals. The difference between this circuit and FIG. 1 is that the switching circuit 8 switches only the input circuit of the A/D converter 2;
The differential amplifier 9 that calculates the difference between the output 103 of the D/A converter 3 and the input 101 of the A/D converter 1 outputs 16 dB (8 dB).
It is clear that the A/D converter 2 has a voltage gain of be.

上述の実施例は入力のアナログ信号が正の電圧
のみを対象とする場合であるが、正および負の電
圧を対象としても、D/A変換器3のアナログ出
力がA/D変換器1の各しきい値の中間値となる
ようにすれば全く同様の構成が可能である。又、
A/D変換器1及び2は共に3ビツトの量子化を
行う並列比較形としたが、3ビツト以外の並列比
較形以外のA/D変換器を使用してもよく、二つ
のA/D変換器の量子化ビツト数は必ずしも同一
でなくてもよい。更に、A/D変換器を二つでな
く三つ以上使用しても同様の構成が可能であり、
複数の粗い量子化と一つの精密量子化とを切替え
て使用することができる。なお、精密量子化と粗
い量子化との切替を入力の切替及びサンプリング
と関連させ、高速で切替動作を行うように構成す
ることもできる。
The above embodiment deals with the case where the input analog signal is only for positive voltage, but even if the input analog signal is for positive and negative voltages, the analog output of the D/A converter 3 is the same as that of the A/D converter 1. A completely similar configuration is possible by setting the threshold value to an intermediate value. or,
Both A/D converters 1 and 2 are of parallel comparison type that performs 3-bit quantization, but A/D converters other than 3-bit parallel comparison type may be used, and two A/D converters may be used. The number of quantization bits of the converters does not necessarily have to be the same. Furthermore, the same configuration is possible even if three or more A/D converters are used instead of two,
Multiple coarse quantizations and one fine quantization can be switched and used. Note that switching between fine quantization and coarse quantization can be associated with input switching and sampling, so that the switching operation can be performed at high speed.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明のA/D変
換回路によれば、一つの精密量子化を行うA/D
変換器とほぼぼ同一の回路規模で精密量子化と複
数の粗い量子化とを切替えて処理できる効果があ
り、人工衛星などに使用すれば重量および消費電
力の両面で無駄を省ける利点がある。
As explained in detail above, according to the A/D conversion circuit of the present invention, the A/D conversion circuit performs one precise quantization.
It has the effect of being able to switch between precise quantization and multiple coarse quantizations with almost the same circuit scale as a converter, and when used in artificial satellites, it has the advantage of reducing waste in terms of both weight and power consumption.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロツク図、第2
図は本発明の他の実施例のブロツク図であり、図
中の参照番号1及び2はA/D変換器、3はD/
A変換器、4及び9は差動増幅器、5及び8は切
替回路、6は比較器、7はエンコーダである。
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a block diagram of another embodiment of the present invention, in which reference numbers 1 and 2 are A/D converters, and 3 is a D/D converter.
A converter, 4 and 9 are differential amplifiers, 5 and 8 are switching circuits, 6 is a comparator, and 7 is an encoder.

Claims (1)

【特許請求の範囲】[Claims] 1 アナログ信号を量子化してデイジタル信号に
変換する少なくとも二つの第1及び第2のA/D
変換器と、前記第1のA/D変換器の出力をアナ
ログ信号に変換して前記第1のA/D変換器の入
力の第1のアナログ信号との差信号を求める差信
号発生手段と、前記第2のA/D変換器を前記差
信号の量子化と前記第1のアナログ信号とは独立
な第2のアナログ信号の量子化とに切替え使用す
る切替手段とを備えて構成されたことを特徴とす
るA/D変換回路。
1 At least two first and second A/Ds that quantize analog signals and convert them into digital signals.
a converter, and a difference signal generating means for converting the output of the first A/D converter into an analog signal to obtain a difference signal between the first analog signal and the first analog signal input to the first A/D converter. , switching means for switching the second A/D converter between quantization of the difference signal and quantization of a second analog signal independent of the first analog signal. An A/D conversion circuit characterized by:
JP26202984A 1984-12-12 1984-12-12 A/d converting circuit Granted JPS61140222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26202984A JPS61140222A (en) 1984-12-12 1984-12-12 A/d converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26202984A JPS61140222A (en) 1984-12-12 1984-12-12 A/d converting circuit

Publications (2)

Publication Number Publication Date
JPS61140222A JPS61140222A (en) 1986-06-27
JPH0358206B2 true JPH0358206B2 (en) 1991-09-04

Family

ID=17370033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26202984A Granted JPS61140222A (en) 1984-12-12 1984-12-12 A/d converting circuit

Country Status (1)

Country Link
JP (1) JPS61140222A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06112827A (en) * 1992-09-28 1994-04-22 Nec Corp Semi-flash type a/d converter

Also Published As

Publication number Publication date
JPS61140222A (en) 1986-06-27

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