JPH0358029A - Production of liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the disconnection of gate terminals and the step cutting of protective films by forming isolated patterns above scanning signal lines in the peripheral edge parts of a resist. CONSTITUTION:The scanning signal lines GL, gate electrodes and the electrodes of holding capacity elements are formed. A silicon nitride film, an (i)-type amor phous silicon film and an N<+> type silicon film are continuously provided and are selectively etched by a photoetching technique to form (i)-type semiconductor layers. The silicon nitride film which constitutes insulating films GI is dry-etched to form the isolated patterns ISP2 above the lines GL in the peripheral edge parts of the resist RST2. The silicon nitride film is selectively etched to form the films GI. Video signal lines, source electrodes, drain electrodes and transpar ent picture element electrodes are then formed and the protective films PRL consisting of 3rd conductive films d3 are provided on the gate terminals GTM. The disconnection of the gate terminals and the step cutting of the protective films are thereby prevented.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly to a method of manufacturing an active matrix type liquid crystal display device using thin film transistors and the like. [Prior Art] An active 71-lix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is constantly operated (duty ratio 1.0), so the active method has lower contrast and contrast than the so-called simple matrix method, which uses a time division fast method. It is becoming an indispensable technology, especially in color. A typical example of a switching element is a thin film transistor (TPT). In the conventional manufacturing method of active matrix type liquid crystal display devices, when dry etching the silicon nitride film used as the gate insulating film, an amorphous silicon film or a polycrystalline silicon film is interposed at the periphery of the resist. By this, a gentle slope 7 is formed on the 8 edges of the silicon nitride film.
After setting SF,,c as a dry etching gas,
The semiconductor layer is formed by selectively etching the silicon film using photolithography using CG. Note that an active matrix type liquid crystal display device using thin film transistors is described, for example, in ``12.5-inch active matrix type color liquid crystal display J with redundant configuration,'' Nikkei Electronics, pp. 193-2.
10, December 15, 1986, published by Nikkei McGraw-Hill.

[Problem to be solved by the invention]

However, in such a method of manufacturing a liquid crystal display device, when forming a semiconductor layer, the underlying pattern of the drain terminal and the chromium film forming the gate terminal are damaged by CQ ions in the dry etching gas. When a signal is sent to the drain terminal or gate terminal with moisture attached to the drain terminal or gate terminal, if the potential difference between adjacent drain terminals or gate terminals is large, the chromium film on the drain terminal or gate terminal may be damaged. Due to ionization, the drain terminal and gate terminal may corrode, and the drain terminal and gate terminal may become disconnected. This invention was made to solve the above-mentioned problems, and an object thereof is to provide a method for manufacturing a liquid crystal display device in which the terminals of signal lines are not disconnected.

[Means to solve the problem]

In order to achieve this object, a first invention provides a method for manufacturing an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode constitute one element of a pixel, in which a gate insulating film of the thin film transistor is At the same time, a semiconductor layer made of a silicon film of the thin film transistor is formed on a silicon nitride film which constitutes an insulating film to be used as an insulating film. An isolated pattern made of the above silicon film is formed above the film. Further, in a second aspect of the invention, in the method for manufacturing an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode constitute one element of a pixel, an insulating film used as a gate insulating film of the thin film transistor is configured. A silicon film is provided on the silicon nitride film to be used, and the silicon nitride film is dry-etched to form an insulating film to be used as the gate insulating film, and a resist is applied to the portion where the insulating film to be used as the gate insulating film is not formed. The semiconductor layer is formed by selectively etching the silicon film with the silicon film provided.

[Effect]

In the method for manufacturing a liquid crystal display device of the first invention, an isolated pattern is formed at the periphery of a resist for dry etching a silicon nitride film and above a conductive film constituting a signal line. The peripheral edge of the insulating film used as the gate insulating film on the conductive film is gently sloped, and an isolated pattern is formed at the same time as the semiconductor layer is formed. The terminals of the gate insulating film are not damaged by the dry etching gas, and since the semiconductor layer is an isolated pattern, film stress can be alleviated and the dry etching time of the gate insulating film can be increased. Further, in the method for manufacturing a liquid crystal display device according to the second invention,
M in which a silicon film is provided on a silicon nitride film, and the silicon nitride film is dry-etched to be used as a gate insulating film.
Since the edge film is formed, the peripheral edge of the N recording film used as the gate insulating film is provided with a gentle slope, and the gate I
The semiconductor layer is formed by selectively etching the silicon film with a resist provided on the part where the insulating film used as the edge film is not formed, so when forming the semiconductor layer, the signal line The terminals of the gate are not damaged by the dry etching gas, and since there is no semiconductor layer around the periphery of the insulating film used as the gate insulating film, the distribution line resistance is reduced commensurate with the step difference in the semiconductor layer.

【Example】

An active matrix color liquid crystal display device to which this invention is applied will be described below. In all the figures for explaining the liquid crystal display device, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section of the second Ail along the RIB-IIB cutting line and the vicinity of the seal portion of the display panel. FIG. 2C is a cross-sectional view taken along the IIC-nc cutting line in FIG. 2A. Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged. <Pixel Arrangement> As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines). line) is placed within the intersection area with DL (in the area surrounded by the four signal lines). Each pixel is a thin film transistor TPT
, transparent pixel electrode work T01 and storage capacitor element C add
including. The scanning signal lines OL extend in the column direction, and a plurality of scanning signal lines OL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction. <<Overall structure in cross section of display section>> As shown in FIG. 2B, a thin film transistor TPT and a transparent pixel electrode ITOI are formed on the lower transparent glass substrate SUBi side with respect to the liquid crystal LC, and the upper transparent glass substrate S
On the UB2 side, a color filter FIL and a light shielding film BM forming a black matrix pattern for light shielding are formed. The lower transparent glass substrate SUBI is, for example, 1. 1
The thickness is approximately [++v+]. The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates SUB1, SUB2 where external lead wiring is present, and the right side shows the cross section of the left side edge portion of the transparent glass substrates SUB1, SUB2. The sealing material SL shown on the left and right sides of FIG. 2B, which shows a cross section of the right side edge of SUB2 where no external lead wiring exists, is configured to seal the liquid crystal LC. Transparent glass substrate SUBI,S excluding the sealing port (not shown)
It is formed along the entire circumference of UB2. The sealing material SL is made of, for example, epoxy resin. Common transparent pixel electrode IT on the upper transparent glass substrate SUBZ side
O2 is applied to the silver paste material SI at least in one place.
It is connected to the external lead wiring formed on the lower transparent glass substrate SUBl side by L. This external lead wiring includes a gate electrode GT, a source electrode SDI, and a drain electrode SD2.
are formed in the same manufacturing process as each. Orientation films ORII, ORI2, transparent pixel electrode ITO1, common transparent pixel electrode ITO2, protective film psv1, PSV2,
Each layer of the insulating film GI is formed inside the sealing material SL. Polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively. The liquid crystal LC has a lower alignment film ORI that sets the direction of the liquid crystal molecules.
1 and the upper orientation 110RI2, and sealed by the seal portion SL. The lower alignment film ORII is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side. A light shielding film BM. Color filter FIL, protective film P
SV2, a common transparent pixel electrode ITO2 (COM), and an upper alignment film ORI2 are sequentially stacked. This liquid crystal display device is constructed by separately forming layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and then stacking the upper and lower transparent glass substrates SUBI and SUB2, and sealing the liquid crystal LC between them. Can be assembled. <Thin Film Transistor TPT> The thin film transistor TPT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is made zero, the channel resistance becomes large. The thin film transistor TPT of each pixel has three
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TFT2, and TFT3. Each of the thin film transistors TPTI to TFT3 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TPT1 to TFT3 mainly has a gate electrode G.
T, gate insulating film G, i type (intrinsi)
c, an i-type semiconductor layer AS made of non-quality silicon (Si) (not doped with conductivity type determining impurities), and a pair of source electrode SDI and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following description, for convenience, one side is fixed as a source and the other side is fixed as a drain. <Gate electrode GT3) The gate electrode GT is the first conductive film gl in FIG. 4 (FIG. 2A,
As shown in detail in the plan view depicting only the second conductive film g2 and the i-type semiconductor layer AS, it has a shape that projects vertically from the scanning signal line GL (upward in FIGS. 2A and 4). (branched into a T-shape). Gate electrode GT is thin film transistor TPT1 to TFT3
It is constructed so that it protrudes to the respective formation areas. The respective gate electrodes GT of the thin film transistors TPTI to TFT3 are integrated (as a common gate electrode) and are formed continuously to the scanning signal line GL. The gate electrode GT is made of a single-layer first layer so as not to create a large step in the formation region of the thin film transistor TPT.
It is made of conductive material of 111gl. The first conductive film g1 is, for example, a chromium (Cr) film formed by sputtering, and lo0
0[AE Formed with a film thickness of about E. As shown in FIGS. 2A, 2B, and 4, this gate electrode GT is formed to be thicker than the i-type semiconductor layer AS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUBI, the gate electrode GT made of opaque chrome forms a shadow, and the backlight light does not shine on the i-type semiconductor layer AS. , conductive phenomena caused by light irradiation, that is, deterioration of the off-characteristics of the thin film transistor TPT, are less likely to occur. Note that the original size of the gate electrode GT is the minimum necessary size to straddle the source electrode SDI and drain electrode SD2, and also includes the alignment margin between the gate electrode GT, the source electrode SDI, and the drain electrode SD2). The depth length that determines the channel width W is determined by the ratio of the distance 11 (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W/L that determines the mutual conductance gIl. It depends on what you do. The size of the gate electrode GT in this liquid crystal display device is of course made larger than the original size mentioned above. Note that if we consider only from the gate and light shielding functions of the gate electrode GT, the gate electrode GT and the scanning signal, Ii
The GL may be integrally formed in a single layer, in which case aluminum (
Al). Pure aluminum, aluminum containing palladium (Pd), etc. can be selected. <<Scanning Signal Line OL> The scanning signal line GL is constituted by a composite film including a first conductive film g1 and a second conductive film g2 provided on top of the first conductive film g1. The first conductive film gl of this scanning signal line GL is the gate electrode G.
The first conductive film g1 of T is formed in the same manufacturing process and is configured integrally. The second conductive film g2 is formed using, for example, an aluminum film formed by sputtering, and has a thickness of about 1000 to 550 (l[A]).The second conductive film g2 reduces the resistance value of the scanning signal aGL, and The scanning signal line GL is configured to increase the transmission speed (improve the writing characteristics of pixel information).Furthermore, the scanning signal line GL has a width dimension of the second conductive film g1 that is larger than the width of the first conductive film g1. The width dimension of g2 is made small. In other words, the side wall of the scanning signal line GL has a gentle stepped shape. <Insulating film GI> The insulating film GI is the gate insulating film of each of the thin film transistors TPTI to TFT3. The insulating film GI is formed on the upper layer of the gate electrode GT and the scanning signal IGL.
Using a silicon nitride film formed by VD,
Formed with a film thickness of approximately . <<I-type semiconductor layer AS> As shown in FIG. 4, the i-type semiconductor layer AS is used as a channel formation region for each of the thin film transistors TPT1 to TFT3 divided into a plurality of parts. i-type semiconductor layer A
S is formed of a non-quality silicon film or a polycrystalline silicon film, and has a thickness of about 1800 [. Formed with a film thickness of approximately This i-type semiconductor layer AS is made of Si by changing the supply gas.
,N. An insulating film G used as a gate insulating film consisting of
Subsequently to the formation of I, it is formed in the same plasma CVD apparatus without being exposed to the outside from the plasma CVD apparatus. Further, a P-doped N+ type semiconductor layer do (FIG. 2B) for ohmic contact is similarly formed continuously to a thickness of about 40 mm. Thereafter, the lower transparent glass substrate SUB 1 is taken out from the CVD apparatus, and the N4 type semiconductor/IdO and i type semiconductor layers AS are separated as shown in FIGS. 2A, 2B and 4 using photo processing technology. It is patterned into an island shape. As shown in detail in FIGS. 2A and 4, the i-type semiconductor layer AS is also provided between the scanning signal line GL and the video signal line DL at an intersection (crossover section). The i-type semiconductor MAS at this intersection is designed to reduce short circuits between the scanning signal line GL and the video signal line DL at the intersection. <<Source electrode SDI, drain electrode SD2>
Thin film transistors TPTI to TFT3 divided into multiple parts
The respective source electrodes SD1 and drain electrodes SD2 of FIG. 2A, 2Bl! As shown in detail in FIG. 1 and FIG. 5 (a plan view depicting only the first to third conductive films d1 to d3 in FIG. 2A), they are provided separately on the i-type semiconductor layer AS. Source electrode SDI, drain electrode S
Each of D2 includes a first conductive film d1, a second conductive film d2, and a third conductive film l from the lower layer side contacting the N+ type semiconductor layer do.
It is constructed by sequentially overlapping d3. Source electrode S
The first conductive film d1, second conductive film d2 and third conductive film d3 of DI are the same as the first conductive film d1, second conductive film d3 of drain electrode SD2.
It is formed in the same manufacturing process as the conductive film d2 and the third conductive film d3. The first conductive film d1 is a chromium film formed by sputtering,
It is formed with a film thickness of 500 to 1000 [A] (in this liquid crystal display device, a film thickness of about 600 [λ]). Doesn't the thicker the chromium film become, the greater the stress? So, 20
The thickness of the film should not exceed 0.00 [A]. The chromium film has good contact with the N+ type semiconductor layer dO. The chromium film constitutes a so-called pariah layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N+ type semiconductor layer do. As the first conductive film d1, in addition to the chromium film, a high melting point metal (
Mo. Ti, Ta. W) film, high melting point metal silicide (M
oSi. , TiSi. , TaSi, , WSi) film. After patterning the first conductive film d1 by photo processing, the N-type semiconductor layer dO is removed using the same photo processing mask or using the first conductive film d1 as a mask. In other words, the N+ type semiconductor layer d remaining on the i type semiconductor layer AS
o, the portion other than the first conductive film d1 is removed by self-alignment. At this time, the N+ type semiconductor layer dO is etched so that its entire thickness is removed, so the i-type semiconductor JA
S is also etched to some extent on its surface, but the degree of etching can be controlled by the etching time. Thereafter, the second conductive film d2 is formed by sputtering aluminum to a thickness of 3000 to 3500 [A] (in this liquid crystal display device, a film thickness of about 3500 [A]). The aluminum film has less stress than the chromium film, and can be formed to a thick film thickness, so that the source electrode SD
1. It is designed to reduce the resistance values of the drain electrode SD2 and the video signal line DL. The second conductive film d2 may be formed of an aluminum film containing silicon or copper (Cu) as an additive in addition to the aluminum film.
After patterning the second conductive film d2 using photo processing technology,
A third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-
It is made of Tin-Oxide ITO (nesa film) and is formed with a film thickness of about 1000 to 2000 [λ] (in this liquid crystal display device, a film thickness of about 1200 [λ]). This third conductive film d3 includes a source electrode SD1 and a drain electrode S.
D2 and the video signal line DL, as well as a transparent pixel electrode ITOI. First conductive film d1 of source electrode SDI, drain electrode SD
Each of the two first conductive films d1 is connected to the upper second conductive film d1.
The conductive film d2 and the third conductive film d3 extend further inward (into the channel region). In other words, the first conductive film d1 in these parts has a gate length L of the thin film transistor TPT, regardless of the second conductive film d2 and the third conductive film d3.
It is structured so that it can be specified. The source electrode SDI is connected to the transparent pixel electrode ITOI. The source electrode SD1 has a step shape of the i-type semiconductor layer As (a step corresponding to the sum of the thickness of the first conductive film g1, the thickness of the N+ type semiconductor layer dO, and the thickness of the i-type semiconductor layer AS). It is organized along the lines. Specifically, the source electrode SDI is connected to a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and a transparent pixel electrode ITOI on the upper part of this first conductive film d1. A second conductive film d2 whose side is smaller in size, and a third conductive film d1 connected to the first conductive film d1 exposed from the second conductive film d2.
It is composed of a conductive film d3. The second conductive film d2 of the source electrode SDI cannot overcome the step shape of the i-type semiconductor layer As because the chromium film of the first conductive film d1 cannot be formed thickly due to increased stress. It is organized for the purpose of In other words, the second conductive film d2
The stepping force barrier is improved by forming it thickly. Since the second conductive film d2 can be formed thickly, the resistance value of the source electrode SDI (drain electrode SD2 and video signal line DL)
The same applies to the above). Since the eighth conductive film 11 [a3 cannot overcome the step shape caused by the i-type semiconductor layer As of the second conductive film d2,
By reducing the size of the conductive film d2, the exposed first
It is configured to connect to the conductor 91[d1. 1st
The conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connection between them, so that the source electrode SDI and the transparent pixel electrode ITO1 can be reliably connected. <<Transparent Pixel Electrode ITOI> The transparent pixel electrode TOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITOI has three transparent pixel electrodes corresponding to each of the thin film transistors TPT1 to TFT3 divided into plural parts of the pixel.
The transparent pixel electrodes are divided into four divided transparent pixel electrodes E1, E2, and E3. The divided transparent pixel electrodes E1 to E3 are each connected to the source electrode SDI of the thin film transistor TPT. Each of the divided transparent pixel electrodes E1 to E3 is patterned to have substantially the same area. In this way, by dividing the thin film transistor TPT of the IW element into a plurality of thin film transistors TPTI to TFT3, and connecting each of the divided transparent pixel electrodes E1 to E3 to each of the divided thin film transistors TPTI to TFT3, Even if a divided part (for example, thin film transistor TFTI) becomes a point defect, it is no longer a point defect in the entire pixel (thin film transistor TFT2
and thin film transistor TFT3 is not defective), so
The probability of point defects can be reduced, and defects can be made difficult to see. Moreover, by configuring each of the divided transparent pixel electrodes E1 to E3 with substantially the same area, the divided transparent pixel electrode E
The respective liquid crystal capacitances Cpix constituted by each of pixels 1 to E3 and the common transparent pixel electrode ITO2 are made uniform. It can be done. <<Protective Film PSVI> A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode TO1. Protective film PSVI
is mainly formed to protect the thin film transistor TPT from moisture, etc., and a material with high transparency and good moisture resistance is used. The protective film PSv1 is, for example, plasma C.
It is formed of a silicon oxide film or a silicon nitride film formed using a VD device, and is formed to a thickness of about aooocλ. <<Light-shielding film BM>> A shielding film BM is provided on the upper transparent glass substrate SUBZ side to prevent external light (light from above in FIG. 2B) from entering the i-type semiconductor layer As used as a channel formation region.
is provided, and the shielding film BM has a pattern as shown by the hatching in FIG. Note that FIG. 6 is a plan view depicting only the third conductive film d3 made of an ITO film, the color filter FIL, and the light shielding 1 [BM in FIG. 2A. The light-shielding film BM is formed of a film having a high light-shielding property, such as an aluminum film or a chromium film, and in this liquid crystal display device, the chromium film is formed by sputtering to a thickness of about 1300 μm. Therefore, the i-type semiconductor layer AS of the thin film transistors TFTI to TFT3 is sandwiched between the upper and lower light shielding films BM and the thick gate electrode GT, and that portion is not exposed to external natural light or backlight light. Blackout! The IBM is formed around the pixel as shown by the hatched area in FIG. 6, that is, the light shielding film BM is formed in a grid pattern (black matrix).
This grid separates the effective display area of one pixel. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM has two functions: shielding the i-type semiconductor layer As and serving as a black matrix. It is also possible to attach the backlight to the upper transparent glass base SUB2 side and place the lower transparent glass substrate SUBI on the II side (externally exposed side). 《Common transparent pixel electrode I
TO2) The common transparent pixel electrode ITO2 is connected to the lower transparent glass substrate SU.
Opposing the transparent pixel electrode ITOI provided for each pixel on the B1 side, the optical state of the liquid crystal LC changes in response to the potential difference (electric field) between each pixel electrode IT○1 and the common transparent pixel electrode ITO2. do. A common voltage Vcow is applied to this common transparent pixel electrode ITO2. The common voltage Vco@ is an intermediate potential between the low-level driving voltage V d @in and the high-level fluctuating voltage V d wax applied to the video signal line DL. <<Color Filter FIL>> The color filter FIL is constructed by coloring a dyed base material made of a resin material such as an acrylic resin with a dye. The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (Fig. 7), and is dyed differently (
Figure 7 shows the third conductive film layer d3 and color filter F in Figure 3.
It depicts only IL, R. G. Each color filter FIL in B is 45° and 135°, respectively, with cross hatching). The color filter FIL is formed thick so as to cover all of the transparent pixel electrode IT○1 (E1 to E3) as shown in FIG. The transparent pixel electrode is formed inside the peripheral edge of the TOI so as to overlap with the transparent pixel electrode TOI. Color filter FIL can be formed as follows. *First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixation treatment to form a red filter R. Next, a green filter G and a blue filter B'tt are sequentially formed by performing similar steps. <<Protective Film PSV2> The protective film PSV2 is provided to prevent the dyes used to dye the color filters FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of a transparent resin material such as acrylic resin or epoxy resin.6 <Pixel Arrangement> As shown in FIGS. A plurality of pixels are arranged in the same column direction as the extending direction, and serve as respective pixel columns Xi, X2, X3, X4, . . . Each pixel column Xi, X2, X3, X
Each pixel of 4,... is a thin film transistor TF.
The arrangement positions of TI-TFT3 and divided transparent pixel electrodes El-E3 are configured to be the same. In other words, odd pixel row Xi
．． In each pixel X3, . . . , the thin film transistors TPT1 to TFT3 are arranged on the left side, and the divided transparent pixel electrodes E1 to E3 are arranged on the right side. Each pixel in the even numbered pixel columns X2, X4, . . . adjacent to each of the odd numbered pixel columns Xi, X3, . . . It is composed of pixels that are symmetrically turned upside down with respect to the direction in which the signal line DL extends. That is, pixel columns X2, X4,
Each pixel of... is a thin film transistor TPT1
~The arrangement position of TFT3 is on the right side, transparent pixel electrode El-E3
The placement position of is configured on the left side. And pixel row X2
, X4, ... are pixel columns Xi, X3
,... are arranged by moving (shifting) half a pixel interval in the column direction, that is, if each pixel interval of pixel column X is 1.0 (1.0 pitch), , the next pixel column X has a pixel interval of 1.0, and is shifted by 0.5 pixel interval (0.5 pitch) from the previous pixel column X in the column direction. The video signal line DL, which runs between each pixel in the row direction, extends for half a pixel interval (0
．． 5 pitches) is configured to extend in the row direction. As a result, as shown in FIG. 7, the pixels in the previous pixel row Pixels on which same-color filters are formed (for example, pixel row
4) are spaced apart by 1.5 pixels (1.5 pitch), and the RGB color filters FIL are arranged in a triangular pattern. Color filter FI
The triangular arrangement structure of RGB of L can improve the color mixing of each color, so that the resolution of the color image can be improved. Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal line D
It is possible to eliminate the routing of L and reduce its occupied area, and it is also possible to eliminate detours of the video signal line DL and eliminate the multilayer wiring structure. <<Equivalent circuit of entire display device>> The equivalent circuit of this liquid crystal display device is shown in No. 8@. XiG, Xi+IG, . . . are video signal lines DL connected to the pixels in which the green filter G is formed. X i
B P X i + I B + . . . are video signal lines DL connected to the pixels in which the blue filter B is formed. X i + l R , X i + 2 R , ・
- is a video signal line DL connected to the pixel in which the red filter R is formed. Of these video signal lines DL, sYi selected by the video signal drive circuit is a scanning signal line OL that selects the pixel column X1 shown in FIG. 3@ and FIG. Similarly, each of Yi+1, Yi+2, . . . is a scanning signal line GL that selects each of the pixel columns X2, X3, . These scanning signals, tllGL, are connected to a vertical scanning circuit. <<Structure of storage capacitor element C add>> Each of the divided transparent pixel electrodes El-E3 is bent into an L-shape at the end opposite to the end connected to the thin film transistor TPT so as to overlap with the adjacent scanning signal 1iGL. It is formed as follows. As is clear from FIG. 2C, in this superposition, each of the divided transparent pixel electrodes E1 to E3 is used as one electrode PL2, and the adjacent scanning signal 1iGL is
A storage capacitance element (electrostatic capacitance element) C add is constructed with the other electrode PLI as the other electrode PLI. This storage capacitor element C add
The dielectric film is composed of the same layer as the insulation film GI used as the gate insulator of the thin film transistor TPT. As is clear from FIG. 4, the storage capacitor element C add is formed in the widened portion of the first conductive film g1 of the gate line OL. Note that the first conductive film g1 at the portion intersecting with the video signal line DL is made thin in order to reduce the probability of short circuit with the video signal line DL. Each of the divided transparent pixel electrodes E1 to E3 overlapped to form a storage capacitance element Cadd
Similarly to the source electrode SDI, a first conductive film d1 and a second conductive film d2 are provided in a part between the transparent pixel electrode IT○1 and the transparent pixel electrode IT○1 to prevent disconnection when going over the step shape. There is an island area. This island region is designed to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITO1. <<Equivalent circuit of storage capacitor element C add and its operation>> 2nd
FIG. 9 shows an equivalent circuit of the pixel shown in FIG. In FIG. 9, Cgs is a parasitic capacitance formed between the gate electrode GT and source electrode SDI of the thin film transistor TPT. The dielectric film of the parasitic capacitance Cgs is an N edge film GI. C pix is a liquid crystal capacitor formed between the transparent pixel electrode ITOI (PIX) and the common transparent pixel electrode IT02 (COM). The dielectric film of the liquid crystal capacitor C pix is the liquid crystal LC, the protective film PSVI, and the alignment films ORII and ORI.
It is 2. Vlc is a midpoint potential. When the thin film transistor TPT switches, the storage capacitance element C add has a midpoint potential (pixel electrode potential) Vl.
It works to reduce the influence of gate potential change ΔVg on c. This situation can be expressed as the following formula. ΔVlc= (Cgs/(Cgs+Cadd+Cpix
))X ΔVgHere, ΔVia represents the change in midpoint potential due to ΔVg. This change ΔVia is the liquid crystal L
This causes the direct current power added to C, but the holding capacity C ad
The larger d is, the smaller its value can be. Further, the storage capacitor element C add also has the effect of lengthening the discharge time, so that video information is stored for a long time after the thin film transistor TPT is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching between liquid crystal display screens. As mentioned above, since the gate electrode GT is enlarged to completely cover the i-type semiconductor layer AS, the overlapping area with the source electrode SDI and drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases, and the center point The opposite effect occurs in that the potential Vlc becomes more susceptible to the influence of the gate (scanning) signal Vg. However, by providing the storage capacitor element Cadd, this disadvantage can also be eliminated. The storage capacitance of the storage capacitor element C add is 4 to 8 times (4・C
pix(C add< 8・C pix). 8 to 32 times the superposition capacitance Cgs (8 ・Cgs<
Cadd<32・Cgs). <Connection method of storage capacitor element C add electrode line> The final stage scanning signal line GL (or first stage scanning signal line GL) used only as a capacitor electrode line is connected to the common transparent pixel electrode as shown in FIG. Connect to ITO2 (Vcom). As shown in FIG. 2B, the common transparent pixel electrode ITO2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by means of a silver paste material SL. Moreover, part of the conductive layer (gl and g2) of this external wiring is connected to the scanning signal line OL.
It is constructed using the same manufacturing process. As a result, the final stage scanning signal line (capacitive electrode line) GL can be easily connected to the common transparent pixel electrode TO2. Alternatively, as shown by the dotted line in FIG. 8, the final stage (first stage) scanning signal 1 (capacitive electrode line) GL may be connected to the first stage (final stage) scanning signal line OL. Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring. <DC cancellation by scanning signal of storage capacitance element Cadd> This liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present application. , by controlling the rotating voltage of the scanning signal line OL, as shown in FIG. 10 (time chart). It is possible to reduce the direct current force applied to the liquid crystal LC. In FIG. 10, Vi is the driving voltage of an arbitrary scanning signal line GL, Vi+1 is the fighting voltage of the scanning signal line GL in the next stage, and Vae is the low-level swinging voltage V applied to the video signal line DL. d win
, Vdd is a high-level dynamic voltage Vdwax applied to the video signal line DL. Each time t=t1~t4
The voltage change Δ of the midpoint potential vic (see Figure 9) at
V■~Δv4 is the total capacitance of pixels C=Cgs+Cpi
When x+Cadd, it is expressed by the following formula. ΔVz= −
(Cgs/C)・V2 Δv,=+(Cgs/C)・(V1+V2)−(Cad
d/C)・V 2 ΔVa=-(Cgs/C)・v1 +(Cadd/C) {V1+V2) ΔV4=-(Cadd/C)・V1 Here, the drive voltage applied to the scanning signal line GL is If sufficient (see below)

(See note), the DC voltage applied to the liquid crystal LC is expressed by the following formula. ΔV, +ΔV. = (Cadd-V 2 - Cga-
v1)/C Therefore. Cadd-V2=
If Cgs-V is 1, the DC voltage applied to the liquid crystal LC will be O.

[Note] Time tl. At t2, the change in the drive voltage Vi affects the midpoint potential Vlc, but during the period from t2 to t3, the midpoint potential Vlc is made the same potential as the video signal potential through the signal line Xi (if the video signal is not sufficiently written) ). The potential applied to the liquid crystal LC is almost determined by the potential immediately after the thin film transistor TPT is turned off (thin film transistor TP
The off period of T is overwhelmingly longer than the on period). Therefore, calculation of the DC component applied to the liquid crystal LC is performed during the period t1 to t3.
can be almost ignored, and it is only necessary to consider the influence of the potential immediately after the thin film transistor TPT is turned off, that is, the transient period at times t3 and t4. Note that the polarity of the video signal is reversed for each frame or line, and the DC component due to the video signal itself is assumed to be zero. In other words, in the DC cancellation method, the reduction due to the pull-in of the midpoint potential Vlc by the parasitic capacitance Cgs is compensated for by the retention capacitance element C.
It is possible to push up the voltage by the drive voltage applied to the add and the next stage scanning signal line (capacitive electrode line) GL, and to extremely reduce the direct current force applied to the liquid crystal LC. As a result,
Liquid crystal display devices can improve the lifespan of liquid crystal LC. Of course, if the gate electrode GT is made larger to increase the light shielding effect, the storage capacitor element C add
All you have to do is increase the storage capacity of Next, a method for manufacturing a liquid crystal display device according to the first invention will be explained with reference to FIG. IA. First, as shown in FIG. 1A (a), a first conductive film g1 made of chromium with a film thickness of 1100 mm is provided by sputtering on a lower transparent glass substrate SUBI made of 7059 glass (trade name). Next, the first conductive layer 1 [K
By selectively etching gL, the first layer of the scanning signal line GL, the gate electrode GT, and the storage capacitor element C a
dd electrode PL1 and drain terminal base pattern DU
Form P. Next, a second conductive film g2 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon, etc. and having a film thickness of IOOOC is formed by sputtering. Next, the second layer of the scanning signal mGL is formed by selectively etching the second conductive film g2 by photolithography using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etching solution. Next, ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD equipment to reduce the film thickness to 3.
A silicon nitride film of 500 [A] was provided, and the plasma Cv
Silane gas and hydrogen gas were introduced into D equipment, and the film thickness was 21.
After forming an i-type amorphous silicon film with a thickness of 300 [A], hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus to form an N'' type silicon film with a film thickness of 300 [A].
Next, SF, , C(1
, by selectively etching the N'' type silicon pus and the i type amorphous silicon film using photolithography technology.
At the same time as forming the i-type semiconductor layer AS, an NI-type silicon film, an i-type non-quality silicon film, is formed on the periphery of the resist RSTl for dry etching the silicon nitride film constituting the insulating film GI and above the drain terminal underlying pattern DUP. An isolated pattern ISP1 made of a silicon film is formed. and,
As shown in FIG. 1B, the width of this isolated pattern ISPI is wider than the width of the drain terminal underlying pattern DUP, and the isolated pattern ISPI has a shape that can be climbed over in two directions. Next, as shown in FIG. 1A (b), an insulating film GI is formed by selectively etching the silicon nitride film by photolithography using SF as a dry etching gas. Next, Figure IA (c
), a first conductive film d1 made of chromium with a film thickness of 600 mm is provided by sputtering. Next, by selectively etching the first conductive film d1 using photolithography, the video signal line DL and the drain terminal DTM are removed.
, a first layer of a source electrode SD1 and a drain electrode SD2 is formed. Next, before removing the resist, C(1!,.SF,) is introduced into a dry etching apparatus to selectively etch the N+ type silicon film, thereby forming an N+ type semiconductor layer do. The film thickness was 3500 [A
] A second conductive film d2 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. is provided by sputtering. Next, a second conductive film d is formed using photolithographic technology.
By selectively etching 2, the video signal line D
Form a second layer of L, drain terminal DTM, source electrode SDI, and drain electrode SD2. Next, the film thickness is 120 mm.
A third conductive film d3 made of an ITO film with a thickness of 0[λ is spread by sputtering. Next, the third conductive film d is etched using a photo-etching technique using a mixed acid of hydrochloric acid and nitric acid as an etching solution.
By selectively etching 3, the video signal line D
A third layer of L, a drain terminal DTM, a source electrode SD1, a drain electrode SD2, and a transparent pixel electrode ITO1 are formed. Next, add ammonia gas to the plasma CVD equipment.
Silane gas and nitrogen gas are introduced to form a silicon nitride film with a thickness of 1 [-]. next. The protection 11 [
Forms PsV1. In this method of manufacturing a liquid crystal display device, resist RS
With the isolated pattern ISPI formed at the periphery of the TI and above the drain terminal underlying pattern DUP, the insulating film G
By performing dry etching of I, the silicon nitride film is etched while recessing the silicon film, taking advantage of the fact that the etching rate of the silicon film is 4 to 7 times that of the silicon nitride film. Since the peripheral edge of the insulating film Gr is provided with a gentle slope on the drain terminal base pattern DUP, it is possible to prevent the video signal line DL from being disconnected. In addition, since the peripheral edge of the insulating film GI on the drain terminal base pattern DUP does not become reversely tapered, dirt can be easily removed by cleaning with an organic solvent or water.
No electrolytic corrosion occurs, increasing reliability. Furthermore, since the isolated pattern ISP1 is formed at the same time as the i-type semiconductor layer As is formed, the drain terminal base pattern DUP is not damaged by Ca ions in the dry etching gas when the i-type semiconductor layer As is formed. Therefore, when a signal is sent to the drain terminal DTM with moisture attached to the drain terminal DTM part, even if the potential difference between adjacent drain terminals DTM is large, the drain terminal DT
Since M is never ionized, the drain terminal DTM
will not corrode and the drain terminal DTM will not be disconnected. *In addition, since the width of the isolated pattern SP1 is made wider than the width of the drain terminal base pattern DUP,
Isolated pattern ISPI when forming video signal line DL
The amount of side etching in the remaining portion is reduced. moreover,
Since the isolated pattern ISPI has a shape that can be crossed over in two directions, the video signal line DL is connected to the isolated pattern ISPI.
It is possible to prevent the video signal line DL from being disconnected when it crosses over the remaining portion of No. 1. Another method of manufacturing a liquid crystal display device according to the first invention will be explained with reference to FIG. First, as shown in FIG. 1C, the scanning signal line GL, the gate electrode GT, and the electrode PLI of the storage capacitor element Cadd are formed. Next, a silicon nitride film, an i-type amorphous silicon film, and an N+ type silicon film are successively provided. Next, SF, CCU.
By selectively etching the N" type silicon film and the i type amorphous silicon film using photolithography technology, the i
At the same time as forming the type semiconductor layer As, the scanning signal A! An isolated pattern ISP2 made of an i-type amorphous silicon film and an N-type silicon film is formed above GL. As shown in FIG. ID, the width of this isolated pattern ISP2 is wider than the width of the scanning signal line OL, and the isolated pattern ISP2 has a shape that can be climbed over in three directions. Next, as shown in FIG. 1B, the silicon nitride film is selectively etched to form an insulating film GI. Next, as shown in FIG. 1C, the video signal line DL, the source electrode SDI. A protective film PRL consisting of a third conductive film d3 is formed on the gate terminal GTM while forming the drain electrode SD2 and the transparent pixel electrode [iITO1].
Generalize. In this method of manufacturing a liquid crystal display device, since the isolated pattern ISP2 is formed at the periphery of the resist RST2 and above the scanning signal line GL, the scanning signal line OL
Since the peripheral edge of the #@edge film GI is provided with a gentle slope on the top, it is possible to prevent the protective film PRL from being cut off. Furthermore, since the isolated pattern ISP2 is formed at the same time as the i-type semiconductor layer As is formed, the scanning signal line GL is not damaged by CQ ions in the dry etching gas when the i-type semiconductor layer AS is formed. Therefore, when a signal is sent to the gate terminal GTM with moisture attached to the gate terminal GTM part, the gate terminal GTM will not be ionized even if the potential difference between adjacent gate terminals GTM is large. GT
M will not corrode and the gate terminal GTM will not be disconnected. Furthermore, since the width of the isolated pattern I SP2 is made thicker than the width of the scanning signal line GL, the protective film PRL
The amount of side etching of the remaining portion of the isolated pattern SP2 when forming the pattern SP2 is reduced. Also, isolated pattern IS
Because P2 has a shape that allows it to be climbed over in three directions,
When the protective film PRL crosses over the remaining portion of the isolated pattern ISP2, it is possible to prevent the protective film PRL from breaking. Furthermore, a protective film PR is formed on the gate terminal GTM.
Since the gate terminal L is provided, the gate terminal GTM will not be corroded and there is no chance of the gate terminal GTM being disconnected. Next, a method for manufacturing a liquid crystal display device according to the second invention will be explained with reference to FIG. First, as shown in FIG. 1E (a), the first layer of the scanning signal line GL, the gate electrode GT,
The electrode PLl and drain terminal base pattern DUP of the storage capacitor element C add are formed. Next, a second layer of scanning signal lines GL is formed. Next, a silicon nitride film, i
A type non-quality silicon film and an N+ type silicon film are successively provided. Next, a resist RST3 is provided for dry etching the silicon nitride film that constitutes the insulating film G. Next, as shown in FIG. 1E (b), SF. The insulating film GI is formed by selectively etching the silicon nitride film using a photolithographic technique using a photolithographic technique. Next, as shown in FIG. 1E (c), with the resist RST4 for forming the i-type semiconductor layer AS provided in the portion where the insulating film GI is not formed, SFs-CCA4 is used as a dry etching gas. An i-type semiconductor layer As is formed by selectively etching the N+ type silicon film and the i-type non-quality silicon film using the photolithography technique used. Next, the video signal line DL, the source electrode SDI. A drain electrode SD2 and a transparent pixel electrode ITOI are formed. Next, a protective film PSVI is formed. In this method of manufacturing a liquid crystal display device, an i-type non-quality silicon film and an N+ type silicon film are provided on a silicon nitride film, and then the silicon nitride film is dry-etched to form an insulating film G process. Since the peripheral edge of the GI is provided with a gentle slope, it is possible to prevent the video signal line DL from being disconnected. In addition, with the resist RST4 provided in the part where the insulating film GI is not formed, N+
Since the i-type semiconductor RAS is formed by selectively etching the i-type silicon film and the i-type amorphous silicon film, when forming the i-type semiconductor layer AS, the drain terminal underlying pattern DUP is etched in the dry etching gas. Since the drain terminal D is not damaged by the CQ ions of
When a signal is sent to the drain terminal DTM with moisture attached to the TM part, the drain terminal DTM will not be ionized even if the potential difference between adjacent drain terminals DTM is large, so the drain terminal DTM will corrode. Therefore, the drain terminal DTM will not be disconnected. Furthermore, as in the first invention, since no remaining portion of the isolated pattern ISPI is generated, the video signal line DL is not cut off at the peripheral edge of the insulating film GI. Also, resist RST3
The adhesion between the resist RST3 and the non-quality silicon film is better than that between the resist RST3 and the silicon nitride film. Since the insulating film GI is formed by dry etching the film, a hole is not generated in the resist RST3, so a hole is formed in the insulating film G, and the gate electrode GT, source electrode SDI, and drain electrode SD2 are short-circuited. can be effectively prevented. As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but this invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course. For example, in the above embodiment, an inverted staggered structure is shown in which gate electrode formation→gate insulating film formation→semiconductor layer formation→source/drain electrode formation, but the present invention can also be applied to a staggered structure in which the vertical relationship or the order of formation is reversed. It is valid. [Effects of the Invention] As explained above, in the method for manufacturing a liquid crystal display device according to the present invention, the terminals of the signal lines are not damaged by the dry etching gas, so moisture does not adhere to the terminals of the signal lines. When a signal is sent to the terminal of a signal line in this condition, even if the potential difference between the terminals of adjacent signal lines is large, the terminal of the signal line will not be ionized, so the terminal of the signal line will not corrode. This prevents the signal line terminal from becoming disconnected. Furthermore, since the semiconductor layer is formed into an isolated pattern, film stress can be alleviated, and a margin can be provided for the dry etching time of the gate insulating film. Furthermore, since the signal line portion at the peripheral edge of the insulating film used as the gate insulating film does not become reversely tapered, dirt can be easily removed by cleaning with an organic solvent or water, so electrical corrosion does not occur. Increased reliability. In addition, the wiring direction over the semiconductor layer, which is an isolated pattern, is changed to 2.
If the direction or three directions are used, the wiring will not be disconnected even if the sputtered film is deposited anisotropically. As described above, the effects of this invention are remarkable.

[Brief explanation of drawings]

FIG. IA and FIG. IB are explanatory diagrams of a method for manufacturing a liquid crystal display device according to the first invention, and FIG. 1C and FIG. IE diagram is second
FIG. 2A is a plan view of a main part showing one pixel of a liquid crystal display section of an active matrix color liquid crystal display device to which this invention is applied, and FIG. 2B is an explanatory diagram of a method for manufacturing a liquid crystal display device according to the invention. Figure 2A is a cross-sectional view of the part taken along the nB-10B cutting line and the surrounding area of the seal, Figure 2C is a cross-sectional view taken along the c-nc line of Figure 2A, and Figure 3 is shown in Figure 2A. A plan view of the main part of a liquid crystal display section in which a plurality of pixels are arranged, FIGS. 4 to 6 are plan views depicting only a predetermined layer of the pixel shown in FIG. 2A, and FIG. 7 is a plan view of the pixel electrode shown in FIG. 3. FIG. 8 is an equivalent circuit diagram showing the liquid crystal display section of an active matrix color liquid crystal display device, and FIG. 9 is a diagram showing the pixel shown in FIG. 2A. The equivalent circuit diagram, FIG. 10, is a time chart showing the related voltage of the scanning signal line by the DC cancellation method. SUB...Transparent glass substrate GL...Scanning signal line DL...Video signal line GL...Insulating film GT...Gate electrode AS...I-type semiconductor layer SD...Source electrode or drain electrode psv...
Protective film BM...Light shielding film LC...Liquid crystal TPT...Thin film transistor ITO...Transparent pixel electrode g. d... Conductive film C add... Holding capacitor element Cgs... Parasitic capacitance C pix... Liquid crystal capacitance DUP... Drain terminal base pattern ISP... Isolated pattern

Claims (1)

[Claims] 1. In a method for manufacturing an active matrix liquid crystal display device in which a thin film transistor and a pixel electrode are constituent elements of a pixel, a nitride nitride constituting an insulating film used as a gate insulating film of the thin film transistor is provided. A semiconductor layer made of the silicon film of the thin film transistor is formed on the silicon film, and at the same time, an isolated pattern made of the silicon film is formed at the periphery of the resist for dry etching the silicon nitride film and above the conductive film constituting the signal line. 1. A method of manufacturing a liquid crystal display device, comprising: forming a liquid crystal display device. 2. In a method for manufacturing an active matrix type liquid crystal display device in which a thin film transistor and a pixel electrode are one constituent element of a pixel, a silicon film is formed on a silicon nitride film constituting an insulating film used as a gate insulating film of the thin film transistor. and dry etching the silicon nitride film to form an insulating film to be used as the gate insulating film. A method for manufacturing a liquid crystal display device, characterized in that the semiconductor layer is formed by selectively etching a film.