JPH0357610B2 - - Google Patents

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Publication number
JPH0357610B2
JPH0357610B2 JP61275447A JP27544786A JPH0357610B2 JP H0357610 B2 JPH0357610 B2 JP H0357610B2 JP 61275447 A JP61275447 A JP 61275447A JP 27544786 A JP27544786 A JP 27544786A JP H0357610 B2 JPH0357610 B2 JP H0357610B2
Authority
JP
Japan
Prior art keywords
layer
electron beam
chloromethylated polystyrene
pattern
sensitive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61275447A
Other languages
Japanese (ja)
Other versions
JPS63129622A (en
Inventor
Satoshi Sudo
Shunichi Nagamine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27544786A priority Critical patent/JPS63129622A/en
Publication of JPS63129622A publication Critical patent/JPS63129622A/en
Publication of JPH0357610B2 publication Critical patent/JPH0357610B2/ja
Granted legal-status Critical Current

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  • Electron Beam Exposure (AREA)

Description

【発明の詳細な説明】 〔概要〕 電子線描画法の際電子がレジスト層に滞電する
ことを防止するために下層にクロロメチル化ポリ
スチレンを用いる。
[Detailed Description of the Invention] [Summary] Chloromethylated polystyrene is used as the lower layer to prevent electrons from accumulating in the resist layer during electron beam lithography.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に係り、より詳
しく述べると、電子線描画法を用いたレジストの
パターニング方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for patterning a resist using electron beam lithography.

〔従来の技術〕[Conventional technology]

レジストの電子線描画法は電子線感光性層に電
子線で描画して露光し、それを現像してレジスト
パターンを形成する手法であり、基本的にはフオ
トレジスタのパターニングと同一であるが、光で
はなく電子線を用いて露光するので微細パターン
の露光が可能であるという特徴を有している。
The resist electron beam writing method is a method of drawing an electron beam on an electron beam-sensitive layer, exposing it, and developing it to form a resist pattern, and is basically the same as photoresist patterning. Since exposure is performed using electron beams instead of light, it has the characteristic that it is possible to expose fine patterns.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、電子線露光は光による露光のよ
うに一括露光ではなく、電子線を走査して露光す
る必要があるため、処理速度が遅いほかに、広い
露光面積を100μm□程度の小区間(サブフイー
ルド)に分割し、その小区画内の露光を終えた後
次の小区間の露光を行なうというようにして小区
画間を移動して最終的に全体の露光を行なつてい
る。そのため、小区画間でパターンが歪むのみな
らず、さらに隣接する小区画間で電子線の描画位
置が大きくズレる(不整合が生ずる)おそれがあ
る。特に、多層レジストプロセスで電子線感光層
あるいは中間層、下層が厚くなると、前に走査さ
れた電子によつて感光層、中間層、下層中に滞電
し、隣の小区間の描画の際に走査中の電子線をゆ
がめるという不都合が生ずる。
However, electron beam exposure is not a one-shot exposure like light exposure, but requires exposure by scanning the electron beam, so in addition to slow processing speed, the wide exposure area can be divided into small sections (subfields) of about 100 μm square. ), and after completing the exposure in that small section, the next small section is exposed, moving between the small sections, and finally exposing the whole. Therefore, not only the pattern is distorted between the small sections, but also there is a possibility that the electron beam writing position is greatly shifted between adjacent small sections (misalignment occurs). In particular, when the electron beam-sensitive layer, intermediate layer, or lower layer becomes thicker in a multilayer resist process, the previously scanned electrons accumulate in the photosensitive layer, intermediate layer, or lower layer, and when drawing the next small section, This results in the disadvantage of distorting the electron beam during scanning.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上記問題点を解決するために、電子
線感光層の下方にクロロメチル化ポリスチレン層
を形成する。この下層クロロメチル化ポリスチレ
ンが、フオトレジストやポリイミドに比べて、電
子線描画の際の滞電増加を防止する。その機構
は、おそらく、 の反応によつて電子がポリマー中に取り込まれる
ことによると考えられる。(塩素がとれたメチレ
ン基は他のポリマーと反応して橋かけを形成する
と考えられる。) クロロメチル化ポリスチレンのクロルメチル化
率(上記式中n/(m+n))が高いほど滞電防
止効果は大きい。本発明の目的からはこのクロロ
メチル化率が50%以上であることが望ましい。
In order to solve the above problems, the present invention forms a chloromethylated polystyrene layer below the electron beam-sensitive layer. This lower layer chloromethylated polystyrene prevents an increase in electrical charge during electron beam lithography, compared to photoresist or polyimide. The mechanism is probably This is thought to be due to the fact that electrons are incorporated into the polymer through the reaction of . (It is thought that the methylene groups from which chlorine has been removed react with other polymers to form crosslinks.) The higher the chloromethylation rate (n/(m+n) in the above formula) of chloromethylated polystyrene, the better the anti-static effect. big. For the purpose of the present invention, it is desirable that the chloromethylation rate is 50% or more.

本発明では、多層レジストプロセスで上層のSi
含有の電子線感光層を電子線描画法でパターニン
グした後、そのパターンを下層のクロロメチル化
ポリスチレンに酸素反応性イオンエツチング
(O2 RIE、Reactive Ion Etching)転写するの
で、解像度は電子線感光層の厚みで決まることに
なり、電子線感光層とクロロメチル化ポリスチレ
ン層からなる全体のレジスト層の厚さは大きくて
も、高い解像度を達成することができる。
In the present invention, the upper layer of Si is
After patterning the containing electron beam photosensitive layer using an electron beam writing method, the pattern is transferred to the underlying chloromethylated polystyrene layer using oxygen reactive ion etching (O 2 RIE, Reactive Ion Etching). Even if the total resist layer thickness consisting of the electron beam-sensitive layer and the chloromethylated polystyrene layer is large, high resolution can be achieved.

また、厚いクロロメチル化ポリスチレン層をパ
ターニングする上で、必要に応じて、電子線感光
層とクロメチル化ポリスチレン層の間に低温成長
のアモルフアスシリコンあるいは塗布有機ガラス
(SOG;spin on glass)からなる中間層を介在さ
せる三層構造にも適用できる。これらの中間層は
上層のパターンを転写した後下層パターニング
(O2RIE)の際のストツパーマスクとして働くも
のである。
In addition, when patterning a thick chloromethylated polystyrene layer, if necessary, low-temperature grown amorphous silicon or spin-on glass (SOG) may be used between the electron beam-sensitive layer and the chloromethylated polystyrene layer. It can also be applied to a three-layer structure with an intervening layer. These intermediate layers serve as a stopper mask during lower layer patterning (O 2 RIE) after transferring the upper layer pattern.

〔実施例〕〔Example〕

第1図を参照すると、アルミニウム基板1上に
クロルメチル化ポリスチレン層(クロロメチル化
率50%)2を約2μmの厚みに形成し、その上に
低温CVD法でアモルフアスシリコン層3を約
0.1μmの厚みに形成し、さらにその上に電子線感
光性レジスト層(PMMS、CMS−EX、OEBR
−100)4を0.8〜1.0μmの厚みに形成した。
Referring to FIG. 1, a chloromethylated polystyrene layer (50% chloromethylation rate) 2 is formed on an aluminum substrate 1 to a thickness of about 2 μm, and an amorphous silicon layer 3 is formed on it by a low-temperature CVD method.
It is formed to a thickness of 0.1 μm, and an electron beam-sensitive resist layer (PMMS, CMS-EX, OEBR
-100) 4 was formed to a thickness of 0.8 to 1.0 μm.

電子線露光装置を用いて、露光面(main
field)を102.4μm□ の小区画(subfield)に分割
し、電磁偏光及び静電偏向を用いて電子線を走査
し描画した。こうして電子線露光後、電子線感光
性レジスト層4を現像し、焼付け、第1図Aの如
くパターニングした。
The exposure surface (main
field) was divided into 102.4 μm square subfields, and an electron beam was scanned and drawn using electromagnetic polarization and electrostatic deflection. After exposure to electron beams, the electron beam-sensitive resist layer 4 was developed, baked, and patterned as shown in FIG. 1A.

次いで、電子線感光性レジスト層4のパターン
をマスクとしてフレオン系ガスを用いて中間層3
を選択的にエツチングした後、電子線感光性レジ
スト層4と中間層3の2層パターンをマスクとし
てO2RIEエツチングによりクロロメチル化ポリス
チレン層2を選択的にエツチングし、パターニン
グした。O2RIEエツチングにより電子線感光性レ
ジスト層4もエツチングされるが、中間層3のア
モルフアスシリコンがストツパーとして働く。
Next, using the pattern of the electron beam-sensitive resist layer 4 as a mask, a Freon gas is used to form the intermediate layer 3.
After selectively etching, the chloromethylated polystyrene layer 2 was selectively etched and patterned by O 2 RIE etching using the two-layer pattern of the electron beam-sensitive resist layer 4 and the intermediate layer 3 as a mask. The electron beam sensitive resist layer 4 is also etched by O 2 RIE etching, but the amorphous silicon of the intermediate layer 3 acts as a stopper.

こうして得られたパターンの小区画間のパター
ンのズレは0.1μm以下であつた。上記実施例にお
いて中間層3としてアモルフアスシリコンの代り
に有機ガラスをスピンコートし、焼付けたガラス
を用いた場合にも、全く同様の成果が得られた。
The pattern deviation between the small sections of the pattern thus obtained was 0.1 μm or less. Exactly the same results were obtained when the intermediate layer 3 in the above embodiment was made of glass spin-coated with organic glass and baked in place of amorphous silicon.

なお、比較のために、上記実施例において下層
2としてクロロメチル化ポリスチレンの代りにフ
オトレジスト(OFPR800、NPR820)を用いて
同様の実験を行なつたところ、小区画間のパター
ンのズレは約0.6〜0.7μmであつた。
For comparison, a similar experiment was conducted using photoresist (OFPR800, NPR820) instead of chloromethylated polystyrene as the lower layer 2 in the above example, and the pattern deviation between small sections was approximately 0.6. It was ~0.7 μm.

また、上記実施例と同様にして、但し、クロロ
メチル化ポリスチレンのクロロメチル化率をいろ
いろに代えて実験したところ、小区画間のパター
ンのズレ量は第2図に示す如くであつた。
Further, when experiments were conducted in the same manner as in the above example, except that the chloromethylation rate of the chloromethylated polystyrene was varied, the amount of pattern deviation between the small sections was as shown in FIG.

また、上記実施例と同様に、但し、中間層3を
形成しないで、そしてクロロメチル化ポリスチレ
ン層2のパターニングをシリコン含有の電子線感
光レジストをマスクとして酸素反応性イオンエツ
チングにより行なつた。パターニング後、パター
ンの全体の厚みは約2μm、小区画間のパターン
のズレは0.1μm以下であつた。
Further, in the same manner as in the above embodiment, the intermediate layer 3 was not formed, and the chloromethylated polystyrene layer 2 was patterned by oxygen-reactive ion etching using a silicon-containing electron beam photoresist as a mask. After patterning, the total thickness of the pattern was about 2 μm, and the pattern deviation between small sections was 0.1 μm or less.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電子線描画法においてレジス
ト層の厚みを大きくしてもレジスト層の滞電増加
を防止してパターンの歪(不整合)を防止するこ
とができる。
According to the present invention, even if the thickness of the resist layer is increased in the electron beam lithography method, it is possible to prevent an increase in charge buildup in the resist layer and to prevent pattern distortion (misalignment).

【図面の簡単な説明】[Brief explanation of drawings]

第1図A,Bは実施例のパターニングの主要工
程における半導体装置の側断面図、第2図はクロ
ロメチル化ポリスチレンのクロロメチル化率に関
するパターンのズレ量を表わすグラフ図である。 1……アルミニウム基板、2……クロロメチル
化ポリスチレン層、3……中間層、4……電子線
感想層。
FIGS. 1A and 1B are side sectional views of a semiconductor device in the main steps of patterning in the example, and FIG. 2 is a graph showing the amount of pattern deviation with respect to the chloromethylation rate of chloromethylated polystyrene. DESCRIPTION OF SYMBOLS 1... Aluminum substrate, 2... Chloromethylated polystyrene layer, 3... Intermediate layer, 4... Electron beam impression layer.

Claims (1)

【特許請求の範囲】 1 基板上にクロロメチル化ポリスチレン層を形
成し、その上に電子線感光層を形成し、該電子感
光層を電子線露光してパターニングし、該パター
ニングされた電子線感光層をマスクに上記クロロ
メチル化ポリスチレン層をパターニングする工程
を含むことを特徴とする半導体装置の製造方法。 2 前記クロロメチル化ポリスチレン層と前記電
子線感光層の間に中間層を形成し、前記電子線感
光層のパターンを一旦該中間層に転写した後、更
に前記クロロメチル化ポリスチレン層をパターニ
ングする特許請求の範囲第1項記載の方法。
[Claims] 1. A chloromethylated polystyrene layer is formed on a substrate, an electron beam-sensitive layer is formed thereon, the electron-sensitive layer is patterned by electron beam exposure, and the patterned electron-beam photosensitive layer is patterned. A method for manufacturing a semiconductor device, comprising the step of patterning the chloromethylated polystyrene layer using the layer as a mask. 2. A patent for forming an intermediate layer between the chloromethylated polystyrene layer and the electron beam-sensitive layer, and after once transferring the pattern of the electron beam-sensitive layer to the intermediate layer, the chloromethylated polystyrene layer is further patterned. The method according to claim 1.
JP27544786A 1986-11-20 1986-11-20 Manufacture of semiconductor device Granted JPS63129622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27544786A JPS63129622A (en) 1986-11-20 1986-11-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27544786A JPS63129622A (en) 1986-11-20 1986-11-20 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS63129622A JPS63129622A (en) 1988-06-02
JPH0357610B2 true JPH0357610B2 (en) 1991-09-02

Family

ID=17555653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27544786A Granted JPS63129622A (en) 1986-11-20 1986-11-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63129622A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008105266A1 (en) * 2007-02-27 2008-09-04 Nissan Chemical Industries, Ltd. Resist lower layer film forming composition for electron lithography

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143826A (en) * 1981-02-28 1982-09-06 Dainippon Printing Co Ltd Formation of resist pattern on gapped semiconductor substrate
JPS59104126A (en) * 1982-12-07 1984-06-15 Nippon Telegr & Teleph Corp <Ntt> Patternizing method of four layers
JPS6014238A (en) * 1983-06-28 1985-01-24 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Formation of multilayer resist on substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143826A (en) * 1981-02-28 1982-09-06 Dainippon Printing Co Ltd Formation of resist pattern on gapped semiconductor substrate
JPS59104126A (en) * 1982-12-07 1984-06-15 Nippon Telegr & Teleph Corp <Ntt> Patternizing method of four layers
JPS6014238A (en) * 1983-06-28 1985-01-24 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Formation of multilayer resist on substrate

Also Published As

Publication number Publication date
JPS63129622A (en) 1988-06-02

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