KR100562299B1 - A method for forming a trench of a semiconductor device, and a method for forming a mask pattern thereof - Google Patents

Abstract

The present invention provides a trench fabrication method of a semiconductor device and a mask pattern forming method for accurately compensating for line width patterning errors generated in a semiconductor substrate when one is an isolated pattern and the other is a dense pattern, and improves the manufacturing uniformity of the semiconductor pattern. It is about. In the method of forming a mask pattern of a semiconductor device according to the present invention, when one opening of one side of the main pattern of the mask has a region that is twice or more wider than the width of the main pattern, dividing the mask pattern into two based on the minimum line width of the main pattern ; Stacking a plurality of resist layers during the mask exposure to develop a photosensitive agent; And removing the lower layer resist of the resist layer. According to the present invention, when one part of the mask pattern has a wide opening, the mask pattern is divided into two and the thickness of the photosensitive agent can be reduced to maintain a uniform photosensitive agent inclination regardless of the width of the opening during patterning. Moreover, by using a two-layered resist, hardening baking can be omitted after mask exposure, and the inclination of a resist can be improved.

Mask, pattern, trench, hard burn, resist, optical proximity compensation

Description

A method for forming a trench of a semiconductor device and a method of forming a mask pattern thereof {A method for forming a trench of a semiconductor device, and a method for forming a mask pattern}

1A to 1D are diagrams illustrating a method of forming a trench in a semiconductor device using a mask according to the prior art.

2 is an electron micrograph of a trench of a semiconductor device manufactured according to the prior art.

3 shows a mask according to the invention.

4A to 4E illustrate a method of forming a trench in a semiconductor device using a mask according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a trench and a mask pattern forming method of a semiconductor device, and more specifically, to accurately compensate for linewidth patterning errors generated in a semiconductor substrate when one is an isolated pattern and the other is a dense pattern, It relates to a trench manufacturing method of a semiconductor device for improving the manufacturing uniformity of the pattern and a mask pattern forming method thereof.

In general, the mask pattern forming technique has a close influence on the accuracy of the pattern formed on the semiconductor substrate. In particular, if the optical proximity effect of the mask pattern is not properly considered, pattern linewidth distortion occurs due to the lithography original exposure intention, resulting in a shortening of the linearity of the line width, thereby adversely affecting the characteristics of the semiconductor device. do.

On the other hand, semiconductor photolithography technology can precisely control the amount of light projected by the mask by precisely mask design. Optical Proximity Correction technology and Phase Shifting Mask technology have emerged for this purpose, and various methods for minimizing the distortion of light due to the pattern shape drawn on the mask have been sought.

In recent years, the development of a chemically amplified resist having excellent photosensitivity to light having a wavelength of 248 nm or 194 nm has emerged. Recently, various modified exposure techniques have been developed to keep the gradient of the resist pattern close to vertical.

In particular, when the semiconductor silicon substrate needs to be etched as close as 1 μm with a trench in order to define an oxide insulating layer in the active region, the slope of the trench is closely related to the characteristics of the well junction. . Therefore, it is necessary to sharply adjust the inclination of the resist pattern due to the difference in density of the pattern from the exposure step.

1A to 1D are diagrams illustrating a method of forming a trench in a semiconductor device using a mask according to the prior art.

First, as shown in FIG. 1A, a resist layer formed on a semiconductor substrate is patterned by about 5000 kV using a mask including a light shielding pattern 15 and a light-transmitting substrate 16, and a nitride film 13 / of about 2200 kPa is disposed below the resist layer. It consists of the oxide film 12 / silicon substrate 11 of about 100 microseconds.

In addition, the exposed portions A, B, and C of the resist and the non-exposed portion 14 are exposed to the exposed portions A, B, C and the non-exposed portion through a post exposure bake (PEB) process 17. 14) After the molecular movement of the photosensitive component of the resist to the boundary portion, and undergoes the development process through the curing burn 18 of Figure 1b, at this time, the solvent (Solvent) inside the resist pattern 14 is moved (19) Vaporize. At this time, the area A where the resist is removed is wider than the area B and C where the resist remains, and the vaporization rate is faster.

Therefore, the isolation pattern without resist around has a relatively strong stress received inside the resist, thereby reducing the tilt of the resist and rounding the corner angle. That is, when there is a resist around, the inclination of the resist is made relatively sharp during the hardening process 18 due to relatively less condensing force.

Here, the purpose of the curing burn 18 is to increase the strength of the resist by evaporating the solvent.

Next, referring to FIG. 1C, a subsequent etching process is performed to continuously etch the oxide film 2 of about 2200 μm of the nitride film 13 and about 100 μm, and then trench the silicon substrate 11 as shown in FIG. 1D. Etched.

2 is an electron scanning micrograph of a trench of a semiconductor device manufactured according to FIGS. 1A to 1D according to the prior art, which has a tilt θ when one side is an isolated pattern, and a tilt (when another side is a dense pattern). [theta] ', the inclination [theta] is smaller than the inclination [theta]' and has a problem of obtaining a gentle inclination.

An object of the present invention for solving the above problems is to precisely compensate for the line width patterning error generated in the semiconductor substrate when one side is an isolated pattern and the other is a dense pattern, thereby producing a fine line width, thereby improving the manufacturing uniformity of the semiconductor pattern It is an object of the present invention to provide a mask of a semiconductor device and a pattern forming method thereof.

As a means for achieving the above object, the mask pattern forming method of a semiconductor device according to the present invention,

When one opening of the main pattern of the mask has an area that is at least two times wider than the width of the main pattern, dividing it into two based on the minimum line width of the main pattern;

Stacking a plurality of resist layers during the mask exposure to develop a photosensitive agent; And

Removing the lower layer resist of the resist layer

It includes.

Here, the micro-openings are formed in one of the main patterns in a wide opening of 0.5 μm or more with respect to the dense pattern and the isolation pattern having a line width ratio of the main pattern of 1: 1.2.

Here, the step of removing the lower layer resist is characterized in that it is carried out in a state that does not hard bake (Hard Bake).

Here, the interval of the main pattern divided into two is characterized in that it has a range of 0.04 to 0.1㎛.

The plurality of resist layers may include at least one photosensitive resist film and at least one spin on glass (SOG) film.

Here, the upper layer resist of the plurality of resist layers is characterized by having photosensitivity, the thickness of which is in the range of 0.1 to 0.5㎛.

On the other hand, as another means for achieving the above object, a trench manufacturing method of a semiconductor device according to the present invention,

Sequentially depositing an oxide film, a nitride film, and a plurality of resist layers on the semiconductor substrate;

Patterning using an upper resist layer among the plurality of resist layers;

Selectively fabricating a mask in which a separate fine opening is formed in addition to the original opening;

Selectively etching a lower resist layer among the plurality of resist layers in a state where the exposure amount is controlled using the selectively manufactured mask;

Sequentially etching the nitride film and the oxide film to expose the semiconductor substrate; And

Etching the exposed semiconductor substrate to form a trench, and filling the trench formation region with an insulating material

It includes.

The plurality of resist layers may include at least one photosensitive resist film and at least one spin-on glass film.

Here, the plurality of resist layers is characterized in that to increase the etch selectivity during the trench etching using an organic polymer (Organic Polymer).

Here, the step of selectively etching the resist layer of the lower layer is characterized in that it is carried out in a state not hardened baking.

Here, the minute openings are formed in the outermost line when the line width ratio of the dense shading pattern maintains the dense pattern or the isolation pattern having a ratio of 1: 1.2.

Here, the width of the fine opening is characterized in that 0.05㎛ or more.

The trench may be shallow trench isolation (STI) having a constant slope regardless of all line width pitches.

According to the present invention, when one part of the mask pattern has a wide opening, the mask pattern is divided into two and the thickness of the photosensitive agent is reduced to maintain a uniform photosensitive agent inclination regardless of the width of the opening at the time of patterning. Moreover, by using a two-layered resist, hardening baking can be omitted after mask exposure, and the inclination of a resist can be improved.

Hereinafter, with reference to the accompanying drawings, a trench manufacturing method and a mask pattern forming method of a semiconductor device according to an embodiment of the present invention will be described in detail.

4A to 4E illustrate a method of forming a trench in a semiconductor device using a mask according to the present invention.

First, referring to FIG. 4A, a semiconductor substrate composed of a photosensitive resist film 1100 Å / 500 SO SOG (Spin On Glass: 38) / 2200 Å nitride film 33/100 산화 oxide film 32 / silicon substrate 31 The exposure amount is controlled by using a mask selectively fabricated on the mask, wherein the mask is formed of the light shielding pattern 35 and the light-transmitting substrate 36.

Further, in addition to the original openings 36D, 36E, and 36F of the mask, separate fine openings 36G are formed, which are dense with the ratio of the line width of the dense shading pattern having a ratio of 1: 1.2 (0.18 µm Line: 0.214 Space). When maintaining a pattern or an isolated pattern, apply to the outermost line. At this time, the width of the fine opening 36G is kept at 0.05 μm.

According to the present invention, patterning is performed using a two-layer resist (photosensitive resist film 34 of 1100 microseconds / SOG 38 of 500 microseconds). The main purpose of the two-layer resist is to significantly reduce the thickness of the resist so as to have an advantage of the etching selectivity in the trench etching by using an organic polymer.

Then, after exposing through a mask and performing post-exposure baking (PEB) 37 before development, the portions exposed through the openings 36D, 36E, and 36F form latent images D, E, and F. The portion exposed through the fine opening 36G forms a latent image G, thereby distinguishing it from the resist 34 'of the portion not exposed.

Unlike the conventional manufacturing method, the mask according to the present invention significantly reduces the thickness of the upper layer resist to about 1100 mm (= 0.11 µm) and exposes the upper part of the uppermost part of the outermost resist pattern of the dense pattern during exposure, thereby exposing the outermost pattern. The condensation force applied to the photosensitive resist can be minimized by simultaneously reducing the unit area of the photosensitive agent to be formed and the height of the photosensitive agent.

3 is a plan view showing a mask according to the present invention. With respect to the dense pattern and the isolation pattern having the line width ratio of 1: 1.2, one portion of the pattern exposed to the wide opening (0.5 탆 or more) forms the fine opening 36G. Here, the cross section of FIGS. 4A-4E is shown according to cross section A-B.

Next, FIG. 4B is a pattern state of the photosensitive resist which is subjected to a developing process and not subjected to a hard bake. The opening images D, E, and F are formed to expose the SOG 38 substrate and simultaneously form the opening image G, which is partially exposed.

Next, as shown in FIG. 4C, the SOG 38 in the lower layer is selectively etched without a hard bake. Since the hardening burn is not performed, the edge and the slope of the resist may be kept sharp, and the opening image G may not affect the substrate when the SOG 38 is etched by the etching ratio.

Next, referring to FIG. 4D, the semiconductor substrate 31 is exposed by continuing etching the 2200 nm nitride film 33/100 nm oxide film 32.

Next, when the semiconductor substrate 31 is trench etched in FIG. 4E, shallow trench isolation (STI) regions D ′, E ′, and F ′ having a constant slope are formed regardless of all line width pitches. Subsequently, the STI regions D ', E', and F 'are filled with an insulating material, and in the case of the isolated pattern and the dense pattern, both have the same slope.

As a result, in the present invention, when one part of the mask pattern has a wide opening, the mask pattern is divided into two, the thickness of the photosensitive agent is reduced, and the hard burn after the mask exposure is omitted by using a two-layer resist. The resist inclination can be improved. In addition, the present invention can fabricate a uniform STI to secure symmetric NMOS and PMOS source / drain regions when forming well junctions.

While the invention has been described above, these examples are intended to illustrate rather than limit this invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments are possible without departing from the technical details of the present invention. Therefore, the scope of protection of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

According to the present invention, when one portion of the mask pattern has a wide opening, by dividing the mask pattern into two and reducing the thickness of the photoresist, it is possible to maintain a uniform photoresist inclination regardless of the width of the opening during patterning. .

Further, according to the present invention, by using a two-layered resist, curing burn can be omitted after mask exposure, and the inclination of the resist can be improved.

In addition, according to the present invention, a uniform STI may be manufactured to secure symmetric NMOS and PMOS source / drain regions when forming well junctions.

Claims (13)

In the pattern formation method of the mask for semiconductors, When one side of the main pattern has a wide opening of 0.5 μm or more for the dense pattern and the isolation pattern having a line width ratio of the main pattern of the mask of 1: 1.2, a fine opening is formed in the main pattern to reference the line width of the main pattern. Dividing into two; Stacking a plurality of resist layers during the mask exposure to develop a photosensitive agent; And Removing the lower layer resist of the resist layer Mask pattern forming method comprising a. delete The method of claim 1, Removing the lower layer resist is a mask pattern forming method, characterized in that is carried out in a state that does not perform a hard bake (Hard Bake). The method of claim 1, The spacing of the main pattern divided into two has a mask pattern forming method characterized in that it has a range of 0.04 to 0.1㎛. The method of claim 1, And the plurality of resist layers comprises at least one photosensitive resist film and at least one spin on glass (SOG) film. The method according to claim 1 or 5, The upper layer resist of the plurality of resist layers has photosensitivity and has a thickness in the range of 0.1 to 0.5 mu m. In the method of forming a trench of a semiconductor element, Sequentially depositing an oxide film, a nitride film, and a plurality of resist layers on the semiconductor substrate; Patterning using an upper resist layer among the plurality of resist layers; Selectively fabricating a mask in which a separate fine opening is formed in addition to the original opening; Selectively etching a lower resist layer among the plurality of resist layers in a state where the exposure amount is controlled using the selectively manufactured mask; Sequentially etching the nitride film and the oxide film to expose the semiconductor substrate; And Etching the exposed semiconductor substrate to form a trench, and filling the trench formation region with an insulating material Trench formation method of a semiconductor device comprising a. The method of claim 7, wherein And the plurality of resist layers comprises at least one photosensitive resist film and at least one spin-on glass film. The method according to claim 7 or 8, The plurality of resist layers are trench forming method of a semiconductor device, characterized in that to increase the etching selectivity during the trench etching using an organic polymer (Organic Polymer). The method according to claim 7 or 8, Selectively etching the underlying resist layer is a method of forming a trench in a semiconductor device, characterized in that the step is performed without a hardening burn. The method of claim 7, wherein The fine opening may be formed in the outermost line when the line width ratio of the dense light shielding pattern maintains a dense pattern or an isolation pattern having a ratio of 1: 1.2. The method according to claim 7 or 11, wherein The trench has a width of 0.05 μm or more. The method of claim 7, wherein And the trench is shallow trench isolation (STI) having a constant slope regardless of all line width pitches.

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