JPH0357490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This is a method for controlling the priority order of main memory access processing. A so-called block fetch, which reads a data block of a predetermined length in multiple accesses.
By processing the first access with priority over other block fetches in progress, it is possible to reduce the access time for the data read first.

[Industrial application field]

The present invention relates to a method for controlling the priority order of main memory access processing in a computer system.

In the computer system, when the storage control device processes access to the main storage device, a central processing unit that accesses through the storage control device;
A method is adopted in which a plurality of ports are provided for each processing device such as a channel processing device, access requests are held in the ports, and the plurality of requests are processed in parallel within the parallel operation capability of the main storage device.

Even in such a system, access requests that cannot be processed in parallel need to be processed serially in terms of time, so requests are usually processed with priority in the order in which they are input to ports.

[Problems to be solved by conventional technology and invention]

FIG. 2 is a block diagram of an example of the configuration of a computer system.

Central processing unit (hereinafter referred to as CPU)
1. The channel processing device 2 and the like are connected to the storage control device 3 and access the main storage device 4 via the storage control device 3.

As shown in FIG. 3, the storage control device 3 is connected to each CPU 1 through, for example, two sets of ports 5 and 6, and processes access requests input from the CPU 1 to each port 5 and 6.

As is well known, in a system in which the CPU 1 has a high-speed buffer (or cache memory), data is generally read from the main memory 4 in units of data blocks of a fixed length, as so-called block fetches.

This data block is a continuous address area block of a certain length (for example, 8 words) that contains the data word (for example, 8 bytes/word) that the CPU 1 wants to access. By storing the data in a high-speed buffer, data in the vicinity of the actually accessed word can be immediately used on the buffer.

Since the access request is input to port 5 or 6 as a block fetch request specifying the address of the target data word to be accessed, the storage controller 3 starts from the specified address and reads only the lower three bits of the word address. The block fetch is processed by changing the block and performing eight read accesses.

For the above control, counters 7 and 8 are provided corresponding to ports 5 and 6, and are normally reset to "0", for example. When processing a block fetch request, counters 7 and 8 are set for each access. +1
and monitor eight accesses.

Such control allows the requesting CPU 1 to obtain the target data word first and proceed with the processing in parallel with reading other words of the same block.

However, if CPU 1 issues a block fetch request to port 5, for example, and then issues another block fetch request to port 6, and the requests are not processed in parallel, then after processing the block fetch of port 5, for example, in the order in which they arrive, Since port 6 is processed, there is a problem in that the reading of the target data word related to the block fetch of port 6 is significantly delayed.

An example of this situation is shown in Figure 4a. port 5
At time 10, a command specifying a block fetch and a storage address are set (this access request is referred to as A). Assume that "010" is specified as the address.

The priority control unit 9 of the storage control device 3 issues an address and a necessary control signal to the main storage device 4 to perform an access operation, as shown by a line 12, by subjecting the access request A to predetermined priority control. to start.

The counter 7 is incremented by 1 for each access, and the storage address of the port 5 is sequentially updated to a predetermined value within the range of the lower three bits.

Port 6 at time 13, delayed by access request A.
Hebrew fetch request (call this request B)
When this is input, the priority control unit 9 does not accept the access request A since it has not been completed, and waits until time 14 to access the first word of the access request B.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

Connect to ports 5, 6 and counters 7, 8,
A block fetch control section 20 is provided, and the priority control of the priority control section 21 is controlled by the output thereof.

[Effect]

When the block fetch control unit 20 detects that there is a block fetch request on both ports based on the signals from ports 5 and 6, it checks the counts of counters 7 and 8, and one of them is '0' and the other is non-'.
When detecting that the value is 0', a signal is issued to the priority control unit 21 to preferentially select port 5 or 6 for the counter whose value is '0'.

By this control, access request B in the case shown in FIG. 4a is also processed preferentially for the first word.

〔Example〕

In FIG. 1, the priority control section 21 operates in the same manner as the conventional priority control section 9 when the signal for changing the priority from the block fetch control section 20 is not outputted to the interrupt signal line 22.

Block fetch control 20 uses signal lines 23, 2
4 monitors commands input from the CPU 1 to ports 5 and 6, and detects a case where both of them result in a block fetch request.

While detecting that there are block fetch requests on both ports 5 and 6, block fetch control section 20 checks the counts of counters 7 and 8 of both ports via signal lines 25 and 26.

As a result, if the value of one counter is non-'0' and the other counter is '0', the counter 7 or 8 with the count value '0' is sent to the interrupt signal line 22.
generates a signal specifying port 5 or 6 corresponding to port 5 or 6.

As mentioned above, counters 7 and 8 are always '0'.
When the block fetch requests for the corresponding ports 5 and 6 are processed, each access reception by the priority control unit 21 is incremented by 1.

Therefore, the port designated as the interrupt signal line 22 above issues a block fetch request and still has 1
The port is never serviced.

The priority control section 21 interrupts the block fetch processing up to that point in response to a signal on the interrupt signal line 22, and prioritizes processing of the block fetch request of the designated port 5 or 6.

As a result, when the port receives read access for the first word, the corresponding counter 7 or 8 is incremented by 1 and becomes non-'0', so that the designation by the interrupt signal line 22 disappears.

Therefore, after reading one word, the priority control unit 21 returns to normal priority control and continues processing the block fetch request of the interrupted port.

An example of the processing under the above control is shown in FIG. 4b. The figure, like FIG. 4a, shows a case where block fetch access request A is issued at time 10, and access request B is issued at time 13 later than that.

As shown by line 30, processing of access request A is started in the same manner as in FIG. It detects that the value of is '0' and raises a signal (indicated by line 31 in FIG. 4b) specifying port 6 on interrupt signal line 22.

In response to this signal 31, the priority control unit 21 at time 32 when the reading process for one word of request A is finished,
The processing of request A is interrupted, the processing of request B is started, and the first word of request B is read out.

At time 33 when this reading process ends, the counter 8 has already been incremented by 1 and the signal 31 has disappeared, so the priority control unit 21 returns to processing request A from time 33 using normal priority control. .

Therefore, the processing after the second word of request B is waited until time 34 when the service of request A ends, as in the past, but the first word is processed at time 34 as described above.
Since the data is read out to the CPU 1 at step 3, the CPU 1 can proceed with the processing from this point onwards, and a drop in execution efficiency due to data waiting can be prevented.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when the processing unit of a computer system performs a block fetch on the main memory, the subsequent block fetch request when a plurality of consecutive block fetch requests is The reading of data is processed quickly, and the reduction in execution efficiency due to data waiting by the processing device is reduced, which has a significant industrial effect of improving the performance of the computer system.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram of an example of the configuration of a computer system.
The figure is a block diagram of an example of a conventional configuration, and FIG. 4 is a time chart. In the figure, 1 is a CPU, 2 is a channel processing device, 3 is a storage control device, 4 is a main storage device, 5, 6
1 is a port, 7 and 8 are counters, 9 and 21 are priority control units, 20 is a block fetch control unit, and 22 is an interrupt signal line.

Claims (1)

[Claims] 1. It has a plurality of ports 5 and 6 that hold access requests from the processing device 1 to the main storage device 4, and the access requests held in the ports 5 and 6 are sequentially processed. In the storage control device 3, when a predetermined access request for reading a data block of a predetermined length by multiple accesses is made to a plurality of ports 5 and 6, among the access requests made to the plurality of ports, A main memory access control system characterized in that: detecting (20) an access request for which the first access among the plurality of accesses has not been executed; and processing the first access with priority (21).