JPH0357254A - Lead frame for semiconductor - Google Patents
Lead frame for semiconductorInfo
- Publication number
- JPH0357254A JPH0357254A JP1193732A JP19373289A JPH0357254A JP H0357254 A JPH0357254 A JP H0357254A JP 1193732 A JP1193732 A JP 1193732A JP 19373289 A JP19373289 A JP 19373289A JP H0357254 A JPH0357254 A JP H0357254A
- Authority
- JP
- Japan
- Prior art keywords
- parts
- frame
- tip
- runner
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 238000005520 cutting process Methods 0.000 claims abstract description 22
- 238000002347 injection Methods 0.000 claims abstract description 20
- 239000007924 injection Substances 0.000 claims abstract description 20
- 238000007789 sealing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 18
- 238000004080 punching Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000001154 acute effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明はリード部とそれに連なる枠部とを備え一方の面
に装着された半導体素子が樹脂封止された後枠部が除去
される半導体用リードフレームに関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention provides a rear frame portion that includes a lead portion and a frame portion connected to the lead portion, and in which a semiconductor element mounted on one surface is sealed with resin. The present invention relates to a semiconductor lead frame from which is removed.
（従来の技術）
一般に、ＩＣ等の半導体部品１は、第８図に示すように
、半導体素子２を樹脂により封止したパッケージ３の側
面から多数本のリード脚４を導出した形状として供され
ている。かかる半導体部品１は、第９図に示すように、
リード部５ａとそれに連なる枠部５ｂとを備えたリード
フレーム５の一面に、半導体素子２を装着し、その半導
体素子２と各リード部５ａとをボンディングワイヤ６に
て接続した後、樹脂封止が行われ、しかる後、リードフ
レーム５のうちの不要な枠部５ｂを除去することにより
製作される。(Prior Art) Generally, as shown in FIG. 8, a semiconductor component 1 such as an IC is provided in the form of a package 3 in which a semiconductor element 2 is sealed with a resin, and a number of lead legs 4 are led out from the side surface of the package 3. ing. Such a semiconductor component 1, as shown in FIG.
A semiconductor element 2 is mounted on one surface of a lead frame 5 having a lead part 5a and a frame part 5b connected thereto, and after connecting the semiconductor element 2 and each lead part 5a with bonding wires 6, resin sealing is performed. After that, the lead frame 5 is manufactured by removing unnecessary frame portions 5b.
前記リードフレーム５を製作するにあたっては、第１０
図に示すように、下金型７とこれに接離する上金型８と
を有するプレス装置を用い、導電板９から不要部を上方
から下方に向けて打抜く方広が採用され、大量生産及び
加工精度の均一化が図られている。In manufacturing the lead frame 5, the 10th
As shown in the figure, a press machine having a lower die 7 and an upper die 8 that approaches and separates from the lower die 7 is used to punch out unnecessary parts from the conductive plate 9 from above to below. Efforts are being made to standardize production and processing accuracy.
而して、一般に打抜き加工にあっては、切断縁部にいわ
ゆるだれ及びかえりが生ずる。このため、前記リードフ
レーム５の切断縁部にあっても、第１１図に示すように
、上面側にだれ部１０が、下面側にかえり部１１が発生
することになる。この場合、リードフレーム５のうち半
導体素子２が装着される側の面にかえり部１１が生じて
いると、半導体素子２のリードフレーム５への装着時ヤ
、ボンディングワイヤ６の取付け時に、そのかえり部１
１に半導体素子２やボンディングワイヤ６が引っ掛かっ
てしまう不具合が起こる。従って、前述の打抜き方向は
、半導体素子２が装着されない側の面にかえり部１１が
来るように設定されている。Generally, during punching, so-called sagging and burrs occur at the cut edges. Therefore, even at the cut edge of the lead frame 5, as shown in FIG. 11, a sagging portion 10 is generated on the upper surface side and a burr portion 11 is generated on the lower surface side. In this case, if a burr 11 is formed on the side of the lead frame 5 on which the semiconductor element 2 is attached, the burr will be removed when the semiconductor element 2 is attached to the lead frame 5 or when the bonding wire 6 is attached. Part 1
A problem occurs in which the semiconductor element 2 or the bonding wire 6 gets caught in the wire 1. Therefore, the above-mentioned punching direction is set so that the burr portion 11 is located on the side where the semiconductor element 2 is not mounted.
（発明が解決しようとする３題）
ところで、上運の樹脂封止の工程においては、半導体素
子２を装着したリードフレーム５を、第９図で二点鎖線
で示すようなキャビティ１２を備える成形型内に収容し
、樹脂を注入して硬化させるものである。このとき、樹
脂注入ゲート１３（同図に二点鎖線で示す）はリードフ
レーム５の枠部５ｂの上面部分に位置し、第１２図及び
第１３図に示すように、樹脂封正により、その樹脂注入
ゲート１３に相当するランナ１４がパッケージ３につな
がった状態に成形される。そして、この後図示しないゲ
ートリムーバル装置によって、ランナｌ４は、第１４図
に示すように支点ａを中心に矢印Ａ方向に相対的に回動
され、折られるようにしてパッケージ３から切離される
ようになっている。(Three Problems to be Solved by the Invention) By the way, in the successful resin sealing process, the lead frame 5 with the semiconductor element 2 mounted thereon is molded into a cavity 12 as shown by the two-dot chain line in FIG. It is placed in a mold, and resin is injected and hardened. At this time, the resin injection gate 13 (indicated by a two-dot chain line in the figure) is located on the upper surface of the frame portion 5b of the lead frame 5, and as shown in FIGS. 12 and 13, the resin injection gate 13 is sealed with resin. A runner 14 corresponding to the resin injection gate 13 is molded to be connected to the package 3. Thereafter, by a gate removal device (not shown), the runner l4 is relatively rotated in the direction of arrow A around the fulcrum a, as shown in FIG. 14, and separated from the package 3 in a folded manner. It has become.
しかしながら、パッケージ３から切離されるランナ１４
の先端部分は、上面側は成形型により鋭角的に形成され
ているものの、下面側はリードフレーム５の枠部５ｂの
内縁部上面部分、即ちだれ部１０に相当する丸みをおび
た形状となる。このため、ゲートリムーバル装置による
切離し作業■、１に、ランナ１４の先端部分下面側では
、応力が先端に集中せずに分散してしまって先端にて適
切に切断されないことがあり、この結果、第１４図に示
すようなランナ残り１５が生ずることがある。However, the runner 14 separated from the package 3
Although the upper surface side of the tip portion is formed at an acute angle by the mold, the lower surface side has a rounded shape corresponding to the upper surface portion of the inner edge of the frame portion 5b of the lead frame 5, that is, the recessed portion 10. . For this reason, during the cutting operation using the gate removal device (1), the stress on the lower surface side of the tip of the runner 14 is not concentrated at the tip but is dispersed, and the tip may not be cut properly. In some cases, 15 runners remain as shown in FIG. 14.
このようなランナ残り１５が生ずると、この後行われる
リードフレーム５の枠部５ｂの切断工程における切断刃
の寿命低下を招いてしまう等の不具合がある。If such runner residue 15 occurs, there will be problems such as shortening the life of the cutting blade in the subsequent cutting process of the frame portion 5b of the lead frame 5.
本発明は上記事情に鑑みてなされたもので、その目的は
、ランチをパッケージから切離す工程において、ランナ
先端での適切な切断ができてパッケージにランナの一部
が残ることを極力防止できる半導体用リードフレームを
提供するにある。The present invention has been made in view of the above-mentioned circumstances, and its purpose is to prevent a part of the runner from remaining in the package as much as possible by properly cutting the lunch at the tip of the runner in the process of separating the lunch from the package. We provide lead frames for
［発明の構成コ
（課題を解決するための手段）
本発明の半導体用リードフレームは、切断線に沿う縁部
のうち、樹脂封止の工程における樹脂注入ゲートの先端
部が位置される部位に、その樹脂注入ゲート内に突出す
るかえり部を設けたところに特徴を有する。[Structure of the Invention (Means for Solving the Problems)] The semiconductor lead frame of the present invention has a structure in which the tip of the resin injection gate in the resin sealing process is located in the edge along the cutting line. , is characterized by the provision of a burr that protrudes into the resin injection gate.
（作用）
上記手段によれば、パッケージにつながるランチは、そ
の先端部にかえり部が鋭角的にくい込んだ形状に形成さ
れる。従って、ランナをパッケージから切離す工程にお
いて、ランナの先端に応力が集中するようになり、ラン
ナ先端での適切な切断がなされる。(Function) According to the above means, the launch connected to the package is formed into a shape in which the burr is recessed into the tip at an acute angle. Therefore, in the process of separating the runner from the package, stress is concentrated at the tip of the runner, and a proper cut is made at the tip of the runner.
（実施例）
以下本発明の第１実施例について、第１図乃至第５図を
参照して説明する。(Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. 1 to 5.
第３図は本実施例に係るリードフレーム２１を示してい
る。このリードフレーム２１は、後述する方法によって
、導電板から不要部を切断線に沿って切断除去して形成
され、装着部２２，？ｊｉ数本例えば１６本のリード部
２３及びそれらに連なる枠部２４を一体に備えて構成さ
れている。そのうち、装着部２２はその上面に半導体素
子２５（第１図．第２図参照）が装着されるようになっ
ており、リード部２３は半導体部品のリード脚となるも
のである。また、枠部２４はそれらを一体に保持するも
のであると共に、搬送用孔２４ａ及び位置決め用孔２４
ｂを存し後述の半導体部品の製造工程における搬送，位
置決めのための役割を果たすものである。尚、この場合
、図示上下に長い導電板に、連続的に複数個のリードフ
レーム２１が形威され、後の枠部２４を除去する工程に
おいて夫々が切離されるようになっている。FIG. 3 shows a lead frame 21 according to this embodiment. This lead frame 21 is formed by cutting and removing unnecessary parts from a conductive plate along a cutting line by a method described later. It is constructed by integrally including several lead parts 23, for example, sixteen lead parts 23 and a frame part 24 connected to the lead parts 23. A semiconductor element 25 (see FIG. 1 and FIG. 2) is mounted on the upper surface of the mounting portion 22, and the lead portion 23 serves as a lead leg for the semiconductor component. Further, the frame portion 24 holds them together, and also serves as a transport hole 24a and a positioning hole 24.
b, and plays a role in transportation and positioning in the manufacturing process of semiconductor components, which will be described later. In this case, a plurality of lead frames 21 are continuously formed on a vertically long conductive plate as shown in the figure, and are separated from each other in the subsequent process of removing the frame portion 24.
ここで、半導体部品の製造工程について第１図及び第２
図を参照して簡単に述べておく。まず、前記リードフレ
ーム２１の装着部２２に半導体素子２５を装着し、その
半導体素子２５と各リード＃２３とをボンディングワイ
ヤ２６にて接続する，次に、このものを、第３図及び第
５図に二点鎖線で示すようなキャビティ２７及びこれに
樹脂を注入するための樹脂注入ゲート２８とを有する成
形型内に収納し、例えばエボキシ樹脂による樹脂封止を
行ってパッケージ２９を形成する。成形型から取出した
後、ゲートリムーバル装置によりランナ３０をパッケー
ジ２９から切離し、しかる後、リード部２３同士間の連
結部分及び枠部２４の切除を行うと共に、リード部２３
を所定形状に折曲げて半導体部品ができあがる。Here, the manufacturing process of semiconductor parts is shown in Figures 1 and 2.
Let me briefly explain this with reference to the figure. First, the semiconductor element 25 is mounted on the mounting part 22 of the lead frame 21, and the semiconductor element 25 and each lead #23 are connected with the bonding wires 26. The package 29 is housed in a mold having a cavity 27 and a resin injection gate 28 for injecting resin into the cavity 27 as shown by the two-dot chain line in the figure, and is sealed with, for example, epoxy resin to form a package 29. After taking it out from the mold, the runner 30 is separated from the package 29 by a gate removal device, and then the connecting portion between the lead parts 23 and the frame part 24 are removed, and the lead part 23 is removed from the package 29.
A semiconductor component is completed by bending it into a predetermined shape.
さて、前記リードフレーム２１は、この場合プレス装置
を用いて導電板から不要部を打抜く方法により形成され
るものであるが、この打抜きと同時に、切断線に沿う縁
部のうち前記樹脂注入ゲート２８の先端部が位置される
部位２１ａ（第３図参照）に、その樹脂注入ゲート２８
内に突出するかえり部３１が形成されるようになってい
る。In this case, the lead frame 21 is formed by punching out unnecessary parts from a conductive plate using a press machine. At the same time as this punching, the resin injection gate is removed from the edge along the cutting line. The resin injection gate 28 is placed in the region 21a (see FIG. 3) where the tip of the resin injection gate 28 is located.
A burr portion 31 is formed that projects inward.
即ち、第４図に示すように、プレス装置は、下金型３２
とこれに接離する上金型３３とを備えて構成され、上金
型３３はバンチ３３ａを有し、下金型３２そのパンチ３
３ａに対応するダイス３２ａを有している。上金型３３
のバンチ３３ａは、導電板の不要部のうち、第５図に示
すような切除代３４を残した部分を打抜くように設けら
れている。そして、第４図に示すように、下金型３２に
は、その切除代３４を下方から打抜くためのバンチ３５
が設けられている。導電板は、半導体素子２５が装着さ
れる側の面を上面として、下金型３２上に配置され、上
金型３３が下降されることにより第５図に示すように切
除代３４を残した不要部が下方に向けて打抜かれ、この
後、バンチ３５の上昇により切除代３４が上方に向けて
打抜かれる。これにより、導電板から不要部全体が切断
除去されたリードフレーム２１が形成される。このとき
、第１図及び第２図に示すように、バンチ３３ａ及びバ
ンチ３５の打抜き方向に基づいて、リードフレーム２１
の切断線に沿う縁部のうち、樹脂注入ゲート２８の先端
部が位置される部位２１ａには、上面側にかえり部３１
が形成される。そして、その他の部位ではその反対に下
面側にかえり，上面側にだれが形威される。That is, as shown in FIG.
The upper mold 33 has a bunch 33a, and the lower mold 32 has a punch 3.
It has a die 32a corresponding to 3a. Upper mold 33
The bunch 33a is provided so as to punch out an unnecessary portion of the conductive plate, leaving a cutting margin 34 as shown in FIG. As shown in FIG. 4, the lower mold 32 has a bunch 35 for punching out the cutting margin 34 from below.
is provided. The conductive plate was placed on the lower mold 32 with the side on which the semiconductor element 25 is attached as the upper surface, and the upper mold 33 was lowered to leave a cutting margin 34 as shown in FIG. The unnecessary portion is punched out downward, and then, as the bunch 35 rises, the cutting margin 34 is punched out upward. As a result, a lead frame 21 is formed in which the entire unnecessary portion is cut and removed from the conductive plate. At this time, as shown in FIGS. 1 and 2, the lead frame 21 is
Among the edges along the cutting line, a portion 21a where the tip of the resin injection gate 28 is located has a burr 31 on the top side.
is formed. In other parts, on the contrary, it turns to the bottom side, and the shape is reflected on the top side.
上記構成のリードフレーム２１では、上述の樹脂封止の
工程において、樹脂注入ゲート２８が枠部２４の上面部
分に位置し、第１図及び第２図に示すように、樹脂封正
により、かえり部３１が位置する部位にて、パッケージ
２９とランチ３０とがつながった状態に成形される。そ
して、この後、図示しないゲートリムーバル装置によっ
て、ランナ３０は、第２図に示すように支点ｂを中心に
矢印Ｂ方向に相対的に回勅され、折られるようにしてパ
ッケージ２９から切離される。このとき、ランナ３０は
、その先端部にかえり部３１が鋭角的にくい込んだ形状
に形成されているから、ランチ３０の先端に応力が集中
するようになり、先端での適切な切断がなされる。また
、半導体素子２５の装着の工程及びボンディングヮイヤ
２６の接続の工程においては、リードフレーム２１の縁
部のうちそれらの作業が行われる部位の面には、かえり
は生じていないから、半導体素子２５やボンディングワ
イヤ２６の引っ掛かりもなく、確実な作業を行うことが
できる。In the lead frame 21 having the above structure, the resin injection gate 28 is located on the upper surface of the frame portion 24 in the resin sealing process described above, and as shown in FIGS. The package 29 and the lunch 30 are molded in a connected state at a portion where the portion 31 is located. Then, by a gate removal device (not shown), the runner 30 is relatively rotated in the direction of arrow B around the fulcrum b, as shown in FIG. 2, and separated from the package 29 in a folded manner. . At this time, since the runner 30 has a burr 31 recessed into its tip at an acute angle, stress is concentrated at the tip of the launch 30, and an appropriate cut is made at the tip. . Further, in the process of mounting the semiconductor element 25 and the process of connecting the bonding wire 26, no burrs are formed on the surface of the edge of the lead frame 21 where these operations are performed. 25 and the bonding wire 26 are not caught, and the work can be carried out reliably.
コノヨウに、本実施例のリードフレーム２１によれば、
半導体素子２５の装着の工程及びボンディングワイヤ２
６の接続の工程においては、従来と同様に引っ掛かりも
なく確実な作業を行うことができ、樹脂注入ゲート２８
の先端部が位置される部位２１ａに、その樹脂庄人ゲー
ト２８内に突出するかえり１３１を形成したことによっ
て、従来のもののようなランナ残り１５が生ずる虞のあ
るものと穴なり、ランチ３０先端での適切な切断ができ
てパッケージ２９にランナ３ｏの一部が残ることを防止
できるものである。Additionally, according to the lead frame 21 of this embodiment,
Step of mounting semiconductor element 25 and bonding wire 2
In the process of connection 6, the work can be carried out reliably without getting caught as in the past, and the resin injection gate 28
By forming a burr 131 that protrudes into the resin gate 28 at the portion 21a where the tip of the launch 30 is located, the tip of the launch 30 becomes a hole where there is a risk of the runner remaining 15 occurring as in the conventional one. The runner 3o can be cut appropriately at this point, and a portion of the runner 3o can be prevented from remaining in the package 29.
第６図及び第７図は本発明の第２実施例を示すもので、
リードフレームを製作する方法が上記第１実施同と異な
っており、本実施例に係るリードフレーム４１は、２種
類の金型を用いて２度に分けて、導電板から不要部を打
抜いて形成されたものである。即ち、まず１回目の打抜
きでは、第６図に示すように、装着部４２とその周囲部
分のリード部４３が、上面側（半導体素子が装着される
側）から下方に向けて打抜かれる。そして、２回目の打
抜きにより、第７図に示すように、残りの不要部（便宜
上斜線を付して示す）が下面側から上方に向けて打抜か
れる。これにより、リードフレーム４１の縁部のうち半
導体素子の装着及びボンディングワイヤの接続の作業が
行われる部位にはかえりは生じず、その他の部位には上
面にかえりが生ずることになる。従って、樹脂注入ゲー
トの先端部が位置される部位には上面側にかえり部が形
成されており、以て、上記第１実施例と同様に、ランナ
先端での適切な切断ができてパッケージにランチの一部
が残ることを防止できるものである。尚、上記の打抜き
の順序は逆であっても良い。6 and 7 show a second embodiment of the present invention,
The method of manufacturing the lead frame is different from that of the first embodiment, and the lead frame 41 according to this embodiment is produced by punching out unnecessary parts from the conductive plate in two steps using two types of molds. It was formed. That is, in the first punching, as shown in FIG. 6, the mounting portion 42 and the lead portion 43 surrounding the mounting portion 42 are punched downward from the upper surface side (the side on which the semiconductor element is mounted). Then, in the second punching, as shown in FIG. 7, the remaining unnecessary portions (shown with diagonal lines for convenience) are punched out from the bottom side upward. As a result, burrs do not form on the edges of the lead frame 41 at the portions where semiconductor elements are mounted and bonding wires are connected, but burrs form on the top surface at other portions. Therefore, a burr is formed on the top side of the portion where the tip of the resin injection gate is located, and as in the first embodiment, it is possible to properly cut the package at the tip of the runner. This can prevent part of the lunch from remaining. Note that the above punching order may be reversed.
その他、本発明は上記各実施例に限定されるものではな
く、要旨を逸脱しない範囲内で適宜変更して実施し得る
ものである。In addition, the present invention is not limited to the above-mentioned embodiments, and can be implemented with appropriate modifications within the scope of the gist.
［発明の効果コ
以上の説明にて明らかなように、本発明の半導体用リー
ドフレームによれば、切断線に沿う縁部のうち、樹脂封
止の工程における樹脂注入ゲートの先端部が位置される
部位に、その樹脂注入ゲート内に突出するかえり部を設
けたので、ランチをパッケージから切離す工程において
、ランチ先端での適切な切断ができてパッケージにラン
チの一部が残ることを極力防止できるという優れた効果
を奏する。[Effects of the Invention] As is clear from the above description, according to the semiconductor lead frame of the present invention, the tip of the resin injection gate in the resin sealing process is located at the edge along the cutting line. We have provided a burr part that protrudes into the resin injection gate at the part where the lunch is separated from the package, so in the process of separating the lunch from the package, the tip of the lunch can be cut appropriately and it is possible to prevent part of the lunch from remaining in the package as much as possible. It has excellent effects.
第１図乃至第５図は本発明の第１実施例を示すもので、
第１図は樹脂封止工程後の要部の縦断面図、第２図はラ
ンチをパッケージから切離す工程における要部の縦断面
図、第３図はリードフレームの平面図、第４図はプレス
装置の要部の断面図、第５図は切除代を切除する前のリ
ードフレームの平面図である。また、第６図及び第７図
は、本発明の第２実施例を示すもので、第６図は１回目
の打抜き後の導電板の平面図、第７図はリードフレーム
の平面図である。そして、第８図は半導体部品の一部を
破断した斜視図であり、第９図乃至第１４図は従来例を
示すもので、第９図は第３図柑当図、第１０図は第４図
相当図、第１１図は切断された縁部の拡大縦断面図、第
１２図は樹脂封止工程後の斜視図、第１３図は第１図相
当図、第１４図は第２図相当図である。
図面中、２１．４１はリードフレーム、２２，４２は装
着部、２３ ４３はリード部、２４は枠部、２５は半導
体素子、２８は樹脂注入ゲート、２つはパッケージ、３
０はランナ、３１はかえり部を示す。1 to 5 show a first embodiment of the present invention,
Figure 1 is a vertical cross-sectional view of the main part after the resin sealing process, Figure 2 is a vertical cross-sectional view of the main part in the process of separating the launch from the package, Figure 3 is a plan view of the lead frame, and Figure 4 is a vertical cross-sectional view of the main part after the resin sealing process. FIG. 5 is a cross-sectional view of the main parts of the press device, and a plan view of the lead frame before the cutting margin is removed. 6 and 7 show a second embodiment of the present invention; FIG. 6 is a plan view of the conductive plate after the first punching, and FIG. 7 is a plan view of the lead frame. . FIG. 8 is a partially cutaway perspective view of the semiconductor component, and FIGS. 9 to 14 show conventional examples. 4, FIG. 11 is an enlarged vertical sectional view of the cut edge, FIG. 12 is a perspective view after the resin sealing process, FIG. 13 is a diagram equivalent to FIG. 1, and FIG. 14 is a diagram equivalent to FIG. This is a corresponding diagram. In the drawing, 21 and 41 are lead frames, 22 and 42 are attachment parts, 23 43 are lead parts, 24 are frame parts, 25 are semiconductor elements, 28 are resin injection gates, 2 are packages, and 3
0 indicates a runner, and 31 indicates a burr.
Claims (1)
成されリード部とそれに連なる枠部とを備えるものであ
って、一方の面に装着された半導体素子が樹脂封止され
た後前記枠部が除去されるものにおいて、前記切断線に
沿う縁部のうち、前記樹脂封止の工程における樹脂注入
ゲートの先端部が位置される部位に、その樹脂注入ゲー
ト内に突出するかえり部を備えてなることを特徴とする
半導体用リードフレーム。1. It is formed by cutting and removing unnecessary parts from a conductive plate along the cutting line, and includes a lead part and a frame part connected to the lead part, after the semiconductor element mounted on one surface is sealed with resin. In the case where the frame portion is removed, a burr portion protruding into the resin injection gate at a portion of the edge along the cutting line where the tip of the resin injection gate in the resin sealing step is located. A lead frame for semiconductors characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1193732A JP2736123B2 (en) | 1989-07-25 | 1989-07-25 | Lead frame for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1193732A JP2736123B2 (en) | 1989-07-25 | 1989-07-25 | Lead frame for semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0357254A true JPH0357254A (en) | 1991-03-12 |
| JP2736123B2 JP2736123B2 (en) | 1998-04-02 |
Family
ID=16312889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1193732A Expired - Lifetime JP2736123B2 (en) | 1989-07-25 | 1989-07-25 | Lead frame for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2736123B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61135145A (en) * | 1984-12-06 | 1986-06-23 | Fujitsu Ltd | Lead frame |
| JPH02140963A (en) * | 1988-11-22 | 1990-05-30 | Yamada Seisakusho:Kk | Lead frame and separating method for gate using the lead frame |
-
1989
- 1989-07-25 JP JP1193732A patent/JP2736123B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61135145A (en) * | 1984-12-06 | 1986-06-23 | Fujitsu Ltd | Lead frame |
| JPH02140963A (en) * | 1988-11-22 | 1990-05-30 | Yamada Seisakusho:Kk | Lead frame and separating method for gate using the lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2736123B2 (en) | 1998-04-02 |
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