JPH0356151U - - Google Patents
Info
- Publication number
- JPH0356151U JPH0356151U JP11627089U JP11627089U JPH0356151U JP H0356151 U JPH0356151 U JP H0356151U JP 11627089 U JP11627089 U JP 11627089U JP 11627089 U JP11627089 U JP 11627089U JP H0356151 U JPH0356151 U JP H0356151U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- lead
- assembled
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11627089U JPH0356151U (en:Method) | 1989-10-02 | 1989-10-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11627089U JPH0356151U (en:Method) | 1989-10-02 | 1989-10-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0356151U true JPH0356151U (en:Method) | 1991-05-30 |
Family
ID=31664552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11627089U Pending JPH0356151U (en:Method) | 1989-10-02 | 1989-10-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0356151U (en:Method) |
-
1989
- 1989-10-02 JP JP11627089U patent/JPH0356151U/ja active Pending