JPH0355986B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method of manufacturing a static induction semiconductor device in which at least one main electrode or a semiconductor region adjacent to the main electrode is divided into a plurality of parts. In a static induction semiconductor device such as a static induction thyristor (SI thyristor) or a static induction transistor (SI transistor), at least one main electrode (for example, a cathode electrode) and a A structure in which an adjacent semiconductor region (for example, a cathode region) is divided into a plurality of regions has been proposed. When using a semiconductor device, the exterior of the main electrode, which is divided into a plurality of parts, is electrically integrated by connecting them with metal members such as electrode plates and lead wires. As is well known, such a divided structure is adopted in order to increase the current capacity of the semiconductor device as a whole without sacrificing the characteristics of the semiconductor device (for example, switching characteristics such as turn-off characteristics).
In the semiconductor device described above, the switching characteristics are mainly influenced by the resistance from the gate region to the gate electrode, so the resistance cannot be increased indefinitely. Therefore, in order to increase the current of this type of semiconductor device, it is necessary not only to increase the size of each semiconductor region in the semiconductor substrate, but also to increase the size of the gate region and A structure is adopted in which semiconductor element structures having a cathode region and a gate electrode disposed close to a gate region are juxtaposed in the same semiconductor substrate. In this specification, each semiconductor element arranged in parallel in this way is referred to as a unit element. Taking the SI thyristor previously proposed by the present inventors as an example, the cathode region in the above-mentioned unit element has a rectangular planar shape with a width of about 0.1 mm and a length of about 4.5 mm. Exposed on one major surface.
On one major surface, the cathode region is surrounded by a gate region. Since each unit element has a similar planar shape, the result is a structure in which a predetermined number of cathode regions are exposed on one main surface of the semiconductor substrate and separated from each other by continuously formed gate regions. . The number of unit elements included in the semiconductor substrate varies depending on the specifications of the semiconductor device, but for example, 4000V100A.
With a rating of
120 unit elements are arranged radially. In order for this type of semiconductor device to operate perfectly, all unit elements included in the above-mentioned semiconductor substrate are required to operate completely and substantially uniformly. However, according to experimental studies by the present inventors, the manufacturing yield of this type of semiconductor device is extremely poor;
It was found that it was difficult to produce it industrially and commercialize it. The yield is particularly reduced when an epitaxial growth process is adopted in the manufacturing process of semiconductor devices, but in other cases, grooves or recesses are formed on one main surface of the semiconductor substrate in order to realize the above-mentioned isolation structure. It has become clear that this decreases when there is a process. Furthermore, it has been found that it is actually difficult to eliminate all dust adhering to wafers during the manufacture of semiconductor devices, and this is also one of the main causes of lower yields. An object of the present invention is to provide a manufacturing method for improving the manufacturing yield of a semiconductor device having a structure in which a large number of unit elements are arranged in parallel within the same semiconductor substrate. The present invention is characterized in that at least one main electrode region, the other main electrode region, and between the one main electrode region and the other main electrode region, and below the one main electrode region. a channel region of the same conductivity type as the one main electrode region and having a higher resistance than the one main electrode region, and a channel region of the opposite conductivity type to the one main electrode region formed to sandwich the channel region; a semiconductor substrate formed by integrating a plurality of electrostatic induction type semiconductor unit elements having a gate region; and at least one main electrode formed in a portion of the surface of the semiconductor substrate where the one main electrode region is exposed. , the other main electrode formed on the surface of the semiconductor substrate at a portion where the other main electrode region is exposed and connected in common, and a gate formed on the surface of the semiconductor substrate at the portion where the gate region is exposed. (a) V _GK1 ≦V _GK <V _GK2 where V _GK is the actual value of the breakdown voltage between one main electrode region and the gate electrode region in any of the above unit elements; , V _GK1 : When the rated forward main voltage is applied between the one main electrode area and the other main electrode area of the unit element, the voltage of the one main electrode area and the other main electrode area is Absolute value of the gate bias voltage applied between the gate electrode region and one main electrode region required to achieve forward blocking between the two main electrode regions, V _GK2 : Among
Trimming and insulating one main electrode of the unit element having a V _GK value that satisfies the design breakdown voltage of the p-n junction, (b) V GK that satisfies V _GK1 ≦V _GK and V _GK2 ≦ _{V GK} The purpose is to commonly connect the one main electrode region of the unit element having a value. Hereinafter, the present invention will be explained in detail by taking an SI thyristor as an example. With reference to FIG. 1, the main parts of an example of the manufacturing process of an SI thyristor will be explained with respect to a unit element, and the problems to be solved by the present invention will also be explained. In step (a), an anode 1 and a gate 3 are respectively formed on a pair of main surfaces of an n ^- type single crystal silicon wafer having a resistivity of 180 Ωcm and a thickness of 600 μm by a diffusion method. First, to form anode 1, only on the anode side,
Heat treatment is performed at 1100°C for 30 minutes with the boron nitride wafer facing each other in a nitrogen atmosphere containing a trace amount of oxygen. Next, the surface of the portion that will become the channel 5 is covered with an oxide film, and boron is deposited on the main surface opposite to the anode side by heat treatment at 950° C. for 30 minutes in the same manner as described above. The entire wafer is then placed in oxygen.
Heat treated at 1250℃ for 25 hours and then driven in. As a result, the diffusion depth of anode 1 is approximately 40 μm,
The diffusion depth of gate 3 is approximately 30 μm. If the width of the oxide film mask at the top of the channel 5 is set to 70 μm, the width of the channel 5 after diffusion will be about 10 μm. In step (b), the oxide film formed on the main surface of the mask during drive-in in step (a) is removed,
Epitaxial layer 21 for embedding gate 3
form. In order to prevent channel 5 from being closed due to autodoping during epitaxial growth, the growth temperature is set lower than that in normal epitaxial growth, for example, 1100°C. First, the temperature of the wafer is raised to 1100°C in a hydrogen gas atmosphere, and the strained layer is removed by vapor-phase etching the silicon wafer surface by about 1 μm using a small amount of hydrochloric acid gas. Subsequently, trichlorosilane gas is flowed to deposit a circuit of about 30 μm at a rate of about 1 μm/min. At this time, a trace amount of phosphine is added to dope phosphorus into the silicon at a concentration of 2×10 ¹⁵ /cm ³ . A typical epitaxial reaction is carried out in a quartz reactor, and the raw material gases used (hydrogen, nitrogen, phosphine, hydrochloric acid, trichlorosilane, etc.) are of high purity and have been passed through a filter. However, during the reaction, the silicon film attached to the reactor wall peels off and scatters, and fine dust in the gas that cannot be completely removed falls onto the silicon wafer. Further, crystal defects may exist on the surface of the silicon wafer itself on which the anode 1 is diffused. Crystal defects are likely to occur in the epitaxial layer due to these dust particles and crystal defects in the substrate. Furthermore, compared to the thickness of the epitaxial layer used in the manufacture of integrated circuit devices, the thickness of the epitaxial layer used in power semiconductor devices such as SI thyristors is approximately 30 μm.
Crystal defects that occur during growth disturb the order of the surrounding area and gradually grow larger to form protruding polycrystalline defects. The occurrence of these defects is highly accidental, and it is difficult to eliminate them completely. If a wafer with a diameter of 76 mm is used, about one defect per wafer will always occur. These defects cause pinholes during photoetching, abnormal diffusion of impurities such as phosphorus, and abnormal etching shapes in subsequent steps. After the epitaxial layer is formed, phosphorus is selectively diffused into the surface including the upper part of the channel 5 to form a highly concentrated cathode 4. At this time, if there are crystal defects in the epitaxial layer during the diffusion of phosphorus, abnormal diffusion of phosphorus occurs, causing a breakdown voltage failure of the gate-cathode junction. In step (c), first, the area around the cathode 4 is etched using photolithography to expose the buried gate 3. In the etching solution,
Hydrofluoric acid: nitric acid, acetic acid = 3:5:3 solution
Use at 10℃. Etching takes about 2 minutes to reach a depth of about 30 μm, allowing the gate 3 to be exposed. This etching exposes the gate-cathode (epitaxial layer 21) junction end face, but since the vicinity of the junction end face has a positive bevel shape, the breakdown voltage of the gate-cathode junction exhibits a nearly ideal breakdown voltage. In this example, the design withstand voltage is approximately 200V. However, in a device in which tens to hundreds of unit elements are integrated, it is difficult to accurately etch the same number of grooves. Furthermore, if a crystal defect exists in the epitaxial layer, the etching rate at that portion increases, resulting in abnormal etching, and the groove becomes non-uniform at that portion. Furthermore, pinholes present in a mask during etching using photolithography also cause abnormal etching. Due to the above-mentioned causes, the shape of the gate-cathode junction end face deviates from the ideal positive bevel shape, which may result in a drop in breakdown voltage or, in extreme cases, a breakdown voltage failure. After exposing the gate 3 by etching, the exposed portion of the gate/cathode junction is again passivated by thermal oxidation to form an anode electrode 12, a gate electrode 13, and a cathode electrode 14. In the case of a power device, a tungsten or molybdenum plate is often bonded to the anode electrode 12 using aluminum solder. Further, the gate electrode 13 and the cathode electrode 14 are formed of an aluminum vapor-deposited film having a thickness of about 10 μm. By arranging the electrode directly on the gate 3, the potential drop caused by the gate current can be reduced, which is advantageous in cutting off a large current at high speed. An electrode plate made of tungsten or the like is pressed into contact with the cathode electrode 14 to electrically connect each unit element. Further, an aluminum wire is connected to one or several places of the gate electrode 13, which is common to each unit element, and connected to an external gate terminal. As mentioned above, the main causes are (1) defects in the wafer itself as a starting material, (2) defects introduced during epitaxial growth or dust adhesion, and (3) non-uniform etching. , the unit elements in the completed SI thyristor are not homogenized. Therefore, the breakdown voltage between the gate and cathode of each unit element is not made uniform. This point will be explained in more detail with reference to FIG. In FIG. 2, two representative unit elements are shown out of a large number of unit elements. In Figure 2, 10 is the main power supply, 8
is a gate power supply, and 91 and 92 are switches, respectively. First, it is checked whether it has the expected forward blocking characteristics. For this purpose, switch 91 is closed and switch 92 is opened to apply a reverse bias voltage between the anode and gate. The dotted line indicates the range of the depletion layer generated at this time. Gate 3 is common to each unit element, and bias is applied to channels 5a and 5b.
The junction between the gate and cathode opposing parts (p-n junction)
reach even. At this time, when the gate-cathode junctions of both unit elements are normal and the junction (pn ^-junction ) of the anode-gate opposing part is also normal, the anode and cathode junctions are normal.
The withstand voltage of the gate junction is the rated withstand voltage (4000~
4500V). However, if the gate-cathode junction of a unit element has even one defect and the breakdown voltage of the gate-cathode junction becomes low, the desired anode-gate breakdown voltage cannot be obtained. For example, in FIG. 2, assume that the gate-cathode junction breakdown voltage of one unit element is lower than the normal gate-cathode junction breakdown voltage because of the junction defect 15. In this case, as the bias voltage between the anode and the gate increases, the bias at the gate-cathode junction also increases, and the channels 5a and 5b begin to close.
However, when the bias between the anode and the gate further increases and the bias voltage applied to the gate-cathode junction exceeds the junction breakdown voltage of the junction defect 15, leakage current flows along the path shown by the arrow before the channel 5b is closed by the depletion layer. flows, and the withstand voltage of the anode-gate junction becomes lower than the expected rated value. In this way, in an SI thyristor that includes a unit element with a low withstand voltage at the gate-cathode junction, the entire unit performs a switching operation, so when a reverse bias voltage is applied between the gate and cathode, leakage current occurs at the gate-cathode junction with a low withstand voltage. occurs. Therefore, the channel surrounded by this junction is not completely closed. As a result, the forward blocking ability between the anode and cathode is lost. Therefore, an SI thyristor that fails the gate-anode withstand voltage test does not have a forward blocking function and cannot be used. Next, we conducted an actual switching operation test on the SI thyristor that passed the above-mentioned gate-anode withstand voltage test. As a result, contrary to expectations, most had poor turn-off behavior. Therefore, we individually measured the breakdown voltage between the gate electrode and the cathode electrode of each unit element for devices with poor turn-off behavior, and found that the breakdown voltage between the gate electrode and cathode electrode was the designed value for devices with poor turn-off behavior. It was found that the number of unit elements below . In addition, SI consisting of 120 unit elements
In a thyristor, the unit element whose breakdown voltage between the gate electrode and cathode electrode is lower than the design value is 1.
It has also become clear that there are only 2. The results of the above tests performed on 30 SI thyristors are shown in the table below. These SI thyristors are manufactured using the process shown in Figure 1, and have a rating of 4000V.
It is 100A and has 120 unit elements in a semiconductor substrate with a diameter of 30mm.

[Table] Among the breakdown voltages between the gate and cathode of a unit element,
Assuming that the voltage required for quiet forward blocking between the anode and cathode is V _GK1 and the voltage required for switching operation is V _GK2 (approximately equal to the design withstand voltage),
In (1)(a) of the table above, the following formula () holds for the actual gate-cathode breakdown voltage V _GK of all unit elements. V _GK2 ≦V _GK () Also, in (1)(b), there is at least one unit element having V _GK that satisfies the following equation (). For this reason, it passed the anode-to-gate withstand voltage test but failed the switching test. V _GK1 ≦V _GK <V _GK2 ... () In (2) (a) and (b) of the above table, the following formula () holds for at least one unit element. V _GK1 ＞V _GK ... () According to the table above, cases (1) and (b) account for 2/3 of the total,
It can be seen that the main reason for the poor manufacturing yield of SI thyristors. According to the present invention, all SI thyristors that fall under (1) and (b) above can be operated to meet (1) and (a) with a relatively simple operation.
Therefore, the manufacturing yield of SI thyristors can be dramatically improved. Note that (2), (3), and (b) in the above table can also be changed to (1) and (a) by applying special processing as described below. Examples of the present invention will be described below. FIG. 3 shows a cross section of a main part of an SI thyristor according to an embodiment of the present invention. Two unit elements are shown in the figure, and the unit element on the right side of the figure corresponds to (1) and (b) in the table above. This SI thyristor was manufactured using the process shown in Figure 1, and its ratings are 4000V and 100A. In FIG. 3, 11 is a load, and 17 is an electrode plate common to the cathode electrodes of each unit element. In this embodiment, only the cathode electrodes of the unit elements corresponding to (1) and (b) are trimmed so that they are not electrically connected to the electrode plate 17. Although any method can be used to trim the cathode electrode, a method of scraping off the cathode electrode with a cutting tool is preferred because it is simple and reliable. In this case, the width of the blade of the knife is somewhat larger than the width of the cathode electrode, and the blade edge is applied to the upper surface of a hard and smooth film 18 such as a SiO ₂ film provided on the surface of the semiconductor substrate adjacent to the cathode electrode. Then, by moving the cutting edge under a constant load in the longitudinal direction of the cathode electrode, the portion of the anode electrode that protrudes from the upper surface of the SiO ₂ film 18 described above is scraped off. In this way, the cutting edge does not directly contact the semiconductor substrate, so the cutting edge does not damage the semiconductor substrate. Thereafter, in order to complete the insulation, an insulator 16 such as polyimide resin or silicone resin is applied to the area including the scraped cathode electrode surface. By the above processing, the unit elements corresponding to (1) and (b) in the above table can be rendered electrically inactive. Other embodiments of the present invention are shown in FIGS. 4 to 6. In these figures, only unit elements corresponding to (1) and (b) in the above table are shown in cross section. In FIG. 4, at least a portion of the cathode electrode corresponding to the channel 5 is removed, and an impurity that determines the conductivity type of the gate 3 is ion-implanted into the cathode electrode, and the channel 5 is formed by driving in by laser light irradiation. It is sealed in the mold area. Although this embodiment has more complicated processing than the embodiment shown in FIG. 3, channel 5 is eliminated, so that among the unit elements that fall under (2) in the table above, the cause of failure is between the gate and cathode. This is also an effective method for things that exist in FIG. 5 shows that in the method shown in FIG. 4, prior to ion implantation, a recess 51 is provided in a portion corresponding to the channel 5 so as to penetrate through the cathode 4 and reach the epitaxial layer 21, and the energy required for ion implantation is reduced. This is an example of reducing the amount of implantation. This embodiment also provides the same effect as the embodiment shown in FIG. 4. In FIG. 6, not only the cathode electrode but also the cathode 4 and epitaxial layer 21 are removed by etching or the like, thereby achieving the same effect as in the embodiment shown in FIG. 4. In the embodiment shown in FIG. 6, channel blocking by ion implantation described above can also be used. In this case, this is accomplished by lightly implanting ions into the channel 5 exposed by etching. As a result, a p-type region (not shown) is formed at the upper end of the channel 5 in FIG. 6 so as to connect the gates 3 with each other. The present invention can also be applied to a type of SI thyristor in which the gate electrode and cathode electrode are located in the same plane.
An example is shown in FIG. In the SI thyristor shown in FIG. 7, the gate electrode 13 and the cathode electrode 14 are interdigitated with each other.
It has a flat pattern of In this embodiment, the cathode electrode or only the cathode of the defective unit element is removed by a method such as mechanical cutting or etching, or at least the connection part with the cathode electrode of another unit element is burned out by laser light. In particular, the defective unit element is rendered electrically inactive. Note that the ion implantation in the embodiment shown in FIG. 4 or 5 may be used in combination with the embodiment. In addition, although the method using the processing of the semiconductor substrate or the electrode film adhered thereto has been described above, when using the electrode plate 17 in the embodiment of FIG.
It is also possible to process the electrode plate 17 to achieve the same purpose. An example is shown in FIG. In FIG. 8, a recess 171 is formed in the part of the electrode plate 17 that should come into contact with the cathode electrode 14 of the defective unit element (on the right side of the figure), so that the cathode electrode and the electrode plate 17 are electrically insulated. ing. The inside of the recess 171 is filled with an insulator 161 for complete insulation. The recess 171 can be formed by, for example, a mechanical cutting method. Although the present invention has been described above with respect to an SI thyristor having a specific gate shape, the present invention is also applicable to other types of SI thyristors, SI transistors, and the like. Although an example in which a unit element has one channel has been described, the number of channels is not limited. FIG. 9 shows an example in which a unit element has three channels. Moreover, the semiconductor material, electrode material, and insulator material are not limited to those of the above-mentioned embodiments, and any materials that can be used in the semiconductor industry are applicable. Furthermore, it goes without saying that in the above-described embodiments, the conductivity type of each semiconductor region may be reversed between p and n. As described above, the present invention is effective in easily improving the manufacturing yield of electrostatic induction type semiconductor devices in which a large number of unit elements are integrated within the same semiconductor substrate.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the main parts of the manufacturing process of an example of an SI thyristor to which the present invention is applied, FIG. 2 is a sectional view of the main parts of the SI thyristor for explaining the problems and features of the present invention, 9 through 9 are sectional views of essential parts of SI thyristors according to embodiments of the present invention. 1...Anode, 2...Base, 3...Gate, 4...Cathode, 5...Channel, 12...
...Anode electrode, 13...Gate electrode, 14...
Cathode electrode, 16, 161... Insulator, 17...
...Electrode plate, 21...Epitaxial layer.

Claims (1)

[Scope of Claims] 1. At least one main electrode region, the other main electrode region, and between the one main electrode region and the other main electrode region and provided below the one main electrode region. a channel region of the same conductivity type as the one main electrode region and having a higher resistance than the one main electrode region; and a gate region of the opposite conductivity type to the one main electrode region formed to sandwich the channel region. a semiconductor substrate formed by integrating a plurality of electrostatic induction type semiconductor unit elements, and at least one main electrode formed in a portion of the surface of the semiconductor substrate where the one main electrode region is exposed; the other main electrode formed in a portion of the surface of the semiconductor substrate where the other main electrode region is exposed and connected in common; and a gate electrode formed in the portion of the surface of the semiconductor substrate where the gate region is exposed. (a) V _GK1 ≦V _GK <V _GK2 where V _GK is the actual breakdown voltage value between one main electrode region and the gate electrode region in any of the above unit elements, V _GK1 : When the rated forward main voltage is applied between the one main electrode area and the other main electrode area of the unit element, the voltage between the one main electrode area and the other main electrode area is Absolute value of the gate bias voltage applied between the gate electrode region and one main electrode region necessary for forward blocking, V _GK2 : The voltage between the one main electrode region and the gate region of the unit element. Trimming and insulating one main electrode of the unit element having a V _GK value that satisfies the design breakdown voltage of the p-n junction, (b) V GK that satisfies V _GK1 ≦V _GK and V _GK2 ≦ _{V GK} A method for manufacturing a semiconductor device, characterized in that the one main electrode region of the unit element having a value is commonly connected. 2. In claim 1, the other main electrode region is of a conductivity type opposite to that of the one main electrode region, and the unit element is configured to have an electrostatic induction thyristor structure. A method for manufacturing a semiconductor device.