JPH0355881A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the holding, rewriting, and TDDB properties of a nonvolatile semiconductor memory by providing an impurity layer of first conductivity type, which is the same as that of the substrate of the memory in the surface area facing the edge of the floating gate electrode, in an erasing area of second conductivity type. CONSTITUTION:After a deep (about 0.5-1.0mum in depth) n<+> diffusion layer 7 is formed, a thin oxide film 8, a first poly-Si layer 5, an inter-layer insulating film 11, and a second poly-Si layer 6 are formed in this order and the second and first poly-Si layers 6 and 5 are simultaneously etched. After etching, a p-type impurity layer 10 is introduced by ion implantation performed in self-aligning manner. The layer 10 finally gets into the layers 5 and 6 by 0.2-0.3mum from their edges as a result of heat treatment performed for activation. Therefore, even when a damaged layer 9 is produced by the etching, no tunnel current flows through this area and increase of trap can be prevented when leak current increases or rewriting is made. The layer 10 is connected with a p-type substrate 1 at a LOCOS edge in a direction perpendicular to the figure, and a positive hole produced by the flowing tunnel current is bypassed through the layer 10. Thus injection of positive holes into the oxide film is suppressed and the TDDB property of the thin oxide film is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory used in electronic equipment such as computers.

[Summary of the invention]

This invention eliminates the effects of damage caused when etching a floating gate electrode in the erase region of a floating gate non-volatile memory using photoelectron injection or tunnel injection, and also eliminates the effects of damage to a thin oxide film during erase operation. In order to suppress hole injection, a shallow impurity region of a conductivity type opposite to that of the erased region is provided on the surface of the erased jI region facing the floating gate electrode edge part. This improvement of the erase area makes it possible to increase the maximum number of rewrites.

[Conventional technology]

FIG. 2 shows a plan view of a conventional channel hot electron injection type nonvolatile memory. Now P the semiconductor substrate here.
The following explanation assumes that it is a type. On the substrate, there is a source 12 and a drain 13 which are diffusion regions, and a floating gate electrode 15 made of polysilicon, silicide, etc. and a control gate 6 capacitively coupled to the floating gate electrode 15 through a thin oxide film. Injection and readout sections are configured. A channel 14 is formed below the floating gate electrode 15 . The channel length is generally short, 1 μm or less. The erase portion is formed such that an n+ diffusion region 17 other than the source/drain region and the floating gate electrode 15 intersect.

Electrons are injected into the floating gate electrode 15 by applying a bias of about 5 V between the source and drain, and
When a write pulse VCG of 10 to 15 V and a duration of several msec is applied to , a channel current flows and some photoelectrons are injected into the floating gate electrode 15 .

In order to extract electrons from the floating gate electrode l5, the control gate electrode 16 is made ○■, and the erase area 17 is
An erase pulse VEIL of approximately V is applied, and erasing is performed by a tunnel current.

A cross-sectional structural diagram of Tsuchiki's erasing section is shown in FIG. 3. First, the n1 diffusion layer 17 is shaped by ion implantation or the like, and the thin oxide film 18 (50 to 150 layers) is shaped by diluted oxidation or the like. Next, the first p which becomes the floating gate electrode 15
Deposit the polysi, and then deposit the second polysi with the glabella insulating film in between. After this, by dry enoching, the first polysi and the second polyS+
are etched at once to form the floating gate electrode 15 and control gate electrode 16.

[Problem to be solved by the invention]

First, in the conventional eraser structure, there is damage l9 on the oxide film surface due to dry etching, and the floating gate electrode 1
This causes an increase in leakage current in the energy section of No. 5 and an increase in toranop during rewriting. Second, during erasing, the tunnel current generates a large number of hole-electron pairs in the n+ diffusion region, and the holes with high energy efficiency are injected into the thin oxide film.
It is to be raped. This hole injection deteriorates the TDDB characteristics of the thin oxide film.

[Means to solve the problem]

In the present invention, a deep n0 diffusion layer is provided, and p
After olysi etching, a shallow P-type impurity layer is formed in a self-aligned manner on the floating gate electrode. Since the P-type impurity layer spreads 0.2 to 0.3 mm inward from the etched-damaged polysilicon layer, the damaged layer does not reach the n0 diffusion region. Moreover, this P-type impurity layer is
It has the same potential as the substrate. [Function] Since the P-type impurity layer is self-aligned, no tunnel current flows in this region, and the influence of traps caused by etching damage is almost eliminated. Furthermore, since the P-type impurity layer acts as a bypass for high-energy holes generated by tunnel current, hole injection into the thin oxide film can be detected.

〔Example〕

FIG. 1 is a cross-sectional structural diagram of the basic erasing section of the present invention.

First of all, it is deep (0.5~i.o enthronement is fine)
Leaving the n+ diffusion layer 7 intact, a thin oxide film 8 and the first p
olysi 5, interlayer insulation If! i 1, 'l p
polysi 6 is formed in this order, and the second polysi 6 and the first polysi 5 are etched simultaneously. Thereafter, a P-type impurity layer 10 is introduced by an injector in a self-aligned manner. The P-type impurity layer 10 is finally heated to about 0.2 to 0.31 polysi 5 and 6 by heat treatment for activation.
Go deeper inside. Therefore, even if there is an etching damage layer 9, no tunnel current flows through this region. Since the P-type impurity layer 1O is connected to the P-type substrate 1 at the acos edge in the direction perpendicular to the figure, the genuine tag generated by the flow of tunnel current is bypassed through this P-type impurity layer 10.

Figure 4 shows the n-type region and the p-type region as diffusion S.
It was realized using elfAlign (DSA) technology.

FIG. 5 is a cross-sectional structural diagram when an erasing area is determined by an etching window of a thin oxide film. In this case as well, there is stress due to the damaged layer or level difference due to ethoching. In this case, the P-type impurity 71510 introduced into the surface works in the same manner as in FIGS. 1 and 4.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate the influence of the damaged layer generated in the thin oxide film in the erased area, thereby reducing leakage and toranop, and further bypassing holes generated by tunnel current. I can do it.

This improves retention characteristics and rewrite characteristics. TDDB characteristics can be improved.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional structural diagram of an erasing section of a nonvolatile memory, Fig. 2 is a plan view of a conventional nonvolatile memory, Fig. 3 is a sectional structural diagram of another conventional erasing section, and Fig. 4 is a cross-sectional structural diagram of an erasing section of a nonvolatile memory. Figure 5 is a cross-sectional structural diagram of the erased part determined by the etched window. 1 ・ ・ ・ P type substrate 5...first polysi 6...second polysi 7...n diffusion layer 8...thin oxide film 9...damage layer 10...P type Non'4@material layer 11...Interlayer insulating film 2...Source region 13...Drain region, channel region, floating gate electrode, control gate electrode, erase diffusion region, thin erase oxide film, damaged layer... P type board

Claims (1)

[Claims] source and drain regions of a second conductivity type provided at intervals on the surface of a semiconductor substrate of a first conductivity type; a channel region on the surface of the semiconductor substrate between the source region and the drain region; a floating gate electrode provided through an oxide film on the semiconductor substrate, a control gate electrode capacitively coupled to the floating gate electrode to control the potential, and the source and drain regions provided on the semiconductor substrate at intervals. an erase region of a second conductivity type, and an impurity layer of a first conductivity type is provided in a surface region facing an edge of the floating gate electrode within the erase region.