JPH0355860A - Fixing method of semiconductor integrated circuit having protruding electrodes to circuit board - Google Patents
Fixing method of semiconductor integrated circuit having protruding electrodes to circuit boardInfo
- Publication number
- JPH0355860A JPH0355860A JP1191866A JP19186689A JPH0355860A JP H0355860 A JPH0355860 A JP H0355860A JP 1191866 A JP1191866 A JP 1191866A JP 19186689 A JP19186689 A JP 19186689A JP H0355860 A JPH0355860 A JP H0355860A
- Authority
- JP
- Japan
- Prior art keywords
- protruding electrodes
- semiconductor integrated
- integrated circuit
- circuit board
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000000853 adhesive Substances 0.000 claims abstract description 39
- 230000001070 adhesive effect Effects 0.000 claims description 32
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000812 Ra alloy Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- HCWPIIXVSYCSAN-UHFFFAOYSA-N radium atom Chemical compound [Ra] HCWPIIXVSYCSAN-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Multi-Conductor Connections (AREA)
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、セラミック基板、ガラス基板またはプリント
基板などの回路基板に、突起電極を有する半導体集積回
路を接着剤を用いて接続する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of connecting a semiconductor integrated circuit having protruding electrodes to a circuit board such as a ceramic substrate, a glass substrate, or a printed circuit board using an adhesive.
従来の技術
従来、セラミック基板、ガラス基板またはプリント基板
などの回路基板と突起電極を有する半導体集積回路とを
接着剤を用いて接続する実装方式は実用化されていなか
った.
しかし、接着剤の硬化温度の低下、接着強度の向上等に
伴い、この実装方式が最近実用化され始めた.第3図は
従来例の実装方式に用いられる接着剤供給治具の要部断
面図であり、特開昭63一201628号公報に示され
る.この実装方式では、第3図に示すように、一定の溝
深さlを持つ接着剤供給油具1に接着剤2を充填し、そ
の接着剤層上に半導体集積回路3を押圧し、各突起電極
4上に均等に接着剤を形成する.
次に、この半導体集積回路3を回路基板の配線パターン
に位置合わせして接続する。Conventional technology Up until now, a mounting method in which a circuit board such as a ceramic substrate, a glass substrate, or a printed circuit board and a semiconductor integrated circuit having protruding electrodes are connected using an adhesive has not been put to practical use. However, this mounting method has recently begun to be put into practical use as the curing temperature of adhesives has decreased and adhesive strength has improved. FIG. 3 is a sectional view of a main part of an adhesive supply jig used in a conventional mounting method, and is shown in Japanese Patent Application Laid-Open No. 63-201628. In this mounting method, as shown in FIG. 3, an adhesive supplying oil tool 1 having a certain groove depth l is filled with an adhesive 2, a semiconductor integrated circuit 3 is pressed onto the adhesive layer, and each Apply adhesive evenly on the protruding electrode 4. Next, this semiconductor integrated circuit 3 is aligned and connected to the wiring pattern of the circuit board.
発明が解決すべき課題
このような先行技術では、接続後回路基板と半導体集積
回路との熱膨張係数の差が原因となり、半導体S積回路
の中心からの距離が長く、大きな応力が作用する四隅に
配置された突起電極を中心に、外側の突起電極における
接続状態が不安定となる.
本発明の目的は、突起電極を有する半導体集積回路の回
路基板への安定した接続方法を提供することである。Problems to be Solved by the Invention In such prior art, the difference in thermal expansion coefficient between the circuit board and the semiconductor integrated circuit after connection causes the four corners of the semiconductor integrated circuit to be located at a long distance from the center and subject to large stress. The connection state of the protruding electrodes placed at the center and the outer protruding electrodes becomes unstable. An object of the present invention is to provide a method for stably connecting a semiconductor integrated circuit having protruding electrodes to a circuit board.
課題を解決するための手段
本発明は、突起電極を有する半導体集積回路の前記突起
電極のうち、周辺部に配置されている突起電極に残余の
突起電極に比べて多くの量の接着剤を付着し、
接着剤が付着された突起電極をその突起電極が接続され
るべき回路基板に接着することを特徴とする突起電極を
有する半導体集積回路の回路基板への取付方法である。Means for Solving the Problems The present invention provides a method for attaching a larger amount of adhesive to the protruding electrodes arranged in the peripheral part of the protruding electrodes of a semiconductor integrated circuit having protruding electrodes than to the remaining protruding electrodes. A method for attaching a semiconductor integrated circuit having a protruding electrode to a circuit board is characterized in that the protruding electrode to which an adhesive is attached is adhered to a circuit board to which the protruding electrode is to be connected.
作 用
本発明に従えば、周辺部に配置されている突起電極に残
余の突起電極に比べて多くの接着剤が付着され、この接
着剤を硬化させて突起電極と回路基板とが接続される。According to the present invention, a larger amount of adhesive is attached to the protruding electrodes disposed at the periphery than to the remaining protruding electrodes, and this adhesive is cured to connect the protruding electrodes and the circuit board. .
このように、周辺部の突起電極の接着剤の量を増やし、
回路基板との密着強度を向上させることで、回路基板と
半導体集積回路の熱膨張率の差によって生ずる応力が大
きい周辺部の突起電極においても安定な接続を得ること
ができる.実施例
本発明の一実施例を第1図および第2図を用いて説明す
る。In this way, increase the amount of adhesive on the protruding electrodes at the periphery,
By improving the adhesion strength to the circuit board, stable connections can be obtained even with protruding electrodes in the peripheral area, where stress is large due to the difference in thermal expansion coefficient between the circuit board and the semiconductor integrated circuit. Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2.
第1図は本発明に用いる接着剤供給治具の要部断面図で
あり、第2図は半導体集積回路と回路基板接続後の断面
図である.第1図に示したように、本発明に用いる接着
剤供給治具は、l1および12の2段階の深さの溝を有
する。この溝深さl1l2は、突起電極4の高さhに応
じて適切に選択する.通常l1は、0,6h程度、l2
は0.5h程度とすることが望ましい。ただし、溝の深
さは第1図に示したように、2段階に限定する必要はな
く、さらに多段階にしてもよいし、場合によっては連続
的にその深さを変えてもよい。FIG. 1 is a sectional view of a main part of the adhesive supply jig used in the present invention, and FIG. 2 is a sectional view after connecting a semiconductor integrated circuit and a circuit board. As shown in FIG. 1, the adhesive supply jig used in the present invention has grooves with two depths, 11 and 12. This groove depth l1l2 is appropriately selected depending on the height h of the protruding electrode 4. Normally l1 is about 0.6h, l2
It is desirable that the time is about 0.5 hours. However, the depth of the groove need not be limited to two stages as shown in FIG. 1, but may be made into more stages, or the depth may be changed continuously depending on the case.
この溝に接着剤2を充填した後、スキージなどで表面を
平滑化する。接着剤としては、粘度200ボイズのエボ
キシ系接着剤などを用いる。この接着剤に、粒径0.1
〜10μm程度の銀とノくラジウムの合金などを含ませ
て導電性接着剤として用いる。After filling this groove with adhesive 2, the surface is smoothed with a squeegee or the like. As the adhesive, an epoxy adhesive with a viscosity of 200 voids is used. This adhesive has a particle size of 0.1
It is used as a conductive adhesive by including an alloy of silver and radium of about 10 μm.
次に、半導体集積回路3の突起電極を、この接着剤供給
治具1上に位置合わせした後、浸漬、押圧し、引き上げ
る.溝深さに応じて、接着剤の粘度のために外側の突起
電極には、内側の突起電極に比べ多くの量の接着剤が付
着する。その後、第2図に示すように、この半導体集積
回路3を回路基板5の配線パターン6に位置合わせし,
接続する。Next, the protruding electrodes of the semiconductor integrated circuit 3 are aligned on the adhesive supply jig 1, and then immersed, pressed, and pulled up. Depending on the groove depth, a larger amount of adhesive adheres to the outer protruding electrodes than to the inner protruding electrodes due to the viscosity of the adhesive. Thereafter, as shown in FIG. 2, this semiconductor integrated circuit 3 is aligned with the wiring pattern 6 of the circuit board 5,
Connecting.
突起電極が、たとえば半導体集積回路の一部に偏って形
成されている場合には、これらの突起電極のうちより周
辺部に配置されている突起電極に接着剤が多く付着する
ようにして、回路基板と接続する.
発明の効果
以上のように本発明によれば、半導体集積回路の周辺部
の突起電極への接着剤形成量を選択的に内側の突起電極
への接着剤形成量よりも多くすることができる.このよ
うに、周辺部の突起電極において、接着剤の量を多くし
て回路基板との密着強度を向上させることで、各種回路
基板と半導体装置との熱膨張率の差によって生ずる応力
が大きい周辺部の突起電極においても安定した接続を得
ることができる.For example, if the protruding electrodes are formed unevenly in a part of a semiconductor integrated circuit, the adhesive should adhere more to the protruding electrodes located on the periphery of the protruding electrodes, so that the circuit Connect to the board. Effects of the Invention As described above, according to the present invention, the amount of adhesive formed on the protruding electrodes on the periphery of a semiconductor integrated circuit can be selectively made larger than the amount of adhesive formed on the protruding electrodes on the inside. In this way, by increasing the amount of adhesive in the protruding electrodes at the periphery to improve the adhesion strength with the circuit board, it is possible to improve the adhesion strength between the protruding electrodes and the circuit board. A stable connection can be obtained even with the protruding electrode at the bottom.
第1図は本発明の一実施例に用いる接着剤供給治其の要
部断面図、第2図は半導体集積回路と回路基板との接続
後の断面図、第3図は従来例に用いる接着剤供給治具の
要部断面図である。
1・・・接着剤供給油具、2・・・接着剤、3・・・半
導体集積回路、4・・・突起電極、5・・回路基板、6
・・・配線パターンFig. 1 is a cross-sectional view of the main parts of the adhesive supplying device used in one embodiment of the present invention, Fig. 2 is a cross-sectional view after connecting the semiconductor integrated circuit and the circuit board, and Fig. 3 is the adhesive used in the conventional example. FIG. 3 is a cross-sectional view of main parts of the agent supply jig. DESCRIPTION OF SYMBOLS 1...Adhesive supply oil tool, 2...Adhesive, 3...Semiconductor integrated circuit, 4...Protruding electrode, 5...Circuit board, 6
...Wiring pattern
Claims (1)
、周辺部に配置されている突起電極に残余の突起電極に
比べて多くの量の接着剤を付着し、接着剤が付着された
突起電極をその突起電極が接続されるべき回路基板に接
着することを特徴とする突起電極を有する半導体集積回
路の回路基板への取付方法。Among the protruding electrodes of a semiconductor integrated circuit having protruding electrodes, a larger amount of adhesive is attached to the protruding electrodes arranged in the peripheral area than to the remaining protruding electrodes, and the protruding electrodes to which the adhesive is attached are A method for attaching a semiconductor integrated circuit having a protruding electrode to a circuit board, the method comprising adhering the protruding electrode to a circuit board to which it is to be connected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1191866A JPH0355860A (en) | 1989-07-25 | 1989-07-25 | Fixing method of semiconductor integrated circuit having protruding electrodes to circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1191866A JPH0355860A (en) | 1989-07-25 | 1989-07-25 | Fixing method of semiconductor integrated circuit having protruding electrodes to circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0355860A true JPH0355860A (en) | 1991-03-11 |
Family
ID=16281793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1191866A Pending JPH0355860A (en) | 1989-07-25 | 1989-07-25 | Fixing method of semiconductor integrated circuit having protruding electrodes to circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0355860A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6780682B2 (en) | 2001-02-27 | 2004-08-24 | Chippac, Inc. | Process for precise encapsulation of flip chip interconnects |
-
1989
- 1989-07-25 JP JP1191866A patent/JPH0355860A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6780682B2 (en) | 2001-02-27 | 2004-08-24 | Chippac, Inc. | Process for precise encapsulation of flip chip interconnects |
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