JPH035583B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field] The present invention relates to an electrostatic recording device, and particularly to an electrostatic recording device that performs electrostatic recording by converting a charged latent image formed on a photoreceptor through a charging process and an exposure process into a visible image through a developing process. [Prior Art] Conventionally, in such an electrostatic recording device, fogging occurs in the image obtained depending on the condition of the photoreceptor or photosensitive drum, or the density of the image decreases, making it impossible to obtain an image with an appropriate density. There's a problem. This will be explained using FIGS. 1 and 2. FIG. 1 is a characteristic diagram showing the relationship between the surface potential of a photosensitive drum and the amount of exposure. In the figure, A shows the characteristics at normal temperature and normal humidity, B shows the characteristics at high humidity, and C shows the characteristics during durability. The image quality adjusted with characteristic A is likely to be foggy with characteristic B, and the density is low and skipping is likely to occur with characteristic C. In order for the user to adjust this, he or she must rely on an exposure dial or an image quality changeover switch linked to the development bias. Generally, this readjustment requires adjustment of the amount of charge, which is impossible for the user.
FIG. 2 is a characteristic diagram showing the relationship between potential and exposure amount when dark and bright potentials are measured and the charging voltage is controlled using the measured output. In the figure, characteristics A, B, and C are the same as in FIG. Although the potential control shown in FIG. 2 is a means taken to eliminate the drawbacks shown in FIG. 1, there is still a difference between characteristic A and characteristics B and C. Therefore,
As a means of preventing fog caused by this difference in characteristics, a method has been adopted in which the white background potential is further measured and the developing bias is controlled. However, when this developing bias control method is adopted, a phenomenon occurs in which the image becomes thinner. The reason for this is that in characteristic A in Figure 2, when the standard plate placed outside the image area is irradiated with the standard exposure amount E _s , the potential formed on the photoreceptor is a, and the developing bias is set based on this potential a. Assuming that the voltage is applied to the developing electrode and the settings are set to obtain appropriate image quality, when the state changes to characteristic B, the standard exposure amount
The potential at E _s rises to b. Since the developing bias is applied based on the potential b, the dark area surface potential (second
The difference between E _D in the figure and the developing bias potential is reduced,
There is no fog, but the density is low. Conversely, in the state of characteristic C, the potential drops to c, and the developing bias is applied based on this potential c, so the difference between the dark area surface potential and the developing bias potential is wider than in the case of characteristic A, resulting in a higher density. Image quality. In order to compensate for this density difference, the value of the standard exposure amount E _s is changed depending on the state of the photoreceptor, for example, to E′ _s in the state of characteristic B, and to E″ _s in the state of characteristic C. Although it is necessary to stabilize the potential during exposure, it is troublesome to do this manually. [Objective] The present invention has been made in view of the above points, and its purpose is to stabilize the photoreceptor. It is an object of the present invention to provide an electrostatic recording device capable of obtaining images of appropriate density with a simple configuration regardless of characteristic fluctuations.That is, the present invention provides a charging means for uniformly charging a recording medium, and a charging means for uniformly charging a recording medium. an exposing means for forming an electrostatic latent image on the recording medium by exposing the recording medium charged by the recording medium; a developing means for developing the electrostatic latent image formed on the recording medium; a reference having a reference white color; a white member, a detection means for detecting the surface potential of the recording medium, and a control means for determining operating conditions of the charging means, exposure means, and development means based on the output of the detection means before image formation; The control means are
operating the charging means based on initial data;
In order to converge the dark potential of the recording medium to a target potential, charging control data for determining the operating voltage of the charging means is determined according to the dark potential detection output of the detecting means, and then, based on this charging control data, the forming a sample area on the recording medium by operating the charging means to charge the recording medium and exposing the reference white member by lighting the exposure means at a standard amount of light based on initial data;
In order to converge the bright area potential of the sample area to a fixed target potential, arithmetic processing is performed on the bright area potential detection output of the detection means according to an approximation formula indicating a preset exposure dose-surface potential correlation. obtaining exposure control data for determining the operating voltage of the exposure means, and then further operating the exposure means based on the obtained exposure control data;
The reference white member is further exposed to light to form a sample area on the recording medium, and in order to set a developing bias voltage without fogging, the bright area potential detection output of the sample area outputted from the detection means is set in advance. The present invention provides an electrostatic recording device characterized in that development control data for determining the bias voltage applied to the developing means is obtained by performing arithmetic processing according to a predetermined arithmetic expression. [Example] Next, an example of the present invention will be described in detail with reference to FIGS. 3 to 7. (Schematic Description of Image Forming Apparatus) FIG. 3 shows a schematic configuration of an electrostatic recording apparatus according to the present invention. The photoreceptor or photosensitive drum 1 is composed of three layers, for example, an insulating layer, a photoconductive layer, and a conductive layer from the surface, and a shaft 1 is attached to the main body (not shown).
It is supported so as to be rotatable in the direction of the arrow around a. Around this photosensitive drum 1, there is a
Secondary charger 2, secondary charger 3, full exposure lamp 4,
A potential sensor 7, a developing roller 5 of a developing device, a transfer charger 28, and a pre-discharge charger 29 are arranged. The entire surface of the photosensitive drum 1 is uniformly charged by the primary charger 2, and the entire surface of the photosensitive drum 1 is pre-neutralized by the charger 29 prior to each process.The original 10 illuminated by the original exposure lamp 11 is then placed on the mirrors 12, 13. After that, the photosensitive drum 1 is exposed to light. At this time, the charge is removed by the secondary charger 3 according to the image of the document, and a latent image is formed. Subsequently, the entire surface is exposed by a full-surface exposure lamp 4, and then toner is developed by a developing roller 5. A bias voltage is applied to the developing roller 5, as will be described later, to improve the gradation of the image. Subsequently, the transfer charger 28 is activated to perform transfer onto recording paper (not shown). (Charging control) Prior to recording an image, by turning on and off the blank exposure lamp 6, a dark area potential (hereinafter referred to as V _D ) and a light area potential (hereinafter referred to as V _SL ) are set on the photosensitive drum 1.
form. Each potential is detected by a surface potential sensor 7 disposed with respect to the photosensitive drum 1 between the entire surface exposure lamp 4 and the developing roller (developing electrode) 5, and is measured as an analog quantity by a potential measuring circuit 8. The surface potential thus measured is converted into a digital quantity by the A/D conversion circuit 9 and processed within the microcomputer (hereinafter referred to as MPC) 15. M.P.C.
15 applies control data so that the bright area potential and the dark area potential approach their respective target values. This data is converted into an analog quantity by the D/A conversion circuit 16 and inputted to the primary and secondary voltage control circuits 18 and 19. The primary high voltage transformer 21 is controlled by the primary high voltage control circuit 18, thereby controlling the primary charger 2.
The amount of charge of the secondary high voltage control circuit 19 is controlled.
The secondary high-voltage transformer 22 is controlled by the secondary charger to control the amount of charge of the secondary charger, and each of V _SL and V _D is adjusted so as to approach the target value. (Exposure Control) Next, a standard white plate (not shown) provided outside the image area of the original 10 is irradiated, and the exposure amount of the original exposure lamp 11 is adjusted. For the first irradiation, predetermined data outputted by the MPC 15 is converted into an analog quantity by the D/A conversion circuit 16, and the light quantity control circuit 1
This is done by applying a lighting voltage regulated by the lamp regulator 14 to the exposure lamp 11 via the lamp regulator 7 . The reflected light from the standard white plate due to this first exposure amount is guided onto the photosensitive drum 1 via mirrors 12 and 13, and the potential (V _L1 ) corresponding to the white background formed on the surface is detected by the potential sensor 7. The measurement is performed via the measurement circuit 8. This measured potential is A/
After being converted into digital data by the D conversion circuit 9, it is led to the MPC 15, where calculations are performed using an approximation formula indicating the correlation between the exposure amount and the surface potential set in advance. The calculation result is converted into an analog quantity by the D/A conversion circuit 16, and the lamp regulator 14 is driven via the light quantity control circuit 17 to adjust the exposure quantity of the exposure lamp 11 so that the white ground potential becomes a target value. This measurement of V _L1 and adjustment of the exposure amount based on the measurement output are repeated three times, the determined exposure amount is irradiated onto the photosensitive drum, and the surface potential of the irradiated portion is V _L2
is measured by the potential sensor 7. (Development bias voltage control) This measured potential V _L2 is input to the MPC 15 via the A/D conversion circuit 9. Based on this, the MPC 15 performs calculation processing such as applying +100V to the measured potential V _L2 , for example. This calculation result is converted into an analog value by the D/A conversion circuit 16, and then the DC developing bias circuit 20 is driven to control the DC developing bias circuit 20 so that an appropriate developing bias can be obtained. This developing bias control further corrects the original exposure control described above. That is, by controlling the exposure of the original, the white background potential is converged to, for example, approximately zero V, and then the developing bias is determined, so that an appropriate developing bias can be obtained. The output of this DC developing bias control circuit 20 is AC
The developing bias control circuit 23 superimposes an AC bias voltage of, for example, 1300 V peak-to-peak and 1 KHz. This alternating current bias functions to faithfully reproduce the gradation of an image. The developing bias voltage obtained from the DC developing bias control circuit 20 and the AC developing bias controlling circuit 23 is applied to the electrode of the developing roller 5, and toner development is performed by jumping development. Regarding jumping development using a developing bias, see, for example, Japanese Patent Application Laid-open No. 18656/1983. The above-mentioned control operation is performed by the MPC 15 receiving an instruction from a means for controlling the sequence of the entire apparatus, for example, in accordance with the procedure shown in FIG. 6 (described later). (Pre-electrostatic elimination, transfer control) The pre-electrostatic elimination step preceding the above process and the transfer step after development are also controlled by the MPC 15, respectively. That is, after the data processed by the MPC 15 is converted into an analog value by the D/A conversion circuit 16, the transfer high-voltage transformer 26 and the pre-static discharge high-voltage transformer 27 are controlled through the transfer control circuit 24 and the pre-static discharge control circuit 25, respectively, and are charged. The devices 28 and 29 are adjusted to control the transfer process and the static elimination process at equal magnification and variable magnification. In the present invention, image forming conditions are thus controlled according to the surface potential on the photoreceptor. (Description of Control Circuit) Next, further details of the control circuit shown in FIG. 3 will be described with reference to FIGS. 4 and 5. The MPC (microcomputer) 15 sends control signals DB0, DB1, DB2,
It receives DB3, STROB, and RESET and performs the above-mentioned arithmetic processing according to the procedure determined by the ROM built in MPC chip Q3. Further, from the sequence controller 15', a primary high voltage ON signal (HV-1), a secondary high voltage ON signal (HV-2), and an AC developing bias ON signal (BIAS) are sent to the primary high voltage control circuit 18,
It is supplied to the secondary high voltage control circuit 19 and the AC developing bias control circuit 23 to turn on and off the generation of the respective high voltage and AC developing bias. Note that each signal has its noise removed by a resistor R1 and a capacitor C1, is inverted and level-shifted by an inverter Q10 at the subsequent stage, and is input to the corresponding input of Q3. RESET initializes Q3. DB0~DB3
The combination of "H" and "L" of these signals indicates the content shown in Table 1, which is judged by the MPC and processed. In the past, the input to the potential control microcomputer 15 was not coded in this way, which had the disadvantage that the number of signal lines increased significantly as the control became more complex. In this embodiment, a maximum of 16 states can be specified as 4-bit data, so the number of signal lines can be reduced.

[Table] In Table 1, DBON means turning on the DC developing bias control circuit 20, and FDB
ON indicates that a DC bias voltage of approximately +400V is generated to prevent toner from adhering to the photosensitive drum 1 during non-development, and LSTR ON is data that specifies turning on the weak secondary voltage output during post-rotation. ,
V _D TS is the measurement timing signal indicating that the potential sensor is measuring the dark potential V _D , V _SL TS is the measurement timing signal of the light potential V _SL , and V _L1 TS is the measurement timing signal of the potential V _L1 due to standard white plate irradiation. measurement timing signal,
V _L2 indicates a timing signal for measuring the surface potential V _L2 by irradiating a standard white plate with an exposure amount determined according to a predetermined characteristic based on the potential V _L. Also, ×1 and ×0.7 are specified data for equal magnification and variable magnification. Q3 is whether the potential currently being measured is the light area potential (V _SL ), the dark area potential (V _D ), or the potential due to standard white plate irradiation (V _L1 ) according to the data in Table 1 input in A10 to A13. The surface potential A/D conversion data described below is taken in, and the results are used as the primary high voltage control value, secondary high voltage control value, light amount control value, and DC developing bias control value. It is output to the D/A converter Q1 of the D/A conversion circuit 16 via DO3. Also, pin 1 of J2
2 (CCC), pins 3-4 (HLC), pins 5-6
(DBC), regardless of the above-mentioned control value, a value that causes the reference current to flow through the primary and secondary chargers 2 and 3, and the original illumination lamp 1 is set.
It is also possible to output the reference lighting voltage value of 1 and the DC developing bias reference value to the D/A converter Q1. (A/D conversion) For example, in detail, the surface potential measured by the surface potential sensor 7 and potential measuring circuit 8 as described in JP-A-55-142363 is
(POTENTIAL) is input. Furthermore, resistance R2
The signal is inputted to the inverting input terminal of the operational amplifier Q2 via the inverter and is inverted and amplified with a gain determined by the ratio of the resistors R1 and R2. A bias of approximately +6V obtained by dividing the +12V power supply voltage by R4, VR1, and R5 is applied to the non-inverting input terminal of Q2 via a resistor R3.
The level of the measured potential can be adjusted by VR1. Further, capacitors C3, C4, and C5 are provided for noise removal. A voltage varying from about 9V to 14V appears on the Q2 output depending on the measured surface potential. This low impedance signal is input to an A/D converter section of an A/D converter circuit 9 including operational amplifiers Q4, Q5, Q6, and the like. A/ from Q3
The D start signal is output from pin 15 of Q3 and is normally at "H". Therefore, the output voltage of inverter Q7 becomes "L", and zero bias is applied between the gate and source of FET Q8, and conduction occurs between the source and drain of Q8, and the output of operational amplifier Q6 reaches the predetermined reference value (A/
D voltage at start). Here, the voltage applied to the Q4 output via R6 to the non-inverting input of Q6 is set to be a value obtained by dividing the Q6 output by R7 and R8. Q4 is for generating the reference voltage for that purpose and is 12V.
is divided by R10 and R9 and then buffered by Q4. At the non-inverting input terminal of Q5,
The Q6 output is inputted via R11, and the voltage equivalent to the measurement potential is inputted to the inverting input terminal via R12. Q5 constitutes a comparison circuit, and before the start of A/D conversion, the inverting input side is at a higher voltage than the non-inverting input side, so the Q5 output is approximately 0V. The output of Q5 is level-shifted by Z _D1 and input to inverter Q9. In this case, Q9 is turned off,
The output is "H". This signal is applied to microcomputer Q3 as an A/D termination pulse. The A/D starts when the STROB signal from the main unit's sequence controller 15' goes from "H" to "L".
This is done by When the STROB signal changes, A/
Q3 determines in what state the measured potential is for D conversion, and changes the A/D start signal (terminal EO ₀ ) from "H" to "L". Therefore, Q7 is turned off, the Q4 output reference voltage is applied to the Q8 gate via the resistor R13, and the source-drain region of Q8 is turned off. Since the Q4 output voltage is applied to the non-inverting input of Q6 via the resistor R6, when Q8 is turned off, the Q6 output and capacitor C
8. An integral loop of resistor R8 is formed, and the output of Q6 uses a predetermined reference voltage as an initial voltage, and the A/D start signal is inverted, and the current flowing through R8 linearly charges capacitor C8 until Q8 becomes conductive. Q8
When Q6 becomes conductive, the charge stored in C8 is discharged through R7, and the output of Q6 rapidly drops to the reference voltage. Q3 starts counting after a certain period of time after integration is started as described above by the A/D start signal. Counting is performed until the Q6 output rises linearly and the non-inverting input of comparator Q5 exceeds the inverting input. When this value is exceeded, the Q5 output reverses its state, inverter Q9 is turned on, and the Q9 output becomes "L".
Q3 determines this state as the end of counting, and the A/D conversion ends. At the end, Q3 inverts the A/D start pulse applied to Q7, makes Q8 conductive, and the Q6 output rapidly drops to the reference voltage as described above. Inside Q3, predetermined processing is performed according to the flowchart described later, using the counted value as A/D conversion data of each measured potential specified by DB0 to DB3. Noise is removed from DB0 to DB3 and STROB by an integrating circuit formed by R1 and C1, respectively, and the signal is input to the microcomputer Q3 via an inverter Q10. (Input/output signals of microcomputer) Q3 uses an NMOS 1 chip 4-bit microcomputer (MN1400) in this embodiment.
Signals as shown in Table 2 below are input or output to each terminal of Q3.

【table】

[Table] As mentioned above, high voltage primary, secondary,
It is possible to switch the light intensity and DC developing bias between the control value and the standard value, and when the terminal B13 is set to "L" during copy operation standby, the combination of "H" and "L" will be changed as shown in Table 3. Generate each display content and send it to terminals CO6 and CO of Q3.
7, CO8, CO9, DO0, DO1, DO2, DO3
Light emitting diode LED2-1,2- connected to
2, 2-3, 2-4, LED1-1, 1-2, 1
Can be displayed in 8 bits -3, 1-4 (DMS mode). In particular, the primary and secondary current values are LED1-1~4, respectively.
It is represented by 4 bits of LED2-1 to 4.
If all the LEDs light up, it indicates that the current value has reached the limiter value.

【table】

[Table] In addition to the above-mentioned display contents during standby, it is also possible to notify the user of the following contents using the LEDs 2-1 to 2-4 during arithmetic processing. In other words, LED2-1 lights up when the primary or secondary current control value reaches the upper limit, LED2-2 lights up when the bright/dark potential difference (contrast) is below 400V, and LED2-3 lights up when the contrast is below 500V. The lit LEDs 2-4 are used to determine whether the data sent from the sequence controller 15' via DB0-3 is normal or abnormal. This is done by focusing on the mutually complementary data V _D TS and V _SL TS in the combination of 4 bits of data sent as shown in Table 1 above, and turning on LEDs 2-4 when one of the data comes in. It is programmed to turn off. In the normal case, V _SL TS and V _D TS are repeatedly given to Q3 several times due to the overall copy sequence requirement, so the LEDs 2-4 repeatedly blink. If the data being sent becomes abnormal due to a disconnection of the data line or a defect in the inverter Q10, the normal LED blinking order will be disrupted, making it possible to determine whether it is normal or abnormal. The clock for Q3 is obtained by an oscillation circuit using a transistor Q11 and a ceramic oscillator CR1. The oscillation signal generated at the collector of Q11 is pulse-shaped by the transistor Q12, and in this example,
It is given to Q3 as a 495KHz clock. or,
In the present invention, the above-mentioned DMS
Along with the mode terminal, connect R16 to pin 4 of J3 (measurement potential signal line supplied from the measurement circuit).
with a single touch at the same time as the terminal connected via the
It is configured so that it can be connected to GND. Therefore, it is possible to adjust the level of the A/D converter described above using only a board equipped with a voltage control circuit without any auxiliary means. In other words, if all pins 1 to 4 of J4 are connected, a voltage equivalent to the surface potential Ov will be supplied to the A/D converter, while in the DMS mode of Table 3, that is, if all the terminals of J2 are open, ,
Since a display corresponding to Ov appears on LEDs 1 and 2, VR1 may be adjusted so that a predetermined bit is displayed. (D/A Conversion) Q3 and D/A converter Q1 are connected by a total of five lines: a 4-bit data line (DA0 to DA3 input) and a Q1 control line (LDI input). Q
3 is Q at the rise of the signal to the LDI terminal.
1, DA0 determines whether the data to be D/A converted is primary current control data, secondary current control data, light amount control data, or DC developing bias control data.
- Specify using the 4-bit signal given to DA3. Also, Q1 is the falling edge of the signal to the LDI terminal,
The data to DA0 to DC3 is the actual control data 4
Latch internally as a bit. For example, if this operation is repeated twice, 8 bits of data will be latched into Q1. Q1 is capacitor C19, C2
It includes 4-bit, 6-bit, and 12-bit binary counters counted by the clock oscillated by 0, C21, resistor R15, and coil L1, and detects coincidence with the data sent to DA0 to DA3 and inputs It is output to DAC1-4 as a pulse having a duty ratio proportional to the data. DAC1 is connected to the match detection output with a 12-bit counter, DAC2 is connected to the match detection output with a 6-bit counter, and DAC3 and 4 are connected to the match detection output with a 4-bit counter, so the output of each resolution is can get. Q1 also has an internal expansion port function, and DA0
~Turn the port on/off depending on the data to DA3
can. In this example, we use PO1 of Q1 to
The ON/OFF and DAC3 outputs are combined through the corresponding resistors R13, increasing the resolution from the 4-bit equivalent of the DAC3 output to the equivalent of 5-bit. By doing this, we improved the accuracy of the DC developing bias control circuit connected to the DAC3 output. In addition, by turning PO8 ON/OFF, it is possible to switch the high-voltage output current value for transfer and pre-static neutralization, which will be described later, between full-size copying and variable-magnification copying. Since DAC1-4, PO1, and PO8 are open-drain outputs, they are connected via pull-up resistors.
This is a pulse output pulled up to 12V.
DAC1~4 pulses are resistor R13 and capacitor C
It is integrated by an RC integration circuit consisting of 22 and becomes an analog voltage. The output of DAC4 is integrated by R13 and C22,
It appears at terminal P105 as a light amount control voltage. This voltage is applied to the inverting amplifier circuit Q14 of the light amount control circuit 17.
(See Figure 5) as a control voltage to the lamp regulator that varies in the range of approximately 13.6V to 16V.
3, and is led to the lamp regulator 14 shown in FIG. 3 via the 2nd pin of J1 to control the lighting voltage of the document exposure lamp 11. DAC1 output is pulse width modulation type 12-bit D/A
At the output, it is integrated by a secondary filter composed of R13, C22 and R17, C23, and is output to terminal P.
106 to the operational amplifier Q15 of the primary high voltage control circuit 18 (see Fig. 5), and R18 to R2.
1 as a primary high-voltage control voltage value of a predetermined voltage width, and is input to a primary high-voltage control circuit configured mainly around an operational amplifier Q16. In this example, the output pulse of DAC1 has a pulse width of about 3 ms per cycle, so in order to improve high-speed response and smoothing efficiency, integration is performed by R13 and C22 and integration by R17 and C23, and the integration circuit is
It is structured in stages. On the other hand, the DAC2 output is integrated by the corresponding R13 and C22 and passes through the terminal P107 to the operational amplifier Q1.
7 and is taken out as a secondary high voltage control voltage value of a predetermined voltage width through a resistor network consisting of resistors R22 to R25, and is inputted to a secondary high voltage control circuit mainly composed of an operational amplifier Q18. Also, the DAC3 output is the corresponding R13, C22
is integrated and appears at terminal P108. The PO1 output further appears at this terminal via resistor R13,
Both voltages are combined. In this example, this composite voltage is selected to be 1/50 of the white ground potential (V _L2 +100V),
It is taken out as a DC developing bias control voltage and inputted to the non-inverting input of the operational amplifier Q19 of the DC developing bias control circuit 20 via a resistor R70 (FIG. 5). 1/50 of the DC developing bias value by the resistor network of R71 to R74 is applied to the inverting input terminal of Q19 via R27. Q19 is a high gain differential amplifier. DC developing bias control voltage and R of R71
A closed loop is constructed so that the 72 connection points have the same potential, and the DC developing bias voltage follows the control voltage with high precision. The Q19 output is applied to the midpoint of the inverter transformer T1 via a current booster consisting of Q20 and Q21. The above DC developing bias value is obtained by a combination of a variable output inverter whose oscillation output changes according to the Q19 output and a fixed output inverter section formed by the transformer T2. The variable output inverter is transistor Q22, Q
23, Q22, Q2
3 alternately turns on and off, and the induced voltage on the primary side is boosted to the secondary side voltage determined by the winding ratio of T1 in accordance with the DC developing bias control voltage applied to the midpoint of T1. After being rectified, it is smoothed by C38, and the value shown in Figure 3 is output from pin 1 of J5 via R28 as the DC developing bias value.
It is applied to the AC developing bias control circuit 23 as a DC superimposed component. On the other hand, the fixed output inverter is T2's 1
A constant value of 24V is applied to the midpoint of the next side, and T2
The secondary high voltage output according to the winding ratio of D31, C41
By rectifying and smoothing a negative high voltage DC voltage, for example -
Get 600V. This voltage is divided using resistors R30 to R35 and superimposed on the output of the variable output inverter as a negative DC bias, and the DC developing bias voltage changes linearly from positive to negative in response to the control voltage. In the fixed output inverter section, in addition to the high voltage fixed output mentioned above, -5V power supply used for the potential control circuit, 24V and 40V floating power supply for the surface potential measurement circuit, -600V high voltage output, etc. are obtained with one transformer. I have to. (High Voltage Control) Next, high voltage control for the chargers 2 and 3 will be described. The above-mentioned primary high voltage control voltage is input to the inverting input of Q16 via R40. Also Q16
The non-inverting input of R4 is the primary high voltage output pulse obtained by sampling the primary high voltage current with resistor RS1.
1, R42, VR3 level-shifted voltage is R
43. These differential voltages are −
It is multiplied by R44/R40 and output from Q16. This output voltage is passed through resistor R45 to transistor Q24.
The current is amplified by the voltage, and is thereby taken out as a primary high-voltage voltage, which is input to the control input of the primary high-voltage transformer 21 via terminal 2 of J6. Terminal P10
The HV-1 signal given to J1 via J1 is “H”
In this case, LED-4 does not light up and diode D
10 is reverse biased, diode D11 is on, and transistor Q36 is on, so 1
The next high voltage transformer 21 does not operate. When the HV-1 signal becomes "L", LED-4 lights up, D10 becomes forward biased, D11 turns off, and Q36 turns off, so the output of Q16 is directly input to the base of Q24, turning on the primary high voltage transformer 21, and Next, it becomes possible to control high voltage transformers. For example, when the current to RS1 decreases due to fluctuations in the high voltage load, the voltage drop due to RS1 decreases and the voltage at the midpoint of VR3 increases. Therefore, the Q16 output increases, increasing the output of the high voltage transformer and increasing the current flowing to RS1. That is R40
Constant current high voltage control is performed according to the voltage applied to the voltage. Similar configurations include secondary charger 3 and transfer charger 2.
8. Also used for high voltage control of the pre-static eliminator 29.
Here, when the feedback loop from the primary high voltage transformer becomes open, the output of Q16 becomes the maximum value, and 1
Since the next high voltage reaches the maximum, by turning on the diode D12 when the loop is open, it is possible to turn on the transistor Q36 and prevent the high voltage output. The secondary charging high voltage control voltage is connected to Q18 via R46.
Applied to non-inverting input. A voltage obtained by sampling the secondary high voltage current with the resistor R _S2 and level-shifting the secondary high voltage sample voltage value with R47, R48, and VR4 is applied to the inverting input via R49. These differential voltages are multiplied by R50/R49 and output from Q18. This output voltage is applied to Q25 via R51.
The current is taken out as a secondary high-voltage control voltage that is amplified by
2 control input. given to J1
When the HV-2 signal is "H", LED-5 is not lit and D9 is reverse biased and inverter Q26 is turned on, so the Q18 output is not transmitted to the high voltage transformer and the high voltage transformer is turned off. When the HV-2 signal becomes "L", LED-5 lights up, D9 becomes forward biased, and Q26 turns off, so the Q18 output is directly applied to the Q25 base, turning on the secondary high voltage transformer 22 and turning on the secondary high voltage. It becomes possible to control the transformer. Regarding the transfer high voltage control, normally in the same size copy mode, Q1 PO8 is set to "H", so Q28 output becomes "L" and connects to the parallel resistance of R52 and R53 via terminal P104. R5
A voltage obtained by dividing 12V by 4 is applied to the inverting input side of Q29 via R55. On the other hand, to the non-inverted side, a voltage obtained by level-shifting the voltage obtained by sampling the transfer current by RS3 by R56 and R57 is applied via R58, and the Q29 output is set so that both are equal. That is, the transfer high voltage transformer 26 is driven through the transistor Q30 and the terminal 6 of I6 to control the transfer high voltage. When changing magnification, PO8 switches to “L”,
Q28 is turned off and R54 and R are connected to the inverting input of Q29.
A voltage obtained by dividing 12V by 53 is applied via R55. This voltage is set to increase in proportion to the rate of change in the transfer current flowing through RS3 from the time of equal magnification to the time of variable magnification, so Q29
The output is reduced, and transfer high voltage control is performed so that a predetermined transfer current at the time of zooming flows into RS3. Regarding the high voltage control for pre-static elimination, during normal copying at the same size, as mentioned above, PO8 of Q1 is set to "H", so the Q31 output becomes "L" via terminal P104, and therefore the Q32 output becomes "H". It's getting old. Therefore, a voltage obtained by dividing 18V by R61 and R61 is applied to the non-inverting input of Q33 via R62. On the other hand, the pre-static elimination current is applied to the inverting input.
A voltage obtained by level-shifting the voltage sampled by RS4 by R63 and R64 is applied via R65. The Q33 output is determined so that both of them are equal, and the transistor Q34 is energized via R66 to control the pre-discharge high voltage. During zooming, PO8 goes to "L" as described above, so Q31 output goes to "H" and Q32 turns on. Therefore, +18V with parallel resistance of R67 and R62 and R60
The divided voltage is applied to the operational amplifier Q3 via R62.
3 non-inverting input. Since this voltage is set to decrease in accordance with the rate of change in the transfer current flowing through RS4 from the time of equal magnification to the time of variable magnification, the output of Q33 decreases and eliminates static electricity before a predetermined period of time of variable magnification. Pre-neutralization high voltage control is performed so that current flows through RS4. The transfer high voltage and the pre-static elimination high voltage are turned on/off in synchronization with the primary high voltage turned on/off. In other words, when the HV-1 signal applied to pin 5 of J1 is “H”, the terminal P101
After that, D16 becomes reverse biased, D17 is turned on, and Q35 is also turned on. Therefore, D20 and D21 become forward biased, and approximately the base of Q30 and Q34, respectively.
Since it is clamped at 0.7V, the control voltage is not transmitted to the high voltage transformer side, and the transfer/pre-electrostatic high voltage is turned off. When the HV-1 signal becomes "L", D16 becomes forward biased, D17 is turned off, and Q35 is also turned off, so Q29 and Q33 outputs each Q3.
0 and Q34 are driven, and the transfer/pre-discharge high voltage is turned on. Also, for protection in case the feedback loop opens, Q35 is configured to be turned on/off from the feedback loop from the transfer high voltage transformer via D18, so if the loop becomes open, D18 will turn on. , Q35 is turned on, the high voltage output is turned off, and abnormal high pressure can be prevented from occurring. (Surface Potential Control) Next, the sequence of potential control will be explained using FIG. 6. (Initial Set Routine) In step 1 (S1) of Fig. 6A, first, after the start of 50, the RAM area is cleared by the reset signal (RESET) from the sequence controller (51), and then the primary high voltage control data (PC
CONTROL VALUE; PCV), primary high voltage standard data (PC STANDARD VALUE; PSV), 2
Next high pressure control data (SC CONTROL
VALUE; SCV), secondary high voltage standard data (SC
STANDARD VALUE; SSV), weak secondary high voltage data (SC LSTR VALUE; SLV) and primary,
Data for each of these secondary magnification changes, exposure control data (HL CONTROL VALUE; HCV),
Exposure standard data (HL STANDARD
VALUE; PCV), development bias control data (DB CONTROL VALUE; DCV), development bias standard data (DB STANDARD VALUE;
DSV), development bias maximum value data (FDB
VALUE; FDV), various data necessary for internal arithmetic processing, initial values of various flags, etc. are set in RAM (52). Next, clear each port (53) and confirm that it is connected to the port.
The LED will also turn off. The output port of the D/A converter is also set to the initial state (54). (Data Output Routine) In the following step 2 (S2), a flag is determined to determine whether or not it is a post-rotation (55), and if it is a post-rotation, the SLV is output and the process proceeds to step 3 (56). If there is no post-rotation, primary and secondary high pressures are output. At that time, it is determined whether there is charge control (CCC), and if it is, PCV,
Outputs SCV (57), if not, PSV, SSV
Output (58). (PCV and SCV are data judgment processing routines that will be described later, and are secured in a predetermined RAM area.) Each data value output routine of PCV, SCV, PSV, SSV, and SLV includes the scaling flag judgment inside. If the scaling flag is set (the flag will be manipulated according to the input data in step 8 described later), the scaling flag will be calculated and saved in step 12 described later, or the scaling flag is set initially in RAM. Data when magnified (equivalent to data when magnified x 0.7)
Output. In step 3 (S3), the presence or absence of exposure control (HLC) is determined (58'), and if it is, HCV is determined (59).
If not, output HSV (60). Further, in step 4 (S4), it is determined whether or not there is developing bias control (DBC) (61), and if there is none, DSV is output (62). If yes, if the flag is set depending on the state of the FDB flag (a flag indicating that the maximum developing bias value is output) (the state of the flag is determined by data from the controller in the data discrimination processing routine described later). output) FDV (63, 64). When the flag is not raised,
Check the DB flag (a flag indicating that a predetermined developing bias value is output) (65), and if the flag is set, DCV (66) is set, and if it is not set, Ov is set.
Output a considerable amount of data (67). In the following step 5 (S5), the variable magnification flag determined in the data judgment processing routine is checked based on the variable magnification command data from the controller (68), and if the variable magnification flag is OFF (the variable magnification flag is off), the port for transfer/static elimination control is set to the same magnification. to be in the state of time (69). If the mode is variable magnification, the port is set to the variable magnification mode (70). In step 6 (S6), it is determined whether or not the DMS mode (a mode for performing various displays) is determined (71), and if it is the DMS mode, the process proceeds to a display routine (step 17) to be described later (C). If not in DMS mode, go to step 7. In step 7 (S7), the controller
If STROB signal is off, step 2
Return to (S2) (72, A) and repeat the above steps, that is, the data output routine.
When the STROB signal turns on, the process moves to the data judgment and processing routine from step 8 (B). (Data Judgment Processing Routine) In step 8 (S8) of FIG. 6B, data (DB0 to DB3) from the sequence controller is input (73), and according to Table 1, it is first judged whether it is "variable magnification data" ( 74). For variable magnification (mode x 0.7),
After turning on the variable magnification flag and FDB flag, turn off the rotation flag and proceed to step 16 (75). If not, it is then determined whether the data is "variable magnification data" (76).
If it is equal magnification (mode x 1), the variable magnification flag and post-rotation flag are turned off (77), the FDB flag is turned on, and the process goes to step 16. Following the same-size data determination,
It is determined whether or not it is "post-rotation (LSTR) data" (78), and if it is post-rotation, the post-rotation LSTR flag is turned on and the process goes to step 16 (79). In step 9 (S9), if the data from the sequence controller is V _L2 (80), A/D conversion is started, and the measured potential V _L2 is converted into a digital value and saved (81). Next, calculate and save V _L2 +100V as developing bias control data, and proceed to step 16 (82). In step 10 (S10), if the data from the sequence controller is V _L1 TS, A/D conversion is started (83), and the measured potential of V _L1 is converted into a digital value and saved (84). Next, it is determined whether or not there is exposure control, and if there is no control, the process directly proceeds to step 16 without changing the output data. If there is control, exposure control data: HCV _o = 1/20 (V _L1o - V _L10 ) + HCV _o-1 (However, the subscript n indicates the n-th control.
Further, V _L10 calculates and saves the target convergence white ground potential equivalent data value) and goes to step 16 (86). In step 11 (S11), if the data from the sequence controller is V _SL TS (87), the STRB LED indicating the arrival of the strobe signal is lit, and the A/
Start D conversion, convert the _VSL measured potential into a digital value, and save it (88). Next, the part related to _VSL of the calculation of the primary and secondary high voltage control data PCV and SCV is processed and the process goes to step 16 (89). In step 12 (S12), if the data from the sequence controller is V _D TS (90),
Turn off the STRBLED, start A/D conversion, convert the V _D measurement potential to a digital value, and save it (91). Next, the presence or absence of charge control (CCC) is determined (92), and if there is no control, the process directly proceeds to step 16. When there is control, the contrast is calculated from the bright and dark potentials and the contrast is
If it is lower than 500V, LED2-3 is lit, and if it is lower than 400V, LED2-2 is lit. Next, PCV, SCV
And calculate and save PCV×0.7 and SCV×0.7 (93),
If PCV or SCV reaches the upper limit
Lights up LED2-1 and reports the outline of the control status in real time. Also, STRB LED at step 11 and step 12
It is determined whether the LEDs (LED2-4) are turned on and off in a predetermined sequence, making it easy to discover abnormalities in the data line. In step 13 (S13), if the data from the sequence controller is development bias ON "DBON" (94), the development bias ON flag (DB flag) is set.
is set, the FDB flag is turned off, and the process goes to step 16 (95). In step 14 (S14), the data from the sequence controller is set to
If DBOFF (96), turn off both the DB flag and FDB flag and go to step 16 (97). In step 15 (S15), the data from the sequence controller is set to the maximum developing bias value ON, that is,
If FDBON (98), the DB flag is turned off and FDB
Turn on the flag and go to step 16 (99). In step 16 (S16), the program waits until the strobe signal from the sequence controller turns off.
Once turned off, return to the output routine from step 2 (100). (DMS Routine) In step 17 (S17), processing from this step is performed in the DMS mode. First, the primary, secondary, and exposure values are standard values (PSV,
SSV, HSV) Outputs the DC developing bias OV (101). In step 18 (S18), data for display switching is input (102). Next, it is determined whether it is in DMS mode again (103),
If it is not the DMS mode, the LED display contents are returned to the contents of step 12 and the process returns to the output routine from step 2 (104). In step 19 (S19), if the potential display mode (MED) is selected (105), A/D conversion is started, the measured surface potential data is displayed, and the process returns to step 18 (106). If it is not MED, go to the next step. In step 20 (S20), if the _VD display mode is designated (107), the _VD data saved in the data judgment processing routine is displayed, and the process returns to step 18. If it is not the _VD display mode, go to the next step (108). In step 21 (S21), if the _VSL display mode is specified (109), the saved _VSL data is displayed and the process returns to step 18. If it is not the V _SL display mode, go to the next step (110). In step 22 (S22), if the V _L1 display mode is specified (111), the saved V _L1 data is displayed and the process returns to step 18. If it is not in V _L1 display mode, proceed to the next step (112). In step 23 (S23), if the V _L2 display mode is selected (113), the V _L2 data is displayed and the process returns to step 18 (115). V If not in _L2 display mode, primary, secondary,
Convert and display control data in 4-bit units and step
Return to 18 (114). To explain the overall operation of the electrostatic recording device that performs such potential control (see Fig. 7), after the power is turned on, the photosensitive drum 1 rotates at low speed, various high pressures are applied, and the fixing roller (not shown) When the photosensitive drum 1 reaches a predetermined temperature, the photosensitive drum 1 starts to rotate at high speed, and a high voltage suitable for high-speed rotation is applied to the front static eliminator 29, primary charger 1, secondary charger 3, and transfer charger 28. A rotation is performed. Further, if the optical system is not at a position for performing the same-size copy at the same time as the pre-rotation, the optical system is moved to the same-size position. Subsequently, potential control is performed by the microcomputer 15 as described above. This potential control increases the amount of high-voltage charge on the photosensitive drum 1 and the exposure lamp 1.
The amount of light 1 and the amount of bias applied to the developing roller 5 are controlled so that an optimal image is formed. When this control ends, the wait ends and copying becomes possible. Normally, after this, the photosensitive drum 1 is rotated and a secondary charger is used to remove residual charges and memory from the drum, cleaning the drum surface. After that, the drum is stopped and placed in a standby state in preparation for copying. Become. As described above, according to the present invention, after controlling the charging conditions so that the dark area potential converges to a fixed target potential, the exposure conditions are controlled so that the bright area potential obtained by the reference white member converges to the fixed target potential. Therefore, an appropriate contrast potential can always be obtained.Furthermore, since the development conditions are controlled using the reference white member used to control each part of the exposure, it is possible to set the appropriate development conditions without complicating the configuration, and images with appropriate density can be obtained. can be obtained.

[Brief explanation of drawings]

1 and 2 are tables explaining conventional surface potential control, FIG. 3 is a layout diagram of an electrostatic recording device using surface potential control according to the present invention, and FIGS. 4 and 5.
The figure shows a more detailed circuit diagram of each control circuit in Figure 3,
6A, B, and C are flowcharts explaining various controls, and FIG. 7 is an explanatory diagram explaining the entire sequence. 1...Photosensitive drum, 2...Primary charger, 3...
Secondary charger, 4...Full exposure lamp, 5...Developing roller, 6...Blank exposure lamp, 7...Surface potential sensor, 10...Original, 11...Exposure lamp, 12, 13...Mirror, 28...Transfer charger, 29...Pre-static eliminator.

Claims (1)

[Scope of Claims] 1. Charging means for uniformly charging a recording medium; Exposure means for forming an electrostatic latent image on the recording medium by exposing the recording medium charged by the charging means; and the recording medium. a developing means for developing an electrostatic latent image formed thereon; a reference white member having a reference white density; a detecting means for detecting the surface potential of the recording medium; A control means for determining operating conditions of a charging means, an exposure means, and a developing means, the control means operating the charging means based on initial data to converge the dark area potential of the recording medium to a target potential. Charging control data for determining the operating voltage of the charging means is obtained in accordance with the dark potential detection output of the detecting means, and then the charging means is operated based on this charging control data to charge the recording medium. At the same time, a sample area is formed on the recording medium by lighting the exposure means at a standard light intensity based on the initial data to expose the reference white member, and the bright area potential of the sample area is set to a fixed target potential. to determine the operating voltage of the exposure means by performing arithmetic processing on the bright area potential detection output of the detection means in accordance with an approximation formula indicating a preset exposure dose-surface potential correlation in order to converge; Next, the exposure means is further operated based on the obtained exposure control data, the reference white member is further exposed to form a sample area on the recording medium, and a fog-free development is performed. In order to set the bias voltage, the bias voltage applied to the developing means is determined by performing arithmetic processing on the bright area potential detection output of the sample area outputted from the detecting means according to a predetermined calculation formula. An electrostatic recording device characterized in that it obtains development control data for making decisions.