JPH0353646B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated semiconductor device, particularly an insulated gate field effect transistor, which is mainly composed of a MOS field effect transistor (hereinafter referred to as a MOS transistor), and has the ability to charge and discharge a large current. The present invention relates to an integrated semiconductor device for a constant voltage source.

It is desirable for circuits using MOS transistors to operate on a single power supply, regardless of whether they are digital or analog circuits, and in particular, integrated circuits that operate on a single 5V power supply are becoming widely used. 5V single power supply operation refers to a circuit that operates using 5V as the power supply voltage _VDD and 0V as the ground voltage GND.
However, recently, there have been attempts to realize high-performance integrated circuits by integrating memories and logic circuits using ternary level locks in single-power supply integrated circuits. For example, as an example of memory,
“Proceedings of the 11th International Conference on Solid State Devices held in August 1979”
the 11th Conference (1979 International) on
``Analysis of Taper Isolated Drum Transistors for Dynamic Memory'' published in pages 209-212 of ``SOLID STATE DEVICES'' (issued at the same time at the August 1979 meeting). Design (original title: “Analysis and
Design of the Taper Isolated Dynamic RAM
PK Chatterjee entitled “Threshold Transistor for VLSI dRMs”
There is a paper by Mr. CHATTERJEE and others. This paper describes a small-area memory cell driven by a three-level clock, and when integrated as a large-capacity memory, it is necessary to generate the three-level clock inside the integrated circuit. Moreover, in order to output a three-level clock from a single power supply integrated circuit, a constant voltage source other than the power supply voltage and ground voltage is required. Such a constant voltage source for generating three-level levels must have a large current supply capability. Constant voltage generation circuits using MOS transistors, which have been commonly used in the past, are mainly used to generate reference voltages for differential amplifiers, and do not have the ability to supply large currents. or,
When such a constant voltage circuit is given current capability,
Another disadvantage is that the steady state current consumption increases and the power consumption of the integrated circuit increases.

The purpose of the present invention is to eliminate the above-mentioned conventional drawbacks and to be suitable for generating a three-value level clock as described above.
An object of the present invention is to provide an integrated semiconductor device for a constant voltage source constituted by MOS transistors.

The device of the present invention includes a first conductive type device having a source connected to a first power source and a drain connected to an output terminal.
a MOS transistor, a second MOS transistor of a second conductivity type whose source is connected to a second power supply and whose drain is connected to the output terminal; a reference voltage generation circuit;
First and second differential amplifiers each having the output terminal voltage and the reference voltage as differential inputs, and a first signal amplified through at least the first differential amplifier are applied to the gate of the first MOS transistor. and a second signal amplified through at least the second differential amplifier is input to the gate of the second MOS transistor, and when the voltage at the output terminal is within a specific tolerance range from the reference voltage. is when both the first and second MOS transistors become non-conductive due to the first and second signals amplified in opposite directions and the voltage at the output terminal deviates from within the allowable range. and means for causing one of the first and second MOS transistors to conduct by the first and second signals amplified in the same direction.

In the first and second differential amplifiers used in the integrated semiconductor device of the present invention, the boundary between the differential inputs that invert the differential output is not completely 0V, but has opposite polarity and is at a range of several mV to several hundred mV. It is desirable that there be. That is, when the output terminal voltage that is input to the differential amplifier and the reference voltage are equal, the first and second differential amplifiers are amplified in opposite directions, and as a result, the first and second MOS transistors are amplified in opposite directions. A gate voltage is applied to the gates of the transistors such that the transistors are rendered non-conductive. On the other hand, if the voltage at the output terminal deviates from the reference voltage by several mV to several hundred mV, the differential output of either the first or second differential amplifier is reversed depending on the polarity of the deviation, and the differential output of either the first or second differential amplifier is reversed. As a result, one of the first and second MOS transistors becomes conductive.
Then, the voltage at the output terminal returns to a voltage substantially equal to the reference voltage. For example, in the integrated semiconductor device of the present invention, the first conductivity type MOS transistor is a p-channel MOS transistor (hereinafter p-channel MOS transistor).
MOS transistor), the second conductivity type MOS transistor is an n-channel MOS transistor (hereinafter referred to as an n-MOS transistor), the first power supply is a 5V power supply, the second power supply is a ground power supply, and the first and second conductivity type MOS transistors are The effect of the present invention becomes even clearer when the boundaries of the differential inputs for inverting the differential outputs of the second differential amplifier are -50 mV and +50 mV, respectively. This 50
mV is the specific tolerance range stated in the claims. In other words, when the output terminal voltage of the first differential amplifier reaches a voltage 50 mV lower than the reference voltage,
Differential output is inverted. Similarly, in the second differential amplifier, the differential output is inverted when the output terminal voltage reaches a voltage higher than the reference voltage by 50 mV. Therefore,
When the output terminal voltage is within ±50 mV from the reference voltage, a power supply voltage of 5V is applied to the gate of the first p-MOS transistor, and a power supply voltage of 5V is applied to the gate of the second n-MOS transistor. is applied so that 0V ground voltage is applied.
In this case, both the p and n-MOS transistors are non-conducting. However, if the output terminal voltage drops by 50mV or more from the reference voltage, the first
The differential output of the differential amplifier is inverted. As a result,
The inversion voltage is fed back to the gate of the first p-MOS transistor, and the gate voltage is
The voltage drops from 5V to a low voltage, the p-MOS transistor becomes conductive, and the output terminal voltage rises. When the output terminal voltage becomes higher than a voltage that is 50 mV lower than the reference voltage, the gate voltage of the p-MOS transistor rises to 5V again, and the supply of current to the output terminal is stopped. On the other hand, when the output terminal voltage becomes higher than the reference voltage by 50 mV or more, the differential output of the second differential amplifier is inverted, and the inverted voltage is fed back to the gate of the second n-MOS transistor, as described above. , its gate voltage increases from 0V to a high voltage, the n-MOS transistor becomes conductive, and the output terminal voltage decreases. When the output terminal voltage becomes lower than a voltage higher than the reference voltage by 50 mV, the gate voltage of the n-MOS transistor drops to 0V again, and current flow from the output terminal stops. In this way, it is possible to generate a voltage that fluctuates within the allowable voltage range of ±50 mV from the reference voltage, and by reducing the voltage difference of the inverting differential input, the fluctuation voltage of the output voltage is reduced. be able to. Moreover, the channel width to channel length ratio (W/L) of the reference voltage generation circuit and the load MOS transistors of the first and second differential amplifiers
To reduce the current consumption, increase the W/L of the output p and n-MOS transistors,
The effects of the present invention can be maximized by providing the ability to charge and discharge a large current in response to fluctuations in the output terminal voltage. When the output terminal voltage is within a certain tolerance range (in this case, within ±50 mV) from the reference voltage, the first and second MOS transistors are non-conducting, and no current is consumed in these MOS transistors, and the entire circuit Since the current consumption is determined only by the reference voltage generation circuit and the differential amplifier, the current consumption is reduced. On the other hand, if the output terminal voltage changes beyond the above-mentioned allowable range from the reference voltage, the first or second
The MOS transistor becomes conductive, charges and discharges a large current, and returns the output terminal voltage to within the above-mentioned allowable range from the reference voltage in a short time. Therefore, by using the integrated semiconductor device of the present invention, a device suitable for a constant voltage source that consumes little current when the output voltage is stable and has the ability to charge and discharge a large current when the output voltage fluctuates can be realized. It is very useful in practice because it is implemented using transistors.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an integrated semiconductor device of the present invention. In the figure, Qp1 is the first p-MOS transistor, Qn2 is the second n-MOS transistor, 1 is the reference voltage generation circuit, 2 is the first differential amplifier, and 3 is the second differential amplifier. 4 is the first voltage shift amplifier; 5 is the first voltage shift amplifier;
is the second voltage shift amplifier, N1 is the constant voltage output terminal, N2 is the gate terminal of the first p-MOS transistor, N3 is the gate terminal of the second n-MOS transistor, and R is the constant voltage C is the load capacity of the constant voltage source line, V _DD is the 5V power line,
GND indicates the grounding wire. first p-
MOS transistor Qp1 connects the source to the 5V power line
V _DD and the drain is connected to the output terminal N1, respectively, and the second n-MOS transistor Qn2
The source is connected to the 0V ground line GND, and the drain is connected to the output terminal N1. The two differential input terminals of the first differential amplifier 2 are connected to the constant voltage source line R and the output terminal of the reference voltage generation circuit 1, respectively, and the two differential input terminals of the second differential amplifier 3 are connected to the constant voltage source line R and the output terminal of the reference voltage generation circuit 1, respectively. , are connected to the constant voltage source line R and the output terminal of the reference voltage generating circuit 1, respectively. The first voltage shift amplifier 4 further amplifies the differential output of the first differential amplifier 2 so that the voltage V ₀ of the constant voltage source line R becomes the reference voltage.
When the voltage is higher than V ₁₁ which is lower than V ₁ by the allowable voltage Va, the output voltage is set to 5V, and conversely, when the voltage V ₀ is lower than the reference voltage V ₁₁ , the output voltage is set to 0V. Similarly, the second voltage shift amplifier 5
further amplifies the differential output of the second differential amplifier 3, and sets the output voltage to 0V when the voltage _V0 of the constant voltage source line R is lower than the voltage _V12 , which is higher than the reference voltage _V1 by the allowable voltage Va. , Conversely, when the voltage V ₀ is higher than the voltage V ₁₂ , it serves to make the output voltage 5V.
As an example, if the reference voltage V ₁ is 2.5V, the allowable voltage Va
When is set to 50 mV, the voltage V ₀ of the constant voltage source line R is
2.45V (V ₁₁ ) is held between 2.55V (V ₁₂ ).
In other words, when the voltage V ₀ is between 2.45V and 2.55V, the gate voltage V ₂ of the p-MOS transistor Qp1
is held at 5V, and the gate voltage _V3 of the n-MOS transistor Qn2 is held at 0V. However, when the voltage _V0 of the constant voltage source line R becomes lower than 2.45V, the differential voltage of the first differential amplifier 2 The output is inverted and the output voltage of the voltage shift amplifier 4 is reduced from 5V. When the gate voltage _V2 falls from 5V to below the threshold voltage of the p-MOS transistor Qp1, the p-MOS transistor Qp1 becomes conductive, current flows into the output terminal N1, and the voltage _V0 increases. Conversely, voltage V ₀ is 2.55V
When the voltage becomes higher, the differential output of the second differential amplifier 3 is inverted, and the output voltage of the voltage shift amplifier 5 becomes
Increases from 0V. Gate voltage _V3 from 0V to n-
The voltage rises above the threshold voltage of MOS transistor Qn2. The n-MOS transistor Qn2 becomes conductive, current flows from the output terminal N1 to the ground line, and the voltage V ₀
decreases. In this way, in this embodiment, the voltage V ₀ of the constant voltage source line R is always maintained between the voltages V ₁₁ and V ₁₂ , and the MOS transistors Qp1 and Qn
to the input voltage V ₀ for inverting the differential amplifiers 2 and 3, respectively, without simultaneous conduction of the differential amplifiers 2 and 3;
Since there is a voltage difference of V ₁₂ −V ₁₁ =100 mV, the circuit of this embodiment is a feedback circuit that is difficult to oscillate.

A more specific circuit example of the embodiment shown in FIG. 1 is shown in FIG. In FIG. 1 and FIG. 2, circuit components labeled with the same symbols indicate the same components. In FIG. 2, circuit blocks 1,
2, 3, 4, and 5 are a reference voltage generation circuit, a first differential amplifier, a second differential amplifier, and a first differential amplifier, respectively.
A voltage shift amplifier and a second voltage shift amplifier are shown, but these circuits are conventionally well-known circuits, and there is no need to be limited to these circuits, and other circuits having the same function may be used. It can be replaced with the following circuit. The circuit of FIG. 2 is merely one example.

The first and second differential amplifiers 2 and 3 are complementary type
This is a differential amplifier using MOS transistors.
In order to have a voltage difference of several tens to hundreds of mV in the input voltage V ₀ that inverts the output voltage, a p-MOS for the load is required.
Transistors and drive n-MOS transistors (Qp21 and Qn23, Qp22 and Qn24, Qp3
1 and Qn33, Qp32 and Qn34)) by changing the W/L,) by changing the mobility ratio, and) by changing the threshold voltage. As an example, a method of changing the W/L of ) will be described. Load p-MOS transistors Qp21, Qp22,
W/L of Qp31 and Qq32 are 1,
2, 2, 1, and the drive n-MOS transistors Qn23, Qn24, Qn33, Qn34 W/
If L is any value between 10 and 20, the reference voltage
When V ₁ is 2.5V and the voltage V ₀ of the constant voltage source line R is 2.5V, between the differential outputs V ₂₁ , V ₂₂ and V ₃₁ , V ₃₂ of the differential amplifiers 2 and 3, V ₂₁ <V ₂₂ and V ₃₁ > V ₃₂ holds true, and when voltage V ₀ is 2.4V, V ₂₁ > V ₂₂
And the relationship of V ₃₁ > V ₃₂ is, when the voltage V ₀ is 2.6V,
The relationships V ₂₁ <V ₂₂ and V ₃₁ <V ₃₂ hold true. In order to reduce the voltage difference between the input voltages V ₀ or the allowable voltage Va that the two differential amplifiers invert, the load p-MOS transistors Qp21 and Qp22 and Qp31 and
This can be easily achieved by reducing the difference in W/L of 32. Also, by the methods of ) and ) described above, it is possible to similarly provide a voltage difference to the inverting input terminal V ₀ .

The first and second voltage shift amplifiers 4 and 5 are composed of a differential amplifier and an inverter circuit, but when the amplification degree of the first and second differential amplifiers 2 and 3 is large, the voltage shift The amplifier for this purpose may be just an inverter circuit. The voltage shift amplifier completely changes the gate voltage V ₂ or V ₅ of the first or second MOS transistor to 0V or 5V when the voltage V ₀ of the constant voltage source line R reaches the inversion voltage V ₁ +Va. It plays a role in shifting. first and second
The W/L of the MOS transistors Qp1 and Qn2 is determined by the load capacitance C of the constant voltage source line R and the magnitude of the fluctuating voltage. For example, with C=1000pF and voltage V ₀
When a voltage fluctuation of 1V is considered, by setting the W/L of the transistors Qp1 and Qn2 to about 100, the voltage _V0 at the output terminal can be stabilized in about 200 nsec. Regarding current consumption, the circuits through which current flows in a steady state are the reference voltage generation circuit 1, the first and second differential amplifiers 2 and 3, and the first and second voltage shift amplifiers 4 and 5. It is only a differential amplifier, and the W/L of these load transistors
By keeping the value small, the steady current consumption in the entire circuit can be reduced.

As is clear from the above explanation, when the present invention is used, the current consumption is small when the voltage of the constant voltage source line is stable, but when the voltage fluctuates, a large current can be charged and discharged and output in a short time. An integrated semiconductor device can be provided that allows the voltage to be returned to a constant voltage. Furthermore, since this can be realized using MOS transistors, integration is easy and is very advantageous in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an integrated semiconductor device of the present invention, and FIG. 2 is a circuit diagram showing an example of the embodiment. In the figure, 1... reference voltage generation circuit, 2... first
differential amplifier, 3...second differential amplifier, 4...first
voltage shift amplifier, 5... second voltage shift amplifier, Qp1... first p-MOS transistor,
Qn2...second n-MOS transistor, C...load capacitance of constant voltage power supply line, R...constant voltage power supply line, V _DD ...5V
Power line, GND...0V grounding line.

Claims (1)

[Claims] 1 A first MOS transistor of a first conductivity type whose source is connected to a first power supply and a drain connected to an output terminal, and a second MOS transistor of a second conductivity type whose source is connected to a second power supply and whose drain is connected to the output terminal. a MOS transistor, a reference voltage generation circuit, and first and second transistors each having a voltage at the output terminal and the reference voltage as differential inputs;
and a first signal amplified through at least the first differential amplifier.
A second signal input to the gate of the MOS transistor and amplified through at least the second differential amplifier is input to the gate of the second MOS transistor, and the voltage at the output terminal is within a specific tolerance range from the reference voltage. , the first and second MOS transistors become non-conductive due to the first and second signals amplified in opposite directions, and the voltage at the output terminal falls within the allowable range. If the deviation occurs, the first and second signals are amplified in the same direction as each other.
An integrated semiconductor device comprising: means for making one of the MOS transistors conductive.