JPH0353050U - - Google Patents
Info
- Publication number
- JPH0353050U JPH0353050U JP11520789U JP11520789U JPH0353050U JP H0353050 U JPH0353050 U JP H0353050U JP 11520789 U JP11520789 U JP 11520789U JP 11520789 U JP11520789 U JP 11520789U JP H0353050 U JPH0353050 U JP H0353050U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- locked loop
- tuning
- filter
- time constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 101000588924 Anthopleura elegantissima Delta-actitoxin-Ael1a Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
Description
第1図は本考案に係るPLLの時定数制御回路
の一実施例を示す回路図、第2図は実施例の動作
を説明するためのタイミングチヤート、第3図は
同期検波方式を採用したテレビジヨン受像機を示
す回路図、第4図は従来のPLLの時定数制御回
路を示す回路図、第5図は従来例の問題点を説明
するためのタイミングチヤートである。
6……APC、7……VCO、8……映像検波
回路、13……ロツクデイテクタ、15……AP
Cフイルタ、Q2〜Q5……トランジスタ、C1
,C2……コンデンサ、R1〜R3……抵抗。
Fig. 1 is a circuit diagram showing an embodiment of a PLL time constant control circuit according to the present invention, Fig. 2 is a timing chart for explaining the operation of the embodiment, and Fig. 3 is a television using a synchronous detection method. FIG. 4 is a circuit diagram showing a conventional PLL time constant control circuit, and FIG. 5 is a timing chart for explaining problems in the conventional example. 6...APC, 7...VCO, 8...video detection circuit, 13...lock detector, 15...AP
C filter, Q2 to Q5...transistor, C1
, C2... Capacitor, R1-R3... Resistor.
Claims (1)
波信号の同一周波数のスイツチング信号を発生す
る位相固定ループと、 この位相固定ループの応答特性を決定するフイ
ルタと、 チヤンネル切換時に局部発振周波数を変化させ
ることによりジヤストチユーニングを行う選局回
路と、 前記ジヤストチユーニング動作時には前記フイ
ルタの時定数を変化させて前記位相固定ループの
応答特性を速くする定数変更手段とを具備したこ
とを特徴とするPLLの時定数制御回路。[Claims for Utility Model Registration] A phase-locked loop that generates a switching signal of the same frequency as an intermediate frequency signal in order to synchronously detect a received video signal, a filter that determines the response characteristics of this phase-locked loop, and channel switching. a tuning circuit that performs just tuning by changing a local oscillation frequency; and a constant changing means that changes a time constant of the filter to speed up the response characteristic of the phase-locked loop during the just tuning operation. A time constant control circuit for a PLL, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11520789U JPH0353050U (en) | 1989-09-28 | 1989-09-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11520789U JPH0353050U (en) | 1989-09-28 | 1989-09-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0353050U true JPH0353050U (en) | 1991-05-22 |
Family
ID=31663545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11520789U Pending JPH0353050U (en) | 1989-09-28 | 1989-09-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0353050U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002327404A (en) * | 2001-05-01 | 2002-11-15 | Sakai Heavy Ind Ltd | Compactor |
JP2008045362A (en) * | 2006-08-21 | 2008-02-28 | Mikasa Sangyo Co Ltd | Rammer handle connection apparatus |
-
1989
- 1989-09-28 JP JP11520789U patent/JPH0353050U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002327404A (en) * | 2001-05-01 | 2002-11-15 | Sakai Heavy Ind Ltd | Compactor |
JP2008045362A (en) * | 2006-08-21 | 2008-02-28 | Mikasa Sangyo Co Ltd | Rammer handle connection apparatus |
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