JPH0352354A - Packet exchange transmission delay measurement system - Google Patents
Packet exchange transmission delay measurement systemInfo
- Publication number
- JPH0352354A JPH0352354A JP1187741A JP18774189A JPH0352354A JP H0352354 A JPH0352354 A JP H0352354A JP 1187741 A JP1187741 A JP 1187741A JP 18774189 A JP18774189 A JP 18774189A JP H0352354 A JPH0352354 A JP H0352354A
- Authority
- JP
- Japan
- Prior art keywords
- packet
- transmission delay
- processor
- time
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 23
- 238000005259 measurement Methods 0.000 title claims description 10
- 238000000691 measurement method Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
Landscapes
- Small-Scale Networks (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はパケット交換機に関し、特にパケット交換機内
部の伝送遅延の測定方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet switch, and more particularly to a method for measuring transmission delay inside a packet switch.
従来、この種の伝送遅延測定方式においては、入力の回
線対応部を持つプロセッサと出力の回線対応部を持つプ
ロセッサにハードウエアのトリガ一回路を設定し、他の
パケットを通過させない状態で特定のパケットを通過さ
せ、２回線間のトリガーの発生する時刻を測定し算出し
ていた。Conventionally, in this type of transmission delay measurement method, a hardware trigger circuit is set up in a processor with an input line correspondence part and a processor with an output line correspondence part, and a specific packet is detected without passing other packets. The packet was passed through and the time at which the trigger occurred between the two lines was measured and calculated.
上述した従来のパケット交換機の伝送遅延測定方式はハ
ードウェアのトリガ−回路を設定して測定するため、測
定回線が固定される欠点がある。The above-described conventional transmission delay measurement method for a packet switch has the disadvantage that the measurement line is fixed because the measurement is performed by setting a hardware trigger circuit.
また、通過パケットを限定するため、パケット交換機が
稼働中は伝送遅延測定を行なうことができない。Furthermore, since the number of packets to be passed is limited, transmission delay measurement cannot be performed while the packet switch is in operation.
本発明のパケット交換機伝送遅延測定方式はマンマシン
インターフェースを有する第１のプロセッサとパケット
交換を行なう複数の第２のプロセッサとをループ状バス
に接続し、前記第２のプロセッサのそれぞれはパケット
回線インターフェースを有する回線対応部を備え、前記
第１のプロセッサは伝送遅延測定回線の情報を有するコ
マンド指示を該当する前記回線対応部へ送出する手段を
備え、前記回線対応部はコマンド指示を受信した時刻を
測定する第１の手段と、相手測定回線へテストパケット
を送出する第２の手段と、テストパケットを受信すると
直ちに送出元の前記回線対応部にテストパケットを返送
する第３の手段と、返送されたテストパケットの到着時
刻を測定する第４の手段と、前記第１の手段により得た
テストパケット送出時刻と前記第４の手段で得た到着時
刻とからパケット交換機内部の伝送遅延時間を算出し前
記第１のプロセッサに報告する第５の手段とを備える。The packet switch transmission delay measurement method of the present invention connects a first processor having a man-machine interface and a plurality of second processors that perform packet switching to a loop bus, and each of the second processors has a packet line interface. The first processor includes a means for sending a command instruction having information on the transmission delay measurement line to the corresponding line corresponding section, and the line corresponding section is configured to determine the time at which the command instruction is received. a first means for measuring, a second means for sending a test packet to the other party's measurement line, a third means for immediately sending the test packet back to the line corresponding unit from which it was sent upon receiving the test packet; a fourth means for measuring the arrival time of the test packet obtained by the first means; and calculating a transmission delay time inside the packet switch from the test packet sending time obtained by the first means and the arrival time obtained by the fourth means. and fifth means for reporting to the first processor.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
一実施例を示す第１図を参照すると、マンマシンプロセ
ッサ２とパケット交換用プロセッサ３とは１つのループ
状バス１に接続され、パケット交換用プロセッサ３にパ
ケット回線インターフェースを持つ回線対応部４が接続
されている。マンマシンプロセッサ２から入力された伝
送遅延測定コマンドは交換用プロセッサ３の回線対応部
４ａに送られ、その時の時刻が測定され、直ちに相手回
線対応部４ｂにテストパケットを送出する。相手回線対
応部４ｂではこのテストパケットを受信すると同時に送
出元へ返送し、送出元回線対応部４ａに返送された時刻
を測定する。送出元回線対応部４ａはテストパケットの
送信信号と受信時刻から伝送遅延時間を算出し、結果を
マンマシンプロセッサ２へ報告する。マンマシンプロセ
ッサ２はこの情報をコマンド応答として表示する。Referring to FIG. 1 showing one embodiment, a man-machine processor 2 and a packet switching processor 3 are connected to one loop bus 1, and a line corresponding section 4 having a packet line interface is connected to the packet switching processor 3. It is connected. The transmission delay measurement command inputted from the man-machine processor 2 is sent to the line corresponding section 4a of the exchange processor 3, the time at that time is measured, and a test packet is immediately sent to the other line corresponding section 4b. At the same time as receiving this test packet, the other line corresponding section 4b returns it to the sending source, and measures the time at which it is sent back to the sending source line corresponding section 4a. The source line correspondence unit 4a calculates the transmission delay time from the transmission signal and reception time of the test packet, and reports the result to the man-machine processor 2. The man-machine processor 2 displays this information as a command response.
以上説明したように本発明によれば、パケット交換機の
内部に伝送遅延を測定する機能を付与することにより、
ハードウェアのトリガー回路を必要とすることなく、コ
マンドで指定する回線の間の伝送遅延を測定できる。ま
た、パケット交換機が稼働中でも伝送遅延測定を行なえ
る．As explained above, according to the present invention, by providing a function to measure transmission delay inside a packet switch,
Transmission delays between lines specified by commands can be measured without the need for a hardware trigger circuit. Furthermore, transmission delay measurements can be performed even when the packet switch is in operation.
第１図は本発明の一実施例を示す構或図である。
１・・・ループ状バス、２・・・マンマシンプロセッサ
、３・・・パケット交換用プロセッサ、４・・・回線対
応部、４ａ・・・送出元回線対応部、４ｂ・・・送出先
回線対応部。FIG. 1 is a structural diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Loop bus, 2... Man-machine processor, 3... Processor for packet switching, 4... Line corresponding section, 4a... Source line corresponding section, 4b... Destination line Correspondence department.
Claims (1)
とパケット交換を行なう複数の第２のプロセッサとをル
ープ状バスに接続し、 前記第２のプロセッサのそれぞれはパケット回線インタ
ーフェースを有する回線対応部を備え、前記第１のプロ
セッサは伝送遅延測定回線の情報を有するコマンド指示
を該当する前記回線対応部へ送出する手段を備え、 前記回線対応部はコマンド指示を受信した時刻を測定す
る第１の手段と、相手測定回線へテストパケットを送出
する第２の手段と、テストパケットを受信すると直ちに
送出元の前記回線対応部にテストパケットを返送する第
３の手段と、返送されたテストパケットの到着時刻を測
定する第４の手段と、前記第１の手段により得たテスト
パケット送出時刻と前記第４の手段で得た到着時刻とか
らパケット交換機内部の伝送遅延時間を算出し前記第１
のプロセッサに報告する第５の手段とを備えることを特
徴とするパケット交換機伝送遅延測定方式。[Scope of Claims] A first processor having a man-machine interface and a plurality of second processors that perform packet switching are connected to a loop bus, and each of the second processors is line compatible having a packet line interface. the first processor includes a means for sending a command instruction having information on a transmission delay measurement line to the corresponding line corresponding section, and the line corresponding section measures a time at which the command instruction is received. a second means for transmitting a test packet to the other party's measurement line; a third means for immediately transmitting the test packet to the transmission source line corresponding unit upon receiving the test packet; a fourth means for measuring the arrival time, and calculating a transmission delay time inside the packet switch from the test packet sending time obtained by the first means and the arrival time obtained by the fourth means;
and fifth means for reporting to the processor of the packet switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1187741A JPH0352354A (en) | 1989-07-19 | 1989-07-19 | Packet exchange transmission delay measurement system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1187741A JPH0352354A (en) | 1989-07-19 | 1989-07-19 | Packet exchange transmission delay measurement system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0352354A true JPH0352354A (en) | 1991-03-06 |
Family
ID=16211385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1187741A Pending JPH0352354A (en) | 1989-07-19 | 1989-07-19 | Packet exchange transmission delay measurement system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0352354A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5620178A (en) * | 1994-03-10 | 1997-04-15 | Sindo Richo Co., Ltd. | Sheet post treatment apparatus for stapling having a sheet aligning member |
| US6866924B2 (en) | 2001-02-14 | 2005-03-15 | Ricoh Company, Ltd. | Tissue paper used for heat-sensitive stencil sheet, heat-sensitive stencil sheet, and method of making the same |
| JP2013197643A (en) * | 2012-03-16 | 2013-09-30 | Hitachi Ltd | Communication apparatus |
-
1989
- 1989-07-19 JP JP1187741A patent/JPH0352354A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5620178A (en) * | 1994-03-10 | 1997-04-15 | Sindo Richo Co., Ltd. | Sheet post treatment apparatus for stapling having a sheet aligning member |
| US6866924B2 (en) | 2001-02-14 | 2005-03-15 | Ricoh Company, Ltd. | Tissue paper used for heat-sensitive stencil sheet, heat-sensitive stencil sheet, and method of making the same |
| US6946049B2 (en) | 2001-02-14 | 2005-09-20 | Ricoh Company, Ltd. | Tissue paper used for heat-sensitive stencil sheet, heat-sensitive stencil sheet, and method of making the same |
| JP2013197643A (en) * | 2012-03-16 | 2013-09-30 | Hitachi Ltd | Communication apparatus |
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