JPH02246429A - Self-check circuit for communication equipment - Google Patents

Abstract

PURPOSE:To attain the flexibility for the production of a self-check signal pattern and the decision of check by using a microprocessor to generate the self-check signal pattern and to check the signal pattern after looping back to its own station. CONSTITUTION:When a self-check request signal (f) is inputted, a microprocessor 9 outputs a self-check select signal (c) to select circuits 2, 4, 6 to form a loopback path comprising the microprocessor 9, a P/S conversion circuit 1, a transmission circuit 3, a reception circuit 5, an S/P conversion circuit 7, a buffer circuit 8 and the microprocessor 9. The microprocessor 9 outputs n-set of patterns of self-check signals (a) in parallel, the loopbacked self-check signal (a) and a check data are compared to judge whether or not there is a fault in the communication equipment. Thus, it is easy to combine or revise the self-check signal patterns.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a self-check circuit for a communication device that performs a self-check of the communication device by returning to its own station.

[Conventional technology]

Conventionally, a local station loopback self-check circuit in a communication device generates a self-check signal pattern in a self-check signal pattern generation circuit, returns this self-check signal from a transmitting section to a receiving section within the local station device, and The self-check signal pattern check circuit is used to check the returned self-check signal pattern to determine whether or not there is an abnormality in the own communication device.

[Problem to be solved by the invention]

In the conventional local station loopback self-check circuit described above,
It has the following drawbacks.

(a) It requires a signal pattern generation circuit for self-check and a signal pattern check circuit for self-check, and since these circuits are configured only with hardware, it is possible to use multiple patterns for self-check with flexibility in the pattern. Generating and checking signal patterns requires several types of self-check signal pattern generation circuits and self-check signal pattern check circuits, which is physically difficult in terms of component mounting area.

(b) When trying to generate and check several types of self-check signal patterns using one type of self-check signal pattern generation circuit and self-check signal pattern check circuit, the self-check signal pattern must be set at any time. This was also impossible from the standpoint of redundancy.

SUMMARY OF THE INVENTION An object of the present invention is to provide a self-check circuit for a communication device that solves the above-mentioned conventional problems and allows easy combinations and changes of self-check signal patterns.

(Means for Solving Problem 18) The present invention is a self-check circuit for a communication device that performs a self-check of the device by returning a self-check signal from a transmitting circuit in the communication device to a receiving circuit, the circuit comprising: a parallel signal; a parallel/serial conversion circuit that converts the serial signal into a serial signal and inputs it to the transmitting circuit; a serial/parallel conversion circuit that converts the serial signal from the receiving circuit to a parallel signal and outputs it; and a self-check by software control. A plurality of patterns of self-check signals necessary for the process are output in parallel to the parallel/serial conversion circuit, and the parallel self-check signals that are folded back and output from the serial/parallel conversion circuit are input, and the input multiple patterns are and a microprocessor that determines whether the communication device is abnormal based on the self-check signal.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a self-check circuit for a communication device according to an embodiment of the present invention.

The self-check circuit for a communication device of this example includes a P/S conversion circuit (parallel/serial conversion circuit) 1, a selection circuit 2, a transmission circuit 3, a selection circuit 4, a reception circuit 5, and a selection circuit 6. , an S/P conversion circuit (serial/parallel conversion circuit) 7, a buffer circuit 8, and a microprocessor 9 for controlling these.

The P/S conversion circuits 1 are six circuits that convert a self-check signal a inputted in parallel from the microprocessor 9 into a serial self-check signal A and output it to the select circuit 2.

The selection circuit 2 selects either the communication signal d from the communication signal input terminal 10 or the self-check signal s from the P/S conversion circuit 1 based on the self-check selection signal C from the microprocessor 9. This is a circuit that outputs to the transmitting circuit 3.

The transmitting circuit 3 is a circuit that transmits the communication signal d or the self-check signal from the select circuit 2 to the line output terminal 11 side.

The selection circuit 4 selects a transmission path from the transmission circuit 3 to the line output terminal 11 or a transmission path from the transmission circuit 3 to the reception circuit 5 based on a self-check selection signal C from the microprocessor 9.
Select one of the return routes and send the transmitter circuit 3 or -
This circuit makes it possible to transmit the signals from the line output terminal 11 to the line output terminal 11 or return them to the receiving circuit 5.

The receiving circuit 5 is a circuit that receives the communication signal from the line input terminal 12 or the signal returned from the transmitting circuit 3 by the select circuit 4, and outputs it to the select circuit 6.

The selection circuit 6 is a circuit that selects either the path from the receiving circuit 5 to the communication signal output terminal 13 or the path from the receiving circuit 5 to the S/P conversion circuit 7 based on the self-check select signal C from the microprocessor 9. It is.

The S/P conversion circuit 7 is a circuit that converts the signal serially inputted from the select circuit 6 into a parallel signal and outputs the parallel signal to the buffer circuit 8.

The buffer circuit 8 is a circuit that inputs the parallel signal from the S/P conversion circuit 7 to the microprocessor 9 in synchronization with the read timing of the read signal e input from the microprocessor 9 via the OR gate 14.

The microprocessor 9 is a circuit that performs at least a return route forming function, a self-check signal input/output function, and a self-check signal check function under the control of predetermined software. The return route forming function means that when the self-check request signal f is input, the microprocessor 9 outputs the self-check select signal C to the select circuits 2 and 4.6, and the select circuit 2
to select the path from the P/S conversion circuit 1 to the transmission circuit 3, to the selection circuit 4 to select the path from the transmission circuit 3 to the reception circuit 5, and to the selection circuit 6 to select the path from the reception circuit 5 to the S/P conversion circuit 7. By doing so, the output self-check signal can be
S conversion circuit 1. Transmission circuit 3. Receiving circuit 5. This is a function to loop back and input the signal along the path of the S/P conversion circuit 7 and the buffer circuit 8.

The self-check signal input/output function is to output in parallel several types of self-check signals necessary for checking based on the self-check request signal r after forming the return path, and output them in parallel from the buffer circuit 8. This is a function to input a signal for self-check. The self-check signal check function compares the parallel self-check signal input from the buffer circuit 8 with pre-programmed data and sends an alarm signal if it is determined that there is an abnormality in the communication device. This function outputs g.

Next, the operation of this embodiment will be explained.

When a self-check request signal f is input to the microprocessor 9 from a supervisory control device or the like (not shown), the microprocessor 9 sends a self-check select signal C to the select circuits 2, 4.6 according to a preprogrammed program. Output. Self-check select signal C
Based on this, the select circuit 2 selects the path from the P/S conversion circuit 1 to the transmitter circuit 3, the select circuit 4 selects the path from the transmitter circuit 3 to the receiver circuit 5, and the select circuit 6
~Select the route of the S/P conversion circuit 7. This allows the microprocessor 9. P/S conversion circuit 1. Transmission circuit 3.
Receiving circuit 5. S/P conversion circuit 7, buffer circuit 8. A return path for the microprocessor 9 is formed.

After forming the return route, the microprocessor 9 outputs n patterns of self-check signals a (a, to an) in parallel, which are necessary for checking the communication device, based on the input self-check request signal f. . These parallel self-check signals a (al”wan) are
It is converted into a serial self-check signal by the P/S conversion circuit 1, and sent to the transmission circuit 3 via the selection circuit 2.
is output to. The self-check signal input to the transmitting circuit 3 is transmitted by the transmitting circuit 3. This self-check signal reaches the receiving circuit 5 via the select circuit 4 and is received. The receiving circuit 5 sends the received serial self-check signal to the S/S via the select circuit 6.
It is output to the P conversion circuit 7.

The serial self-check signal input to the S/P conversion circuit 7 is the parallel self-check signal a (al
waa) and output to the buffer circuit 8. The buffer circuit 8 inputs the input parallel self-check signal a to the microprocessor 9 in synchronization with the read timing indicated by the read signal e from the microprocessor 9.

The microprocessor 9, which has received the returned self-check signal a, compares the self-check signal a with pre-programmed check data.
Determine whether there is an abnormality in the communication device. As a result of this check, if it is determined that there is an abnormality in the communication device, an alarm signal g is sent to the monitoring control device or the like.

〔Effect of the invention〕

As explained above, the self-check circuit for a communication device of the present invention generates a self-check signal pattern and generates a self-check signal pattern after returning to the own station when performing a self-check by looping back within the own station's communication device. Since the check is performed using a microprocessor, it is possible to have flexibility in generating the self-check signal pattern and determining the check, and to simplify and downsize the self-check circuit for communication equipment. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a self-check circuit for a communication device according to an embodiment of the present invention. 1...P/S conversion circuit 3...Transmission circuit 5...Reception circuit 7...S/P conversion circuit 9...Microprocessor agent Patent attorney Yoshiyuki Iwasa

Claims (1)

[Claims] (1) A self-check circuit for a communication device that performs a self-check of the device by returning a self-check signal from a transmitting circuit in the communication device to a receiving circuit, the transmitting circuit converting a parallel signal into a serial signal. A parallel/serial conversion circuit that converts the serial signal from the receiving circuit into a parallel signal and outputs the parallel signal, and a serial/parallel conversion circuit that converts the serial signal from the receiving circuit into a parallel signal and outputs it, and multiple patterns of self-check signals necessary for self-check by software control. is outputted in parallel to the parallel/serial conversion circuit, the parallel self-check signal that is folded back and output from the serial/parallel conversion circuit is inputted, and the communication device transmits the self-check signal based on the input multiple patterns of self-check signals. A self-check circuit for a communication device, comprising: a microprocessor for determining an abnormality in a communication device.