JPH0352211B2 - - Google Patents

Info

Publication number
JPH0352211B2
JPH0352211B2 JP58063359A JP6335983A JPH0352211B2 JP H0352211 B2 JPH0352211 B2 JP H0352211B2 JP 58063359 A JP58063359 A JP 58063359A JP 6335983 A JP6335983 A JP 6335983A JP H0352211 B2 JPH0352211 B2 JP H0352211B2
Authority
JP
Japan
Prior art keywords
height
deflection distortion
chip
sample surface
distortion correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58063359A
Other languages
Japanese (ja)
Other versions
JPS59188916A (en
Inventor
Korehito Matsuda
Tsuneo Ookubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58063359A priority Critical patent/JPS59188916A/en
Publication of JPS59188916A publication Critical patent/JPS59188916A/en
Publication of JPH0352211B2 publication Critical patent/JPH0352211B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/304Controlling tubes by information coming from the objects or from the beam, e.g. correction signals

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、電子ビームもしくはイオンビーム露
光装置における偏向歪補正方法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a deflection distortion correction method in an electron beam or ion beam exposure apparatus.

〔従来技術〕 電子ビームもしくはイオンビーム露光装置にお
いては、描画パタンのつなぎ合せ、重ね合せを高
精度に行なうために、偏向歪の補正を高精度に行
なわなければならない。従来この種の方法はいく
つか考案されているが、第1図にその代表的なも
のの原理を示す。図において、1は上面の偏向歪
測定用マーク、2は下面の偏向歪測定用マーク、
3は試料、4はビーム偏向器を示す。
[Prior Art] In an electron beam or ion beam exposure apparatus, correction of deflection distortion must be performed with high precision in order to connect and overlay drawn patterns with high precision. Several methods of this type have been devised in the past, and FIG. 1 shows the principle of a typical one. In the figure, 1 is a mark for measuring deflection distortion on the top surface, 2 is a mark for measuring deflection distortion on the bottom surface,
3 indicates a sample, and 4 indicates a beam deflector.

上記構成において、まず上下2面の歪測定用マ
ーク1および2についてマーク検出を行なつて偏
向歪量を測定し、その測定結果に基いて偏向歪補
正係数を求めた後、試料面3の高さZを測定す
る。上下2面の高さの差Hは予め知られているた
め、試料面3での偏向歪補正係数は、先に求めた
上下2面についての偏向歪補正係数から、内挿法
により容易に求めることができる。したがつて、
この方法では試料面の高さZをいかに正確に測定
するかがポイントとなる。
In the above configuration, mark detection is first performed for the distortion measurement marks 1 and 2 on the upper and lower surfaces to measure the amount of deflection distortion, and after determining the deflection distortion correction coefficient based on the measurement results, the height of the sample surface 3 is determined. Measure Z. Since the height difference H between the upper and lower surfaces is known in advance, the deflection distortion correction coefficient for sample surface 3 can be easily determined by interpolation from the deflection distortion correction coefficients for the upper and lower surfaces obtained previously. be able to. Therefore,
In this method, the key point is how accurately the height Z of the sample surface can be measured.

第2図に、試料面の高さの測定方法を示す。図
において、5は光発生器、6は位置決め用受光素
子、7は光学軸、8は半導体集積回路チツプ、9
はビーム偏向フイールドであり、試料面で反射し
た光が受光素子6を照射する照射位置によつて試
料面の高さが測定できる。半導体集積回路チツプ
8は、1つ以上のビーム偏向フイールド9からな
る。各偏向フイールドごとにパタン描画が行なわ
れ、チツプ8が2つ以上の偏向フイールドのつな
ぎ合わせで描画される場合にはステージ移動によ
り試料を移動させながら各偏向フイールドについ
て順次パタン描画して行く。その場合、上記試料
面の高さは、従来偏向フイールドの中央またはチ
ツプ中央で測定していた。
FIG. 2 shows the method for measuring the height of the sample surface. In the figure, 5 is a light generator, 6 is a positioning light receiving element, 7 is an optical axis, 8 is a semiconductor integrated circuit chip, and 9 is a light receiving element for positioning.
is a beam deflection field, and the height of the sample surface can be measured by the irradiation position where the light receiving element 6 is irradiated with the light reflected from the sample surface. The semiconductor integrated circuit chip 8 consists of one or more beam deflection fields 9. A pattern is drawn for each deflection field, and when the chip 8 is drawn by connecting two or more deflection fields, the pattern is sequentially drawn for each deflection field while moving the sample by moving the stage. In that case, the height of the sample surface is conventionally measured at the center of the deflection field or the center of the chip.

しかし、半導体集積回路は、既に描画し、所定
のプロセスを経た層の上から数回ないし十数回も
違つた層のパタンを描画するため、チツプの表面
には凹凸ができる。その結果、特に微細なパタン
が密集した部分では高さ測定用の光が散乱され、
光量が著しく低下するために正しく試料面の高さ
を測定することができなくなる。通常半導体集積
回路のチツプ内部は微細なパタンで埋まつてお
り、従来の方法ではプロセスの進行に伴つて試料
面の高さを正確に測定することが困難となる。実
験によれば、パタンが密集したところとパタンが
無いところでは高さの差は200μm以上にもなり、
パタンの重ね合せおよびつなぎ合せ精度も0.5μm
にもなることがわかつた。
However, in semiconductor integrated circuits, patterns for different layers are drawn several to more than ten times over layers that have already been drawn and undergone a predetermined process, resulting in unevenness on the surface of the chip. As a result, the light for height measurement is scattered especially in areas where fine patterns are densely packed.
Since the amount of light decreases significantly, it becomes impossible to accurately measure the height of the sample surface. The inside of a semiconductor integrated circuit chip is usually filled with minute patterns, and with conventional methods, it is difficult to accurately measure the height of the sample surface as the process progresses. According to experiments, the difference in height between areas with dense patterns and areas with no patterns is over 200 μm.
Pattern overlay and connection accuracy is 0.5μm
I found out that it also works.

〔発明の目的および構成〕[Object and structure of the invention]

本発明はこのような事情に鑑みてなされたもの
で、その目的は、試料面の高さを正確に求め、高
精度な偏向歪補正を行なうことが可能な偏向歪補
正方法を提供することにある。
The present invention has been made in view of the above circumstances, and its purpose is to provide a deflection distortion correction method that can accurately determine the height of a sample surface and perform highly accurate deflection distortion correction. be.

このような目的を達成するために、本発明は、
試料面の高さの決定を、位置合せ用マークと特定
の位置関係にある試料面を平坦化しておき、その
試料面について測定した結果に基いてチツプ内部
の高さを算出することにより行なうものである。
In order to achieve such an objective, the present invention
The height of the sample surface is determined by flattening the sample surface in a specific positional relationship with the alignment mark, and then calculating the height inside the chip based on the measurement results for that sample surface. It is.

すなわち、チツプ内の描画パタンの密集してい
る部分での測定を避け、描画パタンの少ない、も
しくは無い平坦部において先に述べたような光学
的手法により測定し、その結果に基いてチツプ内
部の高さを算出するもので、その場合、測定位置
を決めるために、ビーム位置合せ用のマークを利
用するものである。以下、実施例を用いて本発明
を詳細に説明する。
In other words, avoid measuring areas in the chip where drawing patterns are densely packed, measure using the optical method described above on flat areas with few or no drawing patterns, and based on the results, measure the inside of the chip. The height is calculated, and in this case, marks for beam alignment are used to determine the measurement position. Hereinafter, the present invention will be explained in detail using Examples.

〔実施例〕〔Example〕

半導体集積回路チツプ8は、ウエハからなる試
料3の面上に第3図に示すように配置される。チ
ツプ周辺部は、第4図に拡大して示すように通常
100〜200μm幅のスクライプライン10を構成し
ている。11はこのスクライブライン中に設けた
位置合せ用のマークであり、実際の描画に際して
は、このマーク11を検出しながらビームの位置
決めを行なう。
The semiconductor integrated circuit chip 8 is placed on the surface of the sample 3, which is a wafer, as shown in FIG. The area around the chip is normally
A scribe line 10 having a width of 100 to 200 μm is configured. Reference numeral 11 denotes an alignment mark provided in this scribe line, and during actual drawing, the beam is positioned while detecting this mark 11.

第5図は、本発明の一実施例を示すビーム露光
装置のブロツク図である。図において、12は高
さ測定器、13は高さ演算回路、14は反射電子
検出器、15はマーク検出回路、16は制御計算
機、17はインターフエース、18は上下2面の
偏向歪補正係数メモリ、19は補正係数演算回
路、20は描画シーケンサー、21は試料面の補
正係数メモリ、22はパタンデータメモリ、23
はパタンデータ処理回路、24はビーム偏向回
路、25は高さ測定結果のメモリである。
FIG. 5 is a block diagram of a beam exposure apparatus showing one embodiment of the present invention. In the figure, 12 is a height measuring device, 13 is a height calculation circuit, 14 is a backscattered electron detector, 15 is a mark detection circuit, 16 is a control computer, 17 is an interface, and 18 is a deflection distortion correction coefficient for the upper and lower surfaces. Memory, 19 is a correction coefficient calculation circuit, 20 is a drawing sequencer, 21 is a sample surface correction coefficient memory, 22 is a pattern data memory, 23
2 is a pattern data processing circuit, 24 is a beam deflection circuit, and 25 is a memory for height measurement results.

上記構成において、半導体集積回路等のパタン
描画に先立つて、従来と同様に上下2面の偏向歪
測定用マークにより当該上下2面の偏向歪を測定
し、その測定結果に基いて偏向歪補正係数を制御
計算機16により求め、当該補正係数をメモリ1
8に記憶しておく。次に、ステージ移動を行なつ
てチツプ8の左下にある位置合せ用マーク11が
ビーム中心にくるようにし、その点の試料面の高
さを高さ測定器12により測定するとともに、そ
の測定結果をメモリ25に記憶する。その後、反
射電子検出回路14およびマーク検出回路15に
より当該マークの位置検出を行ない、ステージを
次のマークに移動する。ここで再び試料面の高さ
を測定し、その測定結果をメモリ25に記憶す
る。この操作をチツプ8を囲む四隅のマークにつ
いて行ない、マーク位置も検出する。チツプ四隅
での高さ情報は、高さ演算回路13においてその
最大値と最小値を除く2つについての平均値が算
出され、その結果がチツプ内部の高さとして制御
計算機16の内部メモリに記憶される。このチツ
プの高さ情報は、インターフエース17を通し、
さらにメモリ18の上下2面の偏向歪補正係数を
伴つて補正係数算出回路19に入り、そこで直線
補間法を用いて試料面の高さに応じた補正係数に
変換される。この変換された補正係数は補正係数
メモリ21に記憶される。マーク位置情報も同様
の経過で演算され、試料の歪に対する補正係数が
補正係数メモリ21に記憶される。これら高さお
よびマーク位置の演算は、描画シーケンサー20
の制御により順序正しく行なわれる。
In the above configuration, prior to drawing a pattern of a semiconductor integrated circuit, etc., the deflection distortion of the two upper and lower surfaces is measured using the deflection distortion measurement marks on the upper and lower surfaces, as in the past, and the deflection distortion correction coefficient is calculated based on the measurement results. is determined by the control computer 16, and the correction coefficient is stored in the memory 1.
Remember it in 8. Next, the stage is moved so that the alignment mark 11 at the lower left of the chip 8 is at the center of the beam, and the height of the sample surface at that point is measured by the height measuring device 12, and the measurement results are is stored in the memory 25. Thereafter, the position of the mark is detected by the reflected electron detection circuit 14 and the mark detection circuit 15, and the stage is moved to the next mark. Here, the height of the sample surface is measured again, and the measurement results are stored in the memory 25. This operation is performed for the marks at the four corners surrounding the chip 8, and the mark positions are also detected. As for the height information at the four corners of the chip, the height calculation circuit 13 calculates the average value of the two excluding the maximum and minimum values, and the result is stored in the internal memory of the control computer 16 as the height inside the chip. be done. This chip height information is transmitted through the interface 17.
Furthermore, the deflection distortion correction coefficients for the upper and lower surfaces of the memory 18 are entered into a correction coefficient calculation circuit 19, where they are converted into correction coefficients corresponding to the height of the sample surface using a linear interpolation method. This converted correction coefficient is stored in the correction coefficient memory 21. Mark position information is also calculated in a similar manner, and correction coefficients for sample distortion are stored in the correction coefficient memory 21. These height and mark position calculations are performed by the drawing sequencer 20.
This is done in an orderly manner under the control of

一方、半導体集積回路用パタンデータは、パタ
ンデータメモリ22に記憶されており、制御計算
機16から描画の指令を受けると当該データはパ
タンデータ処理回路23に入り、そこでメモリ2
1から転送されて来た試料面の補正係数との間で
歪補正演算が行なわれ、正しいパタン位置データ
となる。当該パタン位置データは、ビーム偏向制
御回路24に送出され、この結果ビームは正しく
偏向されることとなる。
On the other hand, pattern data for semiconductor integrated circuits is stored in a pattern data memory 22, and when a drawing command is received from the control computer 16, the data enters the pattern data processing circuit 23, where it is stored in the memory 22.
A distortion correction calculation is performed with the sample surface correction coefficient transferred from 1, resulting in correct pattern position data. The pattern position data is sent to the beam deflection control circuit 24, and as a result, the beam is correctly deflected.

本実施例では、各チツプ四隅の周辺について高
さを測定し、その最大・最小値を除く2点の測定
結果の平均値をチツプ全体の高さとした。通常の
LSIプロセスを経た試料では、ウエハの変形量は
高々50μmであり、チツプ間では10μm以下であ
る。ビームのランデイング角を2.5mradとする
と、10μmの高さ変化によるビーム位置のずれは
0.025μmであり実用上全く問題はない。試料の変
形が特に大きな試料に対しては、上述したような
チツプ周辺での高さ測定結果に基き、チツプ内の
高さ変化を平面または曲面近似により求め、チツ
プを分割する偏向フイールド単位で偏向歪補正演
算を行なえばよい。また逆に、試料が平坦な場合
には、複数チツプごとにチツプ周辺の高さ測定を
行ない、当該測定データを単に平均して各チツプ
の高さとしてもよい。
In this example, the height was measured around the four corners of each chip, and the average value of the measurement results at two points excluding the maximum and minimum values was taken as the height of the entire chip. normal
For samples that have undergone the LSI process, the amount of deformation on the wafer is at most 50 μm, and between chips it is less than 10 μm. If the beam landing angle is 2.5 mrad, the beam position shift due to a 10 μm height change is
It is 0.025 μm, which poses no practical problem. For samples with particularly large deformations, the height change within the chip is determined by plane or curved surface approximation based on the height measurement results around the chip as described above, and the deflection is performed in units of deflection fields that divide the chip. It is sufficient to perform distortion correction calculations. Conversely, if the sample is flat, the height around each chip may be measured for each chip, and the measured data may simply be averaged to determine the height of each chip.

また、上述した実施例では高さ測定をチツプ周
辺の位置合せ用マーク上で行なつたが、必ずしも
マーク上でなくても、当該マークを基準として特
定の位置関係にある近傍の試料面を平坦化してお
き、そこで行なうようにしてもよい。
In addition, in the above-mentioned embodiment, the height was measured on the alignment mark around the chip, but it is not necessary to measure the height on the alignment mark. You can also create a file and do it there.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、試料面
の高さ測定を描画チツプの周辺もしくはチツプ内
部に設けた位置合せ用マーク上またはその近傍の
平坦部で行なうようにしたことにより、描画パタ
ンの密集する中央部で直接測定する場合のように
凹凸による高さ測定器への外乱がなく、きわめて
信頼性の高い高さ測定が可能である。したがつて
高精度な偏向歪補正が行なえる。
As explained above, according to the present invention, the height of the sample surface is measured on the alignment mark provided around the drawing chip or inside the chip, or on a flat part in the vicinity, thereby making it possible to improve the drawing pattern. There is no disturbance to the height measuring device due to unevenness, unlike when directly measuring in the central area where there is a high density of trees, and extremely reliable height measurement is possible. Therefore, highly accurate deflection distortion correction can be performed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は偏向歪補正方法の原理を説明するため
の図、第2図は従来の試料面の高さの測定方法を
説明するための図、第3図は半導体集積回路チツ
プの配列図、第4図はチツプ周辺を拡大して示す
詳細図、第5図は本発明の一実施例を示すビーム
露光装置のブロツク図である。 1……上面の偏向歪測定用マーク、2……下面
の偏向歪測定用マーク、3……試料、4……ビー
ム偏向器、5……光発生器、6……位置決め用受
光素子、7……光学軸、8……半導体集積回路チ
ツプ、9……ビーム偏向フイールド、10……ス
クライブライン、11……位置合せ用マーク、1
2……高さ測定器、13……高さ演算回路、14
……反射電子検出器、15……マーク検出回路、
16……制御計算機、17……インターフエー
ス、18……上下2面の偏向歪補正係数メモリ、
19……補正係数演算回路、20……描画シーケ
ンサー、21……試料面の補正係数メモリ、22
……パタンデータメモリ、23……パタンデータ
処理回路、24……ビーム偏向回路、25……高
さ測定結果のメモリ。
Fig. 1 is a diagram for explaining the principle of the deflection distortion correction method, Fig. 2 is a diagram for explaining the conventional method for measuring the height of the sample surface, Fig. 3 is an arrangement diagram of semiconductor integrated circuit chips, FIG. 4 is a detailed enlarged view showing the vicinity of the chip, and FIG. 5 is a block diagram of a beam exposure apparatus showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Mark for measuring deflection distortion on the top surface, 2... Mark for measuring deflection distortion on the bottom surface, 3... Sample, 4... Beam deflector, 5... Light generator, 6... Light receiving element for positioning, 7 ...Optical axis, 8...Semiconductor integrated circuit chip, 9...Beam deflection field, 10...Scribe line, 11...Alignment mark, 1
2...Height measuring device, 13...Height calculation circuit, 14
...Backscattered electron detector, 15...Mark detection circuit,
16... Control computer, 17... Interface, 18... Upper and lower deflection distortion correction coefficient memory,
19... Correction coefficient calculation circuit, 20... Drawing sequencer, 21... Correction coefficient memory for sample surface, 22
... Pattern data memory, 23 ... Pattern data processing circuit, 24 ... Beam deflection circuit, 25 ... Memory for height measurement results.

Claims (1)

【特許請求の範囲】[Claims] 1 予め設けた既知の段差を有する上下2面に取
り付けた偏向歪測定用マークを用い、当該上下2
面のマーク検出により偏向歪を測定しその測定結
果に基いて上下2面の偏向歪補正係数を算出する
とともに、試料面の高さを決定して上記上下2面
の偏向歪補正係数から当該試料面の高さに応じた
偏向歪補正係数を求める電子ビームもしくはイオ
ンビーム露光装置における偏向歪補正方法におい
て、上記試料面の高さの決定を、当該試料面に描
画すべき集積回路を構成する各チツプもしくは複
数チツプごとに設けた位置の基準となるマークと
特定の位置関係にある平坦化した試料面について
高さを測定し、その測定結果に基いて描画チツプ
内部の高さを算出することによつて行なうことを
特徴とする偏向歪補正方法。
1 Using deflection distortion measurement marks attached to the upper and lower surfaces with a known level difference prepared in advance,
Deflection distortion is measured by detecting marks on the surface, and based on the measurement results, the deflection distortion correction coefficients for the upper and lower surfaces are calculated.The height of the sample surface is determined and the deflection distortion correction coefficients for the upper and lower surfaces are used to calculate the deflection distortion correction coefficients for the above-mentioned two surfaces. In a deflection distortion correction method in an electron beam or ion beam exposure apparatus that calculates a deflection distortion correction coefficient according to the height of a surface, the height of the sample surface is determined by each of the integrated circuits that constitute the integrated circuit to be drawn on the sample surface. The height is measured on the flattened sample surface in a specific positional relationship with the reference mark provided for each chip or multiple chips, and the height inside the drawing chip is calculated based on the measurement results. A deflection distortion correction method characterized in that the deflection distortion is corrected by
JP58063359A 1983-04-11 1983-04-11 Correction of deflection distortion Granted JPS59188916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58063359A JPS59188916A (en) 1983-04-11 1983-04-11 Correction of deflection distortion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58063359A JPS59188916A (en) 1983-04-11 1983-04-11 Correction of deflection distortion

Publications (2)

Publication Number Publication Date
JPS59188916A JPS59188916A (en) 1984-10-26
JPH0352211B2 true JPH0352211B2 (en) 1991-08-09

Family

ID=13226978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58063359A Granted JPS59188916A (en) 1983-04-11 1983-04-11 Correction of deflection distortion

Country Status (1)

Country Link
JP (1) JPS59188916A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045022A (en) * 1983-08-23 1985-03-11 Toshiba Corp Correction of height at lsi manufacturing device
JPS61129825A (en) * 1984-11-29 1986-06-17 Toshiba Mach Co Ltd Electron beam exposure equipment
JP2687256B2 (en) * 1991-03-26 1997-12-08 株式会社ソルテック X-ray mask making method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5367365A (en) * 1976-11-29 1978-06-15 Nippon Telegr & Teleph Corp <Ntt> Correcting method for beam position
JPS5498577A (en) * 1978-01-20 1979-08-03 Nippon Telegr & Teleph Corp <Ntt> Correction method for electron beam scanning position

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5380368U (en) * 1976-12-06 1978-07-04
JPS55167657U (en) * 1979-05-18 1980-12-02

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5367365A (en) * 1976-11-29 1978-06-15 Nippon Telegr & Teleph Corp <Ntt> Correcting method for beam position
JPS5498577A (en) * 1978-01-20 1979-08-03 Nippon Telegr & Teleph Corp <Ntt> Correction method for electron beam scanning position

Also Published As

Publication number Publication date
JPS59188916A (en) 1984-10-26

Similar Documents

Publication Publication Date Title
USRE45245E1 (en) Apparatus and methods for determining overlay of structures having rotational or mirror symmetry
TWI776163B (en) Method, computer program product, semiconductor inspection device of obtaining a 3d volume image of an integrated semiconductor sample
JP3971937B2 (en) Exposure condition monitoring method and apparatus, and semiconductor device manufacturing method
US5627624A (en) Integrated circuit test reticle and alignment mark optimization method
US6549648B1 (en) Method for determining a position of a structural element on a substrate
US8179536B2 (en) Measurement of overlay offset in semiconductor processing
EP0114517A1 (en) Mark position detecting method and apparatus
JP2008145439A (en) Improvement in shape accuracy using new calibration method
EP0947828B1 (en) Method and apparatus for improved inspection measurements
KR102496148B1 (en) Method for semiconductor wafer inspection and system thereof
JP2001189263A (en) Method of inspecting misalignment and charge beam exposure method
KR101962830B1 (en) Pre-alignment measuring device and method
JPH0352211B2 (en)
JPH0897114A (en) Alignment method
CN100380234C (en) Method of measuring critical dimension and overlay in single step
US5285075A (en) Electron beam lithography method
US5972772A (en) Electron beam drawing process
US6337486B2 (en) Electron beam drawing process and electron beam drawing apparatus
US6127683A (en) Electron beam drawing apparatus
JPH0210819A (en) Inspection method of pattern defect
JPH09251945A (en) Pattern for superimposing accuracy control and superimposing accuracy control method using it
JP2825875B2 (en) Dimension inspection method
KR910000607B1 (en) Target keys for wafer probe alignment
Groves Statistics of pattern placement errors in lithography
JPH0547648A (en) Setting method for height of irradiating position of electron beam exposure apparatus