JPH0352198B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a dimming control device that is suitably used in a dimming device that controls lighting modes of various types of lighting.

BACKGROUND TECHNOLOGY On theater stages, television studios, etc., multiple lighting lights are used to create performances by changing their brightness and color. Normally, these illumination lights are controlled using a control console called a dimming control console in which a plurality of sliding faders are arranged.
That is, each fader is connected one-to-one with a dimmer that controls the dimming of the illumination lamp, and by operating this fader, the brightness of the illumination lamp, etc. can be controlled.

The lighting condition created by operating each fader is called a scene, and in recent years, this scene has been numbered and memorized in advance during rehearsals, so that during the actual performance it can be called up and played back with a single number (memory format). (light control console), add one more scene to the above scene
By assigning it to a book's fader and allowing scenes to be played just by operating that fader (so-called submaster function, such a fader is called a submaster fader), increasingly complex lighting effects can be realized with ease. It has been devised.

FIG. 5 shows a configuration example of a conventional light control device 1 that realizes the above-mentioned submaster function, and FIG. 6 shows a processing flowchart. As shown in FIG. 5, the conventional light control device 1 includes n submaster faders F1 to Fn (indicated by reference numeral F when collectively referred to as n submaster faders) and a digital signal.
Mij (i=1, 2,..., m, j=1, 2,...,
storage means 2 having elements n) and analog signals from submaster faders F1 to Fn as analog/
It consists of an analog/digital converter (hereinafter referred to as a converter) 3 for digital conversion and a central processing unit (CPU) 4. The necessary digital processing is
The purpose is to execute the operation expressed by the first equation below.

Pi=MAX (Mij×Fj) ...(1) (i=1~m, j=1~n) Mij: Channel of the jth submaster feeder Fj: Channel of the jth submaster feeder Fj: Channel of the jth submaster feeder F Data In this conventional example, first, in steps n1 and n2, addresses i and j of the storage means 2 are initialized to 1 and 1, and in step n3, each channel (operation status of submaster fader F for each scene) is initialized for each channel CH1 to m. The storage element Mij of is multiplied by the analog output Fj from the submaster feeder Fj (which is taken into the central processing unit 5 via the converter 4 and is indicated by the same reference numeral as the submaster feeder F), and the result is It is temporarily stored in a variable Qij assigned to the storage means 2. As shown in steps n4 and n5, the storage means 2
The process is performed for the entire one-row storage element array, and further, as shown in steps n6 and n7, is performed for all the storage elements of the storage means 2.

Next, as shown in steps n8 to n15 in FIG. 6, the maximum value is searched for each channel CHi, and finally the output Pi of the channel CHi is obtained. Such conventional examples have the following drawbacks.

Regarding the processing time required to execute the above processing, the burden placed on the software is large (especially when the number of storage elements in the storage means 2 increases).

A relatively expensive analog/digital converter 2 must be used.

When the number of submaster faders F increases, the fader inputs can be connected to an analog multiplexer (not shown) to capture the fader level F.
This requires more complex control and faster analog multiplexers.

An example of a configuration that solves these problems is Japanese Patent Application No. 61-013299 filed by the present applicant. In this example configuration, the central processing unit (CPU)
Although it is effective in large-scale systems (systems with hundreds to thousands of scenes) with high capacity, it is effective in small-scale systems (systems with a high submaster fader
In systems with more than 10 channels, and the number of channels is in the range of tens to 100 channels, incorporating multipliers, comparators, multiple memories, analog/digital converters, etc. into the system will lead to increased costs and larger size. , cannot be said to be suitable.

Purpose The purpose of the present invention is to solve the above-mentioned technical problems,
An object of the present invention is to provide a dimming control device that can perform high-speed arithmetic processing with a simplified circuit configuration.

Structure of the Invention The structure of the present invention to achieve the above object includes a plurality of faders F1 to Fn that each generate analog fader signals, and a multiplexer that switches and outputs the fader signals from each fader F1 to Fn. 15, a storage unit 13 that stores a plurality of data strings Mij (i=1 to m, j=1 to n) corresponding to each of the feeders F1 to Fn, and feeders F1 to Fn from the multiplexer 15.
A digital/analog converter 12 that performs digital/analog conversion by multiplying each fader signal by a data string M1j to Mmj (j=1 to n) from the storage unit 13; and an output from the digital/analog converter 12. A dimming device characterized in that it includes a peak hold circuit 23 that holds and outputs the maximum level of a signal, and a sample hold circuit 16 that receives the maximum level signal from the peak hold circuit 23, holds it, and outputs it. It is a control device.

According to the present invention, the feeders F1 to
The fader signal, which is an analog quantity from Fn, is input as a reference voltage to the digital/analog converter 12, and the data string Mij from the storage unit 13 and the fader signals F1 to Fn are multiplied according to this input level. and digital/analog conversion. Also, regarding this calculation result, the peak hold circuit 23 calculates the maximum value. In this way, in the present invention, there is no need to provide an analog/digital converter for converting a fader signal, which is an analog quantity, into a digital signal, and the circuit configuration is simplified. Further, a control for reading the fader signals F1 to Fn via the analog/digital converter;
The arithmetic processing performed between the read result and the data string Mij in the storage unit 13 is performed by hardware. This greatly speeds up arithmetic processing. Furthermore, software for performing the above-mentioned reading processing and arithmetic processing is unnecessary, and the amount of software used in the present invention can be reduced.

Embodiment FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention. The basic configuration of this embodiment will be explained with reference to FIG. The light control device 11 of this embodiment, which is a light control device, is provided with a plurality of faders F1, F2, . The analog output of each fader F is connected to a digital/analog converter (hereinafter referred to as
A digital signal is inputted to a converter (abbreviated as a converter) 12, and a digital signal from a storage section 13 implemented by, for example, a RAM (random access memory) is given to the converter 12.

The output from the converter 12 is sent to the maximum value detection holding unit 1
4 is input. From this maximum value detection holding unit 14, peak data Pi, which is the maximum value as described later, is obtained.
is obtained.

FIG. 2 is a block diagram showing an example of the structure of the light control device 11 shown in FIG. A configuration example of the light control device 11 will be described with reference to FIG. 2. Light control device 11
includes a plurality of faders (hereinafter referred to as submaster faders) F1 to Fn as described above, and their outputs are switched and derived by an analog multiplexer 15 as described later. Also,
The maximum value detection and holding section 14 is realized by including a peak hold circuit 23.
A sample-and-hold circuit 16 is provided which receives an output signal f from the circuit and outputs peak data Pi (i=1 to m) in parallel as described later. Also,
An address generation section 17 is provided for generating an address signal in the analog multiplexer 15, the storage section 3, the sample hold circuit 16, etc., and the address signal is led out to an address bus 18.

FIG. 3 is a circuit diagram showing an example of the configuration of the converter 12 shown in the second figure. The configuration of the converter 12 will be described with reference to FIG. 3. The storage unit 3 mentioned above
The data bus 19 from which digital signals are derived from the converter 12 includes, for example, j-bit (j=n in this embodiment) parallel lines l1, l2, l3, . . .
Consists of lj. The analog signal V _REF output from the analog multiplexer 15 is sent to n switching means S via a resistor circuit 20 as shown in the third figure.
1, S2, S3, . Each of the switching means S1 to Sn is controlled to open or close by a high level or low level signal via the lines l1 to ln, and a desired analog voltage is output from the output terminals 21 and 22 according to the resistance value of the resistance circuit 20 obtained. I get the output.

FIG. 4 is a timing chart explaining the operation of the light control device 11 shown in FIGS. 2 and 3. FIG. The operation of the light control device 11 will be explained with reference to FIGS. 2 to 4.

The address generating section 7 generates an address signal a shown in FIG. 4, a peak hold circuit reset signal e shown in FIG. 5, and a sample hold signal g shown in FIG. 7 at the timing shown in FIG. First, when the address is "0", the analog multiplexer 15
selects the submaster fader F1 and applies the fader signal F1 to the reference voltage input terminal V _REF of the converter 12 as shown in FIG. 4. At this time, data M11 is output from the storage section 13 and is also applied to the data input terminal D _IN of the converter 12 as shown in FIG. 3. The converter 12 converts the data on the data input terminal D _IN from digital to analog according to the magnitude of the reference voltage input V _REF = Fj (j = 1 to n), and outputs the result d to the fourth output terminal Vo. The voltage is output as shown in FIG.

Thereafter, in the same manner, the submaster faders F2, F
3, . . . , Fn are selected, and at the same time, the stored data M12, M13, . and the fourth
A voltage output d as shown in FIG. 4 is obtained. The peak hold circuit 23 holds only the largest voltage among the voltage outputs d, and obtains an output f having a waveform as shown in FIG. 4. Sample hold circuit 16
samples/holds this waveform at the timing of the sample/hold signal g shown in FIG.
Obtain the final output of channel CH1. The peak hold circuit 16 then uses the fourth
It is reset to the "0" level by the reset signal e in FIG. 5, and prepares for processing regarding the next channel CH2. Similar processing is performed in the storage unit 13 below.
This is performed along the column direction for each row-direction array data column.

As described above, according to the present embodiment, when storing the output level Fi of the submaster fader Fi, as long as the channel CHi level is written so as to be arranged in the storage section 13 shown in FIG. It is possible to perform calculations to obtain the final output Pi of each channel CHi shown in the first equation above only by digital/analog conversion processing without placing any burden on software.

As described above, according to the embodiment described above, the outputs of the submaster faders F1 to Fn are directly transmitted to the converter 12.
was connected to the V _REF (reference voltage) input of the converter 12, and the input data to the converter 12 was converted from digital to analog according to this input level. Therefore, there is no need for the central processing unit (not shown) that controls these operations to read the level of the submaster fader F, and the analog/digital converter 3 shown in the prior art is not required. Multiplication processing by software can be omitted.

As described above, this embodiment eliminates the need for the analog/digital converter 3 described in the prior art, and also has a configuration that temporarily stores the multiplication results when performing the arithmetic processing of the first equation using software. This also eliminates the need for the circuit configuration. Further, the multiplication process and the maximum value calculation process of the first equation are performed by hardware,
Furthermore, by connecting the analog fader signals from each of the faders F1 to Fn to the digital voltage input of the digital/analog converter, analog/digital conversion processing is performed while performing multiplication operations.

Therefore, the processing in which a microprocessor or the like reads the analog output of each fader F1 to Fn via an analog/digital converter as in the prior art, and the arithmetic processing performed on the read results are performed by hardware. I am trying to do it at Therefore, software related to the above processing is not required, and the amount of software used in this embodiment can be reduced, and the calculation processing speed can be significantly increased.

As described above, the present invention is particularly effective in systems that are small-scale, have low data processing capabilities, and handle fader signals as analog values.

Effects According to the present invention, the fader signals, which are analog quantities from the faders F1 to Fn, are input as the reference voltage of the digital/analog converter 12, and the data string from the storage unit 13 is changed in accordance with this input level.
Multiplication is performed between Mij and fader signals F1 to Fn, and digital/analog conversion is performed. Also, regarding this calculation result, the peak hold circuit 23
The maximum value is calculated by . In this way, in the present invention, there is no need to provide an analog/digital converter for converting a fader signal, which is an analog quantity, into a digital signal, and the circuit configuration is simplified. Further, the control for reading the fader signals F1 to Fn through the analog/digital converter and the arithmetic processing performed between the read results and the data string Mij in the storage section 13 are performed by hardware. There is. This greatly speeds up arithmetic processing. Furthermore, software for performing the above-mentioned reading processing and arithmetic processing is unnecessary, and the amount of software used in the present invention can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a light control device 11 according to an embodiment of the present invention, and FIG. 4 is a timing chart showing the operation of the light control device 11, FIG. 5 is a block diagram of the light control device 1 of the prior art, and FIG. 6 is a flow chart showing the operation of the light control device 1. DESCRIPTION OF SYMBOLS 11... Light control device, 12... Digital/analog converter, 13... Storage section, 14... Maximum value detection holding section, 16... Sample hold circuit, 23...
...Peak hold circuit, 24...Diode, 2
5...Voltage OR circuit, F1~Fn...Submaster fader, Pi...Peak data.

Claims (1)

[Claims] 1. A plurality of faders F1 to Fn each generating an analog fader signal, a multiplexer 15 that switches and outputs the fader signal from each fader F1 to Fn, and a multiplexer 15 facing each fader F1 to Fn. A storage unit 13 that stores a plurality of data strings Mij (i=1 to m, j=1 to n), and faders F1 to Fn from the multiplexer 15
A digital/analog converter 12 that performs digital/analog conversion by multiplying each fader signal by a data string M1j to Mmj (j=1 to n) from the storage unit 13; and an output from the digital/analog converter 12. A dimming device characterized in that it includes a peak hold circuit 23 that holds and outputs the maximum level of a signal, and a sample hold circuit 16 that receives the maximum level signal from the peak hold circuit 23, holds it, and outputs it. Control device.