JPH0352051A - Image dam transfer interface circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of the whole system by enabling one interface circuit to perform input/output control over both a scanner unit and a printer unit and shorten the occupation time of a system bus for image transfer processing as much as possible. CONSTITUTION:This circuit consists of a scanner/printer interface part 9, a FIFO memory 8, and a control circuit 5. Interface processing for DMA transfer of image data is performed between a page memory 11 connected to a system bus 10 and an image input/output device such as a scanner unit 13 and a printer unit 14. At this time, one interface circuit performs transfer between two image units, i.e. the scanner unit 13 and printer unit 14. Further, the image data are buffered, line by line. Consequently, the transfer of the system bus side is performed at the highest speed without being affected by the transfer rate of the input/output device and the occupation rate of the system bus for the image transfer processing is minimized.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a computer system that performs image processing, and particularly to an image input/output device and a page memory (video RA
The present invention relates to an image DMA transfer interface that efficiently exchanges image data between M) via a system bus using a DMA (direct memory access) method.

[Conventional technology]

The data transfer control method in the input/output control section of a conventional computer system uses a dedicated controller etc. to transfer data independently of the operation of the processor.
M A (Direct Me＋＊ory Ac
There is a program control method in which data is transferred one byte (or one word) at a time under program control on a processor.

In the DMA system, a DMA control circuit requests a bus from a processor, and when the request is accepted, the bus is occupied and data is transferred.

Furthermore, in order to perform image processing, characters and figures are stored in units of pixels (pixel+pIXel), which requires a large capacity memory. Therefore, generally, the main memory is not shared, and a page memory is used to hold image data.

In computer systems that perform image processing, when a large amount of image data is read into a personal computer or workstation system at high speed using a laser printer, image scanner, etc., the system bus and processor are occupied for a long time, causing system problems. This will reduce the overall throughput.

Currently, in order to avoid a decrease in the throughput of the system, data transfer between the page memory and the input/output device is performed using the DMA method, as described above.

Regarding the transfer of these image data, please refer to Volume 5 of "Electronic Information and Communication Handbook" edited by the Institute of Electronics, Information and Communication Engineers.
It is detailed in Division 4.3, Volume 25, Section 2 2.4, and Volume 25, Division 6, 8.2 and 8.3.

[Problems to be Solved by the Invention] In conventional Ii image processing devices and computer devices, when reading information from a device that handles a large amount of data such as image data into the system, the system bus and CPU length In order to avoid reducing the throughput of the entire system due to time occupancy, data is transferred using the DMA method.

However, in the conventional image data transfer method using the DMA transfer method, the scanner interface is a circuit dedicated to the scanner interface, and the printer interface is a circuit dedicated to the scanner interface.
A dedicated circuit for the interface was used, resulting in a large circuit, and depending on the printer or scanner model, corresponding circuits were designed completely separately, resulting in a lot of waste.

In addition, each interface circuit has a partial read function.
However, since reading and processing of one page's worth of images is performed at once, the system bus is occupied for a long time, which further reduces system throughput.

The purpose of the present invention is to solve these problems of the conventional technology, to enable input/output control of both the scanner unit and the printer unit with a single interface circuit, and to minimize the time occupied by the system bus due to image transfer processing. Image D improves the throughput of the entire system.
An object of the present invention is to provide an MA transfer interface circuit.

[Means to solve the problem]

(F3) In order to achieve the above object, the image DMA of the present invention
The transfer interface circuit includes a system bus that is shared by multiple processors, a bus control circuit that arbitrates the right to use the system bus, and a page memory that is connected to the system bus. In image processing devices and computer devices that transfer image data by DMA between an image data input/output device such as an image scanner and a page printer and a page memory, the image processing device and the computer device are connected directly to the input/output device, and are connected line by line, and A scanner/printer interface unit that performs pixel-by-pixel synchronization; A counter that counts the lines processed by the IFO memory, a counter that counts the number of bytes transferred between the system bus and input/output devices, an address counter for the page memory, and a sequencer that controls the sequence between each control signal. The present invention is characterized in that it is provided with a control circuit that controls the operation timing of the FIFO memory and the access timing signal of the system bus. (b) The counter that counts the number of transferred bytes of the control circuit is set separately to the counter that counts the number of transferred bytes on the input/output device side and the counter that counts the number of transferred bytes on the system bus side, and Another feature is that only a partial rectangular area of one page of data is transferred between system buses.

[Operation] In the present invention, the scanner/printer interface section is directly connected to the input/output device, and
Then, image data is read from the scanner unit pixel by pixel and transmitted to the FIFO memory, or conversely, image data is read from the page memory via the FIFO memory and output to the printer unit.

The FIFO memory writes and reads data for I lines between the system bus and the scanner/printer interface using first-in, first-out processing in synchronization with the operation of the scanner/printer interface circuit.

The control circuit controls the operation timing of the FIFO memory and the access timing signal of the system bus, and also controls the acquisition of bus rights to the system bus.

The above scanner/printer interface section, FIFO
The image DMA transfer interface circuit, which is composed of a (FIFO) memory and a control circuit, performs DMA of image data between the page memory connected to the system bus and image input/output devices such as scanner units and printer units. Performs transfer interface processing.

At this time, one interface circuit transfers image data from both the scanner unit and the printer unit. Furthermore, this image DMA transfer interface circuit!
By buffering each line, data is transferred at the highest speed without being affected by the transfer rate of the input/output device, minimizing system bus occupancy due to image transfer processing. Keep it to In addition, by setting the counters on the system bus side and the input/output device side separately in the control circuit, it is possible to transfer only a partial rectangular area of one page of data on the input/output device side between the system buses. is possible.

〔Example】

Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a DMA transfer control system to which the present invention is applied.

The interface board 12 according to the present invention includes a bus control section 11CPU2, an address decoder 3, a driver 4, a control section 5, a driver/receiver 6, a byte conversion section 7, a FIF○8, and a scanner/printer interface 9.
It is made up of.

It is connected to a system bus 10 by a bus control section 1, a driver 4, and a driver/receiver 6, and is further connected to a page memory 11 via the system bus 10. Further, the PIFO 8, which inputs and outputs scanner image data of the scanner unit 13 and printer image data of the printer unit l4 via the scanner/printer interface 9, performs first-in, first-out processing of information, and connects the system bus 10, the scanner unit l3, and Transfers image data from printer unit l4.

This interface board 12 has two operating modes: scanner mode and printer mode. In the scanner mode, the scanner image data from the scanner unit 13 is read into the PIFO 8 via the scanner/printer interface 9, and the control unit 5
DMA transfer is performed onto the page memory ll of another board on the system bus 10 under the control of the . Conversely, in the print mode, image data from the page memory 11 on the system bus 10 is sent to the control unit 5.
Under the control of , the data is read into the FIF○8 and transferred to the printer unit 14 via the scanner/printer interface 9. In the embodiment shown in FIG. 1, the PIFO 8 is 8 bits wide and the system bus 10 is 16 bits wide, and the byte converter 7 matches the bit widths.

FIG. 2 is a block diagram showing the internal configuration of the control section 5 in FIG. 1.

Hereinafter, the control section 5 will be referred to as (1) sequencer section, (2)
The explanation will be divided into three functional parts: the counter part and (3) other functional parts.

(1) Sequencer section The sequencer section consists of the following three parts, and
The state machines having respective functions include: a) DMA sequencer 22: Controls acquisition/release permission of bus rights.

b) Bus sequencer 21: page memory l1 and FIFO
C) Unit controller 23: Data transfer control between scanner unit 13 and printer unit 14 and PIFO 8. (2> Counter Section The following four counters are provided in this LSI.

a) Line counter 24: 16 bits b) Pixel counter 25 (scanner and printer unit side): 12 bits e) DMA counter 27 (system bus side): 12 bits d) Address counter 26: 23 bits The line counter 24 is used for transfer Count the number of lines. The pixel counter 25 counts the number of bits of data transfer between the FIFO 8 and the scanner unit l3 and printer unit l4 in FIG. 1, and outputs a data transfer end signal LENDO for one line.

DMA counter 27 is connected to FIFO 8 and system bus 10.
The number of data transfer bits during this period is counted, and a data transfer end signal for one line (hereinafter referred to as LENDV) is output.

Address counter 26 outputs an address for system bus access. Counts up every time the system bus is accessed, during DMA and onboard C
Used when inputting the PU2 access signal (hereinafter referred to as CPUDSN). (3) It also has an internal address/data bus 28 for access from the onboard CPU 2. Note that the address in this embodiment includes only the lower 8 bits. Further, the control unit 5 has a command register 30, a status register 31, an address latch 32 and an address decoder circuit 29 for outputting a select signal for an internal register of each counter or the like.

Now, the operation of the control section 5 of this embodiment will be explained in more detail below. The control unit 5 of this embodiment controls each internal register as CP.
11Fl is controlled by being read/written by U2. Figure 3 is. 2 is a block diagram showing the connection between a CPU 2 and a control unit 5. FIG. A read (hereinafter referred to as DRN) signal terminal and a write (hereinafter referred to as WRN) signal terminal of the CPU 2 are directly connected to the address decoder 29 of the control unit 5 in FIG.
Furthermore, DRN signal and Wf? ．． The N signal is connected to each internal register in FIG. The address latch enable (hereinafter referred to as ALE) signal terminal of the CPU 2 is directly connected to the address latch of the control unit 5 shown in FIG. 2, and at the same time is connected to the address latch in the address decoder 3 shown in FIG. The IO/memory (hereinafter referred to as 10/MN) signal terminal of the CPU 2 is connected to the address decoder 3 shown in FIG.
~7) is decoded, and the chip select (hereinafter referred to as CSN) is performed.
) signal is output to the CSN terminal of the controller 5 in Figure 2. These signals (ALE%RDN, WRN
%CSN) is the address latch 32 in the controller 5.
Alternatively, it is output via the address decoder 29 as a select signal for internal registers such as each counter. Fourth
The figure is a timing chart showing the timing of the operation of the CPU 2 in FIG. 3 to control the control section 5. The data bus is latched by the rise and fall of the ALE signal and the rise of the IO/MN signal in cycle TI of CPU CLOCK,
) is confirmed. In the next cycles T2 and T3, data is read or written to the internal register. Furthermore, in the scanner mode, the control unit 5 controls the image output from the scanner unit 13 side in synchronization with a connection confirmation (hereinafter referred to as LINE) signal or a unit clock (hereinafter referred to as tJcLK) signal from the scanner/printer interface 9. Data as PIFO
8, and in print mode, conversely, PIF
Generates a timing signal to send data from O8 to the printer unit 14 side. The generation of this timing signal is mainly performed by the unit controller 23.
The operation of the unit controller 23 will be explained using FIG. FIG. 5 is a state transition diagram showing the timing signal generation operation of the unit controller 23.

In the state transition diagrams below, circles of Sn represent each state, and signal names without underlining within the circles represent output signals from the sequencer in each state.

A signal with N at the end of the signal name indicates low active. The signal name written next to the arrow indicates the condition of the input signal.
The arrow indicates the transition when that condition is met.

! represents NOT1& represents AND. In addition, transitions without a conditional input signal can be caused by external (or internal) CP
The transition occurs in one cycle of the system clock (hereinafter referred to as CLK) from U2).Furthermore, [0 0 0
01 and [0 0] indicate the bit states of each flip-flop representing each state. For example, S1[0100],
If it is described as [01], the S1 state indicates that only the second flip-flop among the four or 21m flip-flops is in the High state, and in reality, the state of each flip-flop is By reading, you can determine each state. Now, gate array reset (hereinafter referred to as G) from external or internal CPU2
The unit controller 23 enters the idle state (SO state, [1 1
F). Start from command register 30 (hereinafter referred to as ST)
It is activated by the signal (written as ART), and furthermore, the DM
A page indicating that operation is possible from the A sequencer 22 (hereinafter P
If the input of the signal (written as AGE) is confirmed, the state changes to the S1 state ([1 0]). In the S1 state ([1 01), the LINE signal from the scanner/printer interface 9 or the DMA sequencer 22
Waits for the input of a signal (hereinafter referred to as PAGE) indicating that it is ready for operation. When the LINE signal or PAGE signal is input, the unit controller 23 sends the FIF○/unit reset (hereinafter referred to as FRSTU) signal to the pixel counter 27, which is the source of the signal for resetting the PIFO 8 in FIG. A data transfer enable signal (hereinafter referred to as DTEN) indicating that data transfer operation is possible is output to the scanner/printer interface 9.
Waits for input of UCLK signal from scanner/printer interface 9 (state 32, [0 01). U.C.
When the LK signal is input, the output of the FRSTU signal is stopped,
Outputs only the DTEN signal (S3 state, [011
). In this state, data is transferred as appropriate. When the data transfer is completed, a line transfer end (hereinafter referred to as LENDU) signal is input from the pixel counter 25, and
Transition to state.

FIG. 6 shows the P
It is a block diagram showing the operation and configuration of IFO8.

In the scanner mode, this UCLK signal is outputted to the PIFO 8 as a write clock (hereinafter referred to as WCK) signal via the PIFO R/W timing section 33 in the control section S.

On the other hand, in the print mode, it is similarly output as a readout glock (hereinafter referred to as RCK) signal.

PIFO depending on the state of the mode (hereinafter referred to as MODE) signal that indicates whether it is a printer mode that uses a printer unit or a scanner mode that uses a scanner unit.
The operating force direction of 8 has been switched.

That is, the control section 5 controls the scanner unit l3.
In the scanner mode, the image data from the scanner unit 13 side is sent to P in synchronization with the LINE signal or UCLK signal from outside the printer unit 14, etc.
In the print mode, data is read into the IFO 8 and, conversely, a timing signal is generated to send the data from the PI FO 8 to the printer unit l4 side. Generation of this timing signal is mainly caused by the unit controller 23. That is, the unit controller 23 in FIG.
By outputting the FIFO R/W switching unit 33 to the RSTRN signal and RCK signal,
Switch to RSTWN signal and WCK signal. Note that this switching operation changes the operating direction of the single FIFO 8. Furthermore, FIG. 7 is a timing chart showing the operation timing of each signal in FIG.

By inputting the LINE signal shown in Figure 5, the RSTRN signal is output in printer mode, and the RSTRN signal is output in scanner mode.
The STWN signal is output, the FIF08 is reset, and the l-line transfer operation is started. Also, each signal is C
Operates based on the LK signal. Furthermore, the UCLK signal acts as a strobe signal for the scanner unit 13 and printer unit 14 to read/write data in the PIFO 8, and as shown in FIG. An RCK signal is generated in the printer mode, and a WCK signal is generated in the scanner mode.

This completes the explanation of the operation of the unit controller 23 in the control section 5 in FIG. 2.

Next, in FIG. 1, the control s5 performs DMA transfer between the system bus lO and the FIF○8 on a line-by-line basis. The second controlling acquisition and abandonment
The DMA sequencer 22 shown in the figure will be described first, and then the path sequencer 2l that generates access timing signals for the system bus 10 and the FIF 8 will be described.

FIG. 8 is a state transition diagram showing the state transition of the DMA sequencer 22 in the control section 5 of FIG.

The DMA sequencer 22 enters the idle state of the SO state ([1 1 1 1) in response to input of the GRST signal from the external or internal CPU 2 in FIG.

2nd rJ! START from command register 30 of J
The signal activates the DMA sequencer 22, and the second
The page starts from line counter 24 in the figure (hereinafter P
Wait for the LINE signal (written as STRT) and the LINE signal from the scanner/printer units 13 and 14 in Figure 1.
If these two signals are input together, a bus request (hereinafter referred to as BRN) signal is output (S2 state, [0100]). When a path grant use permission (hereinafter referred to as LBGN) signal is returned from the arbiter of the system bus 10 (not shown), it negates the BRN signal, sends out a DMA signal, and activates the path sequencer 2l (S3 State, [0101co).

The transfer for l lines is completed, and the DMA counter 27 indicates L.
When the ENDV (end of line transfer) signal is input, the DM
A transfer is terminated (S4 state, [0001]). Thereafter, it waits for the LINE signal to be input (S5 state, [00001), and repeats the DMA sequence for the next line in the same way.

However, in printer mode, if the DoUBLE signal from the command register 30 in FIG. 2 is input in the S4 state (S6 state, [0011]), wait one more line (S7 state, [0010 command]) ), performs the following DMA sequence. In this way, the DOUBLE signal causes DMA transfer to be performed every l line of the line signal from the printer unit 14 in FIG. 1, and the same data is transferred to the printer unit l4 every two lines. ．． still. 1st
For PIFO8 in the figure, it is necessary to select one that can be transmitted. Also, the 2x magnification function in the sub-scanning direction. Although this is achieved, the control unit 5 does not support expansion in the main scanning line direction.

If a page transfer end (hereinafter referred to as PEND) signal is input from the line counter 24 in FIG. 2 in state 84 in FIG. Status (S
Return to o state, [1l1l]). Next, the DMA sequencer 22 performs the steps 1 to 2 in FIG.
PA to the task register 31 and the unit controller 23
Sends GE signal. This signal is in the idle state (So
It is Low in state [11111), and High during the DMA transfer sequence for one page (states other than SO).

Additionally, the DMA sequencer 22 issues a bus release permission (hereinafter referred to as R).
ELENN) signal is output. This signal is BR
During the period from the bus request by sending the N signal to the end of the DMA transfer (S2, 33 states), RELENN=H.
In any other state, RELENN=Low indicates that bus release is permitted. Note that this signal can be used externally for bus control. Next, the operation of controlling the exchange of signals between the system bus 10 and the FIFO 8 in FIG. 1 by the path sequencer 2l in the controller 5 in FIG. 2 will be explained using FIGS. 9 to 12. First, FIG. 9 is a block diagram showing the configuration of the signal connection between the bus control unit 1 and the FIFO 8 in FIG. 1. Bus control unit 1, control unit 5, byte conversion unit 7, F
It is composed of an IFO 8, a converter 91, and a scanner data control section 92.

As shown in FIG. 9, the control section 5 of this embodiment
In this case, control of data transfer between the system bus 10 and the FIFO 8 shown in FIG. 1 is performed by each signal generated by the path sequencer 2l, as described above. That is, the path sequencer 2l transmits image data from the system bus 10 in the first [ffl] to the FI by the MODE signal.
Load it into FO8 (print mode) or vice versa
Generates a control timing signal for transfer from the FO 8 to the system path 10 (scanner mode).

Furthermore, although the system bus 1o in FIG. 1 has a width of 16 bits, the FrFO8 has a width of 8 bits, so the conversion between them is performed via the byte converter 7, and the low byte is transferred to the PIFO8 first. Or start reading. The operation of the path sequencer 2l will be explained in more detail below based on FIG. When the DMA signal from the DMA sequencer 22 in FIG. 2 and the MODE signal from the scanner/printer interface 9 in FIG. 1 are input to the path sequencer 21 in FIG.
Output the signal to PIFO8. In actual operation, the path sequencer 2l inside the controller 5 receives the DMA signal and the MODE signal, outputs the VCLK signal, and outputs the VCLK signal.
The cLK signal is converted to the RCK signal or WCK signal via the 71 PIFO R/W switching unit 33 in FIG.
It is output to FIF○8.

That is, the scanner/printer interface 9 in FIG.
If the MODE signal from
The signal to FO8 is the WCK signal.

In the printer mode, the controller 5
A DMA data strobe (DMADSN
) signal to the bus control unit 1, and the bus control unit l outputs the DM
Based on the ADSN signal, system bus 1 in Figure 1
Outputs a data strobe (DSN) signal to 0. At the same time, the DMADSN signal is also output to the byte converter 7 and used as a strobe signal, and the byte converter 7
Preparation is made for reading data from the system bus 10 in FIG.

When a data acknowledgment (hereinafter referred to as DTACK) indicating permission to use DMA is input via the system bus lO in FIG.
A line data acknowledge (hereinafter referred to as LDTACKN) signal is sent to. Upon receiving the LDTACKN signal, the controller 5 first outputs a low byte read (hereinafter referred to as LBRN) signal to the byte converter 7, and then,
In place of the LBRN signal, a high byte read (hereinafter referred to as H
BRN) Outputs a signal. The byte converter 7 receives the LBRN signal, first takes in the low byte (8 bits) of the first 16 bits of data from the system bus 10, sends it to the PIFO 8, then receives the HBRN signal, The high byte (8 bits) of the first 16 bits of data from the system bus IO is taken in and sent to PIFO8.

This operation is repeated in accordance with the WCK (VCLK) signal, and the second and third data from the system bus IO are transferred one after another.

Incidentally, at this time, the scanner data control section 92 controls the converter 9.
1, it is turned off based on the MODE signal, so
The connection with the scanner unit l3 in FIG. 1 is off.

In the scanner mode, the scanner data control unit 9
2 turns on, and the RCK (VCLK) signal becomes High/
Based on the Low operation, each byte is sent to the byte converter 7 via FIF○8. In the byte converter 7,
Low byte light from controller 5 (hereinafter referred to as LBWN)
The high byte write (hereinafter referred to as HBWN) signal is used. In synchronization with the HBWN signal, the controller 5 performs a data strobe/write (
Output the signal (hereinafter referred to as DSWN) to the byte converter 7,
Based on this DSWN signal, the low byte and high byte taken into the byte converter 7 are put together as 16-bit information on the system bus 10. Next, the controller 5 sends out the DMADSN signal and
Transfer data to the system bus 10 in sequence while checking the input of the DTAKN signal. In addition, the master strobe output from the controller 5 (
The signal (hereinafter referred to as MASN) is also sent to the address counter 26 in FIG. 2, and at the same time, is sent to the system bus 10 as an address strobe (hereinafter referred to as AS*) signal via the bus control section l. This signal synchronizes the data transfer of the DMA address buses (VA23-1).

FIG. 10 is a state transition diagram showing the state transition of the path sequencer 2l in the controller 5 in FIGS. 9 and 2. The path sequencer 21 enters an idle state (S
o state, [1111]), waits for a DMA signal from the DMA sequencer 22 in FIG. When the DMA signal from the DMA sequencer 22 in FIG. 2 is input, the path sequencer 21 waits for the MODE signal from the scanner/printer interface 9 in FIG. 1 (S6 state. [1110]). When the MODE signal is input, the path sequencer 2l outputs V
CLK (PIFO R/W switching section 33 in Figure 2)
A signal (which becomes the RC:K/WCK signal) is output to the PIFO 8 in FIG.

If the input MODE signal is High, it becomes the scanner mode (S5 state, [1100]), and conversely,
If the MODE signal is Low, the printer mode is entered (Sl state, [0010]). In the 31st state in the printer mode, the DMA D S N signal is output to the bus control unit l and the byte conversion unit 7 in FIG.
The STVN signal is output to the FIFO 8 (inputted to the FIFO 8 as the R S TWN signal via the PIFO R/W switching unit 33 in FIG. 2), and the VC
The LK (WCL) signal also continues to be output.

When the LDTAKN signal from the bus control section 1 in FIG. 9 is input, data transfer from the system bus 10 is started (S2 state, [101O]). L.D.
While the TAKN signal is being input, the S3 state ([
1 0001 ) (at this time, the controller 5 in FIG. 9 exchanges the lower 8 bits of the system bus data). Next, if the LDTAKN signal turns off and the DMA signal is still input, the S4 state (
[00001) and Sl state ([0010])
(at this time, the upper 8 bits of system bus data are exchanged), and waits for the LDTAKN signal for the next system data exchange.

If in S3 state ([1000F), LDT
When the AKN signal is off and the DMA signal is also off, the state transitions to the S7 state ([10011) and then to the S8 state ([1011]), and the data transfer ends.
Returns to the idle state (So state, [1111]).Next, in the scanner mode, the path sequencer 2l changes from the S6 state ([1110]) to the 85 state ([
1100], and further, the S3 state ([1000
F), and depending on the states of the LDTAKN signal and the DMA signal, the transition is made in the order similar to the printer mode described above. Along with this state transition, the scanner unit 1 in FIG.
3 to the FIF08 is transferred to the system bus 10.

FIG. 1l is a timing chart showing the operation timing of each signal of the path sequencer 2l in the scanner mode.

CLK is a system clock from an external or internal CPU 2 in FIG. 1, and other signals are controlled using this clock as a reference. The path sequencer 2l, which was initially in the SO state, is in the D
Input of MA signal causes S6 state, and VCLK (
RCK) signal and LBWN signal, and the next MODE
When the signal is input, the S5 state is entered, and the scanner data from the scanner unit l3 in FIG. 1 is transferred to the PIF in FIG. 9.
Start capturing the low byte portion via O8, S
The 5th state is a state for only one CLK cycle, and immediately transitions to the 83rd state. In this state of 83,
If the LDTAKN signal is not input, it enters the S4 state, outputs the HBWN signal, and starts taking in high-byte data. At the same time, the DSWN signal and MA
The first data transfer is started via the SN signal DMA address bus, and transitions to the Sl state after one CLK cycle. At this time, the DMA D S N signal is output to the bus control circuit 1 shown in FIG. 9, and the response signal LDTAKN is awaited. 9th
When the LDTAKN signal is input through the bus control circuit 1 shown in the figure, the state becomes 82, and the second data acquisition starts, and the state changes to S3. Similarly, S
4, the image data of the PI FO 8 in FIG. 9 is transferred to the system bus IO in the cycles of the Sl, S2, and S3 states.

If the DMA signal and LDTAKN signal are not input in the S3 state, the S7, S8, and SO states are entered, and the data transfer ends.

Note that VCLK (RCK) i4H* is synchronized with the state transition change of the path sequencer 2l in FIG.
In synchronization with the rise of the CLK (RCK) signal, data is exchanged via the PIFO 8 in FIG. 9 in the scanner mode.

FIG. 12 is a timing chart showing the operation timing of each signal in the path sequencer 2l in the print mode.

Similar to the explanation in item 11, CLK is a system clock from the external or internal CPU 2 in FIG. 1, and other signals are controlled using this clock as a reference.

The path sequencer 2l, which was initially in the SO state, is in the D
When the MA signal is input, the VCLK (WCK) signal is output, and the S6 state is entered. Since the MODE signal is not input at this time (because it is Low), the DMADSN signal is output to the bus control unit l in FIG. 9 to notify the DMA request, and the FRSTVN (RSTWN) signal is output to Reset PIFO8 in the figure, output the MASN signal, and transition to the Sl state. In the St state, the LBRN signal is output to the byte converter 7 in FIG. 9 by inputting the LDTAKN signal, and the LDTAKN signal is input.
At the same time as the input of the DTAKN signal, transmission of the first low byte (8 bits) of data from the system bus IO in FIG. 9 to the FIF 8 in FIG. 9 is started.

The S2 state becomes the S3 state after one cycle of CLK, and the input state of the LDTAKN signal is checked again, and at the same time, the state of the DMA signal is also checked. The first data acquisition is completed, the LDTAKN signal is no longer input, and the DMA
If only a signal is input, the state transitions to S4.

At this time, the HBRN signal is output and the sending of the first high byte (8 bits) of data from the system bus 10 in FIG. 9 to the FIFO 8 in FIG. 9 is started.

The S4 state shifts to the S1 state after one cycle of CLK, at which time the DMADSN signal is output again to inquire about the transmission of the next data from the system bus IO in FIG.

Thereafter, data transfer is performed by repeating the transition to the S2, S3, and S4 states in the same manner.

If in the S3 state, the previous data has been fetched, the LDTAKN signal is no longer input, and the DMA signal is also not input, S7, S8, S
Transition to O state and end data transfer.

Here, the VCLK (WCK) signal is synchronized with the transition of each state, and data transfer is started at the falling edge of the VCLK (WCK) signal. As described above, the path sequencer 2l in FIG.
It also transfers data to and from the printer unit l4.

In this way, according to this embodiment, it is possible to control the input and output of both the scanner unit 13 and the printer unit l4 by one interface board l2, and further,
Since buffering is performed line by line, the time occupied by the system bus 10 due to processing such as image reading is minimized, and transfers on the system bus 10 side are performed regardless of the transfer rate on the input/output device side. This enables the highest speed transfer and minimizes bus occupancy.

Furthermore, in this embodiment, since the counter for the number of transferred bytes is independent between the input/output device side and the system bus 10 side, for example, when reading data from the scanner unit l3, Any rectangular area can be partially extracted from the read data and transferred to the page memory l1 on the system bus lO. Furthermore, in this embodiment, the PIFO 8 is 8 bits wide and the system bus 10 is 16 bits wide, and the bit widths are matched by the byte converter 7, but in general,
Since the interface methods of scanner units and printer units differ depending on the model (for example, bit width and signal level differ), if a circuit that absorbs these differences is designed for each scanner unit or printer unit,
The control unit 5 of this embodiment can be used with any scanner unit or printer unit.

In this embodiment, the control section 5 is an LSI such as a gate array, and by having the data path part outside the LSI without putting it inside the LSI, the data path can be doubled, tripled, etc.・Increase the width like this,
Furthermore, since the path occupation time can be reduced, it is possible to handle large amounts of data transfer at high speed.

〔Effect of the invention〕

According to the present invention, it is possible to control the input and output of both a scanner and a printer using a single interface circuit, and furthermore, it is possible to minimize the time occupied by the system bus due to image transfer processing, thereby improving the throughput of the entire system. It is possible.

[Brief explanation of drawings]

The drawings show embodiments of the present invention; FIG. 1 is a block diagram showing the configuration of a DMA transfer control system to which the present invention is applied;
The figure is a block diagram showing the internal configuration of the control section 5 in FIG. 1, FIG. 3 is a block diagram showing the connection between the CPU and the internal register (CDMAC) in the control section 5 in FIG. 1, and FIG. 3 is a timing chart showing the operation timing when the CPU controls the internal register (CDMAC), FIG. 5 is a state transition diagram showing the timing signal generation operation of the unit controller in FIG. 2, and FIG. FIG. 7 is a block diagram showing the operation and structure of the FIFO, FIG. 7 is a timing chart showing the operation timing of each signal in FIG. 5, FIG. 8 is a state transition diagram showing the state transition of the DMA sequencer in FIG. 2, and FIG. The figure is a block diagram showing the connection between the path sequencer 2l in FIG. 2 and the bus control unit l and FIFO in FIG. 1, and FIG. 10 is a state transition diagram showing the state transition of the path sequence in FIG. 9. FIG. 11 is a timing chart showing the operation timing of each signal in the scanner mode of the pass sequence of 101iH, and FIG. 12 is a timing chart showing the operation timing of each signal in the print mode of the pass sequence of FIG. 10. . 1: Bus control section, 2: CPU, 3: Address decoder, 4: Driver, 5: Control section. 6: Driver/receiver, 7 2-byte converter, 8: PIF0, 9: Scanner/printer interface, lO: System bus, l1: Page memory, 12: Interface port,
13: Scanner unit, 14: Printer unit, 2
1: Bus sequencer, 2 2: DMA sequencer,
23 Nuuni Soto Controller, 24: Line Counter, 25: Pixel Counter, 26: Address Counter,
27: DMA counter, 28 near address/data bus,
29: Address decoder, 30: Command register, 3
l: Status register, 32: Address latch, 33
:FIFO R/W switching unit, 9l: converter,
92: Scanner data control unit. Figure 4 Figure 5 GRSTN S3 Tomi [0 1} rllllh-L vote i1lTh! Green

Claims (2)

[Claims] (1) It has a system bus that is shared by a plurality of processors, a bus control means that arbitrates the right to use the system bus, and a page memory that is connected to the system bus. DM image data between the image data input/output device including an image scanner and a page printer and the page memory.
A scanner/printer interface means that is directly connected to the input/output device and performs line-by-line and pixel-by-pixel synchronization in the image processing system to be transferred;
A FIFO memory that writes and reads data for a line using first-in, first-out processing;
The FIFO comprises a counter that counts the lines processed by the memory, a counter that counts the number of bytes transferred between the system bus and the input/output device, an address counter for the page memory, and a sequencer that controls the sequence between each control signal. An image DMA transfer interface circuit comprising a control means for controlling memory operation timing and system bus access timing signals. (2) The control means separately sets a counter for counting the number of transferred bytes on the input/output device side and a counter for counting the number of transferred bytes on the system bus side, and 1 on the device side
2. The image DMA transfer interface circuit according to claim 1, wherein only a partial rectangular area of a page's worth of data is transferred between the system buses.