JPH0350874A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE:To make a data holding characteristic good and to comply with a high integration by a method wherein a phosphosilicate glass layer is formed on sidewall parts of a floating gate and a control gate and a silicon nitride film and an arsenosilicate glass film or a boron phosphosilicate glass film are formed one after another so as to cover the control gate. CONSTITUTION:A PSG film 6 is formed on sidewall parts of a floating gate FG and a control gate CG. On the other hand, a source region 7 and a drain region 8 which are, e.g. of an n<+> type are formed in a p-type Si substrate 1 in a self-aligned manner with the floating gate FG and the control gate CG. A memory transistor is formed of the floating gate FG, the control gate CG, the source region 7 and the drain region 8. An interlayer insulating film is constituted of the PSG film 6, an Si3N4 film 9 and an AsSG film 10. As viewed from the floating gate FG, the interlayer insulating film is a three-layer structure of the PSG film 6, the Si3N4 film 9 and the AsSG film 10. Consequently, it is possible to realize an EPROM whose data holding characteristic is good and which can comply with a high integration sufficiently.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to nonvolatile memory devices.

[Summary of the Invention] The present invention provides a nonvolatile memory device having a memory cell having a structure in which a control gate is stacked on a floating gate with an insulating film interposed therebetween. A silicon nitride film and an arsenic silicate glass film or a boron phosphorus silicate glass film are sequentially formed over the control gate.

This makes it possible to realize a nonvolatile memory device that has good data retention characteristics and is compatible with high integration.

[Conventional technology]

As a non-volatile memory device, E P ROM (Era
sable and programmable Re
ad 0nly Memory) and EE P ROM
(Electrically f!rasable a
nd Programmable Read 0nly
Memory) is known. This EPROM and E
EPROM stores data by accumulating charge in a floating gate.

In Japanese Patent Application No. 5A-23I1OS, the present applicant has proposed a layer of phosphorus silicate glass (PSC) containing 1 to 8% phosphorus on a floating gate, and a layer of silicon nitride (5%
izNa ) 111 and arsenic silicate glass (As
S G ) film or boron phosphosilicate glass (B
By creating a structure in which PSG) films are sequentially formed,
We have proposed a nonvolatile memory device and its manufacturing method that can improve the data retention characteristics of EPROMs and EEPROMs.

[Problem to be solved by the invention]

As mentioned above, the eyebrow insulating film of EPROM or EEPROM is made of PSG/5isNa/Ass G or PSC.
/SizN4/BPSG three-layer structure can improve data retention characteristics, but as higher integration progresses and contact holes become smaller, new problems such as the following will arise: occurs in This problem will be explained in detail below with reference to FIGS. 3A and 3B.

FIGS. 3A and 3B show a conventional EFROM manufacturing method.

As shown in FIG. 3A, according to the conventional EFROM manufacturing method, for example, on a p-type silicon (Si) substrate 101, a field insulating film 102, a gate insulating film 103, a floating gate FC'', a control gate CG', an insulating After forming the films 104 and 105, for example, the n-type source region 106 and drain region 107, P is formed as an insulating film between the eyebrows.
SG film 108, Si:+Na film 109 and As5G film 1
10 is formed on the entire surface. As already mentioned, a BPSG film may be used instead of this As5G film 110.

Next, on this As5G film 110, a resist pattern (not shown) is formed where a contact hole is to be formed.
After forming A, use this resist pattern as a mask.
s5G film 110, S i 3 Na film 109, PSG
The film 10B and the gate insulating film 103 are sequentially etched. As a result, contact holes C1' and 02' are formed as shown in FIG. 3B. After this, the resist pattern is removed.

Next, the As5G film 110 is reflowed by heat treatment, thereby forming the contact hole jLtC+.
, Cz" has a rounded and smooth shoulder as shown by the dashed line in FIG. The film is formed by sputtering or vapor deposition, and prior to this, light etching is first performed using a hydrofluoric acid (HF)-based etching solution as a pretreatment.

Then, after forming an Al film or an Al-5t alloy film,
This film is patterned into a predetermined shape by etching to form interconnections (not shown) that contact source region 106 and drain region 107 through contact holes C1' and Cz', respectively.

However, during the above-mentioned light etching, the P exposed inside the contact holes c, ′, c, ′
The SG film 108 is also etched into the shape shown by the dotted line in FIG. 3B. As a result, the contact hole CISO! after this light etching. There was a problem in that the shape of `` would deteriorate, which could cause contact failure.

Accordingly, an object of the present invention is to provide a nonvolatile memory device that has good data retention characteristics and is compatible with high integration.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a nonvolatile memory having a structure in which a control gate (CC,) is stacked on a floating gate (FC) via an insulating film (4). (F
A phosphorus silicate glass layer (6) is formed on the side walls of the control gate (CG) and the control gate (CG), and a silicon nitride film (9) and an arsenic silicate glass film (10) or a boron phosphorus film are formed to cover the control gate (CG). A silicate glass film is sequentially formed.

Here, from the viewpoint of obtaining good data retention characteristics and preventing deterioration of moisture resistance, a phosphorus-siligate glass layer (6
), it is preferable to use one containing 1 to 8% by weight of phosphorus.

[Function] The phosphorus silicate glass layer (6) is a floating game)
(FC) and the control gate (CG), the contact hole (C+,
Cz) can be formed at a location away from the phosphosilicate glass layer (6) by sequentially etching the arsenic silicate glass film (10) or the boron phosphosilicate glass film and the silicon nitride film (9). For this reason, the phosphosilicate glass layer (6) is not exposed inside the contact hole (c+, Cm) during light etching using a hydrofluoric acid-based etching solution, which is performed as a pretreatment for forming a film for forming wiring. There is no possibility that this phosphosilicate glass layer (6) will be etched during light etching. by this,
Contact hole (C+.

It is possible to prevent deterioration of the shape of C2), and therefore it is possible to respond to higher integration of nonvolatile memory devices.

The floating gate (FC) is formed by a three-layer glabella insulating film consisting of a phosphosilicate glass layer (6), a silicon nitride film (9), and an arsenic silicate glass film (10) or a boron phosphosilicate glass film. Since the structure is covered, good data retention characteristics can be obtained as already mentioned.

As described above, it is possible to realize a non-continuous memory device which has good data retention characteristics and is compatible with high integration.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to an EFROM. In addition, in all the drawings of the embodiment, the same parts are given the same reference numerals.

FIG. 1 shows an EPROM according to one embodiment of the present invention.

As shown in FIG. 1, in the EPROM according to this embodiment, for example, SiO□
A film-like field insulating film 2 is formed to provide isolation between elements.

The active area surrounded by this field insulating film 2? A gate insulating film 3, such as a SiO2 film, is formed on the surface of the +■ region. On this gate insulating film 3, for example, phosphorus (
n-type polycrystalline Si doped with impurities such as P)
A floating gate FC made of a film is formed. On this floating game (FC), for example, SiO
The control gate CG is
are layered. This control gate CG is made of, for example, an n'-type polycrystalline Si film or this n'-type polycrystalline Si film.
For example, tungsten silicide (W Si z
) can be formed using a polycide film, etc., which is a stack of high-melting point metal silicide films such as a film. Furthermore, an insulating film 5 such as a SiO□ film is formed on the upper surface of the control gate CG and on the side walls of the floating gate FG and the control gate CGO.

In this embodiment, the side walls of the floating gate FC and control gate CG are made of PSGSeO2. Here, the phosphorus concentration in this PSG film 6 is 1 to 8.
It is set as ``Juyo %''. Moreover, this PSGSeO2 thickness is, for example, 2
There are about 7,000 people.

On the other hand, there is a floating gate F in the p-type Si substrate 1.
For example, an n-type source region 7 and drain region 8 are formed in the self-alignment line with respect to G and control gate CG. And these floating games)
A memory transistor is formed by FC, control gate CO, source region 7, and drain region 8.

The code 9 is, for example, S i :l N where the film thickness is 0 about 500.
The reference numeral 10 indicates an As5G film having a thickness of about 6,000, for example. Then, the PSG film 6 and the S
The i 3 Na film 9 and the As5G film 10 constitute an interlayer insulating film.

Symbols C, , C, indicate contact holes. For example, A through these contact holes C+ and Cz.
Wiring lines 11 and 12 made of I or Al-5t alloy are in contact with the source region 7 and drain region 8, respectively.

Next, the EFR according to this embodiment configured as described above
An example of a method for manufacturing an OM will be described with reference to FIGS. 2A to 2C.

As shown in FIG. 2A, first, by selectively thermally oxidizing the surface of the p-type St substrate 1, a field insulating film 2 is formed to perform element isolation, and then the field insulating film 2 is surrounded by A gate insulating film 3 is formed on the surface of the active region.

Next, after forming a polycrystalline Si film for forming a floating gate on the entire surface by, for example, CVD method, this polycrystalline St
The film is doped with an n-type impurity such as P at a high concentration to form an n'-type polycrystalline St film. Next, this n+ type polycrystalline St film is patterned by etching to a predetermined width in a direction perpendicular to the cross section shown in FIG. 2A. Next, an insulating film 4, such as a SiOg film, is formed on this n-type polycrystalline Si film by, for example, a thermal oxidation method. next,
For example, after forming a polycrystalline St film for forming a control gate on the entire surface using the CVD method, this polycrystalline St film is doped with an n-type impurity such as P at a high concentration to form an n-type polycrystalline Si film. do. Next, a resist pattern (not shown) having a shape corresponding to the control gate CG to be formed on the n3 type polycrystalline St peritoneum for forming the control gate is formed by lithography. Next, according to the so-called double self-line method, using this resist pattern as a mask, an n-type packed crystal Si film for forming the control gate and an n-type packed crystal Si film for forming the floating gate are etched, for example, by reactive ion etching. By sequentially anisotropically etching in the direction perpendicular to the substrate surface using the (RIE) method, the floating gate)FG
and control gate CG are formed at the same time. As a result, these floating gates FG and control gates CG are formed with self-aligned lines. Next, for example, using the above resist pattern as a mask, p-type Si
By ion-implanting an n-type impurity such as arsenic (As) into the substrate 1 at a high concentration, the source region 7 and drain region 8 of, for example, the n0 type are formed into a floating gate F.
A self-aligned line is formed for G and control gate CG. After this, the resist pattern is removed. Note that these source regions 7 and drain regions 8 are treated with a control gate (C) after the resist pattern is removed.
It is also possible to form by performing ion implantation using G and floating gate FC as a mask. Next, the insulating film 5 is formed on the upper surface of the control gate CG and the side walls of the floating gate FC and the control gate CG by, for example, a thermal oxidation method. Thereafter, a PSG film 6 is formed on the entire surface by, for example, a CVD method.

Next, this PSG film 6 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE, so that only the side walls of the floating gate FC and the control gate CG are etched with this PSG film, as shown in FIG. 2B. Membrane 6 is left. Next, a Si3N4 film 9 and an As5G film 10 are formed on the entire surface by, for example, the CVD method.

Next, a resist pattern (not shown) with openings corresponding to the contact holes C, , C, to be formed on the As5G film 10 is formed, and using this resist pattern as a mask, the As5G film 10, the Si3N film, and the By sequentially etching the etching layer 9 and the gate insulating film 3, contact holes C+ and Ct are formed on the source region 7 and drain region 8, respectively, at locations away from the PSG film 6, as shown in FIG. 2C.

Next, the As5G film 10 is reflowed by heat treatment at a temperature of, for example, about 850°C. As a result, the shoulders of contact holes CI and Cg are made into rounded and smooth shapes (see FIG. 1).

Next, as a pretreatment before forming an AI film or an Al-5t alloy film for forming wiring, light etching is performed using an HF-based etching solution. In this case, as is clear from FIG. 2C, since the PSG film 6 is not exposed at all inside the contact holes C+ and Cz, there is no possibility that the PSG film 6 will be etched during this light etching. Next, after forming, for example, a single film or an Al-5i alloy film on the entire surface by, for example, sputtering or vapor deposition, this film is patterned into a predetermined shape by etching to form wiring lines as shown in Figure 1. EP that forms and aims at 11.12
Complete the ROM.

As described above, according to this embodiment, P is applied only to the side walls of the floating gate FC and the control gate CG.
An SG film 6 is formed, and contact holes C+, C
Since this PSG film 6 is not exposed at all inside Cz, a write process using an HF-based etching solution is performed after forming these contact holes C+ and Cz and prior to forming an Al film or an Al-St alloy film. This eliminates the problem of this PSG film 6 being etched during etching.For this reason, as EPROMs become more highly integrated, contact holes C1
, C2 are miniaturized, these contact holes C, , C are formed by this light etching.

There is no risk that the shape will deteriorate. Also, when viewed from the floating gate FC, the insulating film between the eyebrows is the PSG film 6,
Since it has a three-layer structure of the S i 3 Na film 9 and the As5G film 10, good data retention characteristics can be obtained as already mentioned.

As a result of the above, it is possible to realize an EPROM which has good data retention characteristics and is fully compatible with high integration.

The EPROM according to this embodiment is, for example, 0TP (One
It can be applied to one-chip microcomputers (Time Programmable), etc.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, it is possible to use, for example, a BPSG film instead of the As5G film 10 in the above embodiment. Also,
The memory transistor is a so-called LD D (Light
It is also possible to have a structure such as a doped drain.

Furthermore, the PSG film 6 and 5izN4 in the above embodiment
It is also possible to have a structure in which another film, such as a 5in2 film, is interposed between the film 9 and the Si3N film, and between the film 9 and the As5G film 10.

Further, in the above-described embodiments, the case where the present invention is applied to an EPROM has been described, but the present invention is applicable to an EEFR
It can be applied to OM and other various floating gate devices.

〔Effect of the invention〕

As explained above, in the present invention, a phosphosilicate glass layer is formed on the side walls of a floating gate and a control gate, and a silicon nitride film and an arsenic silicate glass film or a boron phosphosilicate glass film are sequentially formed covering the control gate. As a result, the shape of the contact hole does not deteriorate due to light etching performed as a pre-processing for film formation for wiring, and this makes it possible to create a non-volatile memory that has good data retention characteristics and is compatible with high integration. The device can be realized.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an EFROM according to an embodiment of the present invention, FIGS. FIG. A and FIG. 3B are cross-sectional views for explaining a conventional EFROM manufacturing method step by step. Explanation of main symbols in the drawings Lap type Si substrate, 3: Gate insulating film, 4°5: Insulating film, 6: PSG film, 7: Source region, 8 Nidrain region, 9: St: +N4 film, 10: A
s5G film, FG: floating gate, CG
: Control gate, C,, C, : Contact hole.

Claims (1)

[Claims] A nonvolatile memory device having a memory cell having a structure in which a control gate is stacked on a floating gate via an insulating film, wherein a phosphosilicate glass layer is formed on the sidewalls of the floating gate and the control gate. A nonvolatile memory device, wherein a silicon nitride film and an arsenic silicate glass film or a boron phosphorus silicate glass film are sequentially formed to cover the control gate.