JPH0350822A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remove, in the process of growth, the projection arising at the surface of a group III-V compound growth layer by putting the angle formed by the substrate main surface and the cavity side face in an acute angle at the place where the faces adjoin each other, when selectively growing the group III-V compound at the cavity part provided on a silicon single crystalline substrate. CONSTITUTION:An SiO2 layer 23 in the region where a single crystalline gallium arsenic layer is formed, and a silicon substrate 20 are etched in rectangle in the <110> direction. It is dug by ion beam etching method capable of oriented etching so that the angle alpha between the substrate surface and the cavity side face may be acute, for example, 55 deg.. For the single crystalline gallium arsenic layer grown at the face 100 of a silicon single crystalline substrate, a facet 100 is formed at the surface, and an face 111, inclined 55 deg. to the face 100, is grown at the end. A high resistance gallium arsenic layer 26 and an n-type gallium arsenic layer 27 to become a channel layer are formed in the groove.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor device, in which In −
The present invention relates to a method for manufacturing a semiconductor device that grows a group V compound.

<Conventional technology> Advanced integration technology has been established for integrated circuits made of silicon, and the silicon single crystal that serves as the substrate is inexpensive and can be obtained in large diameter, so it is manufactured at low cost. . On the other hand, In − including gallium arsenide
V-group compound semiconductors have been rapidly developed in recent years because they can produce elements that operate faster than silicon semiconductors, and they can produce light-emitting elements that cannot be produced with silicon semiconductors, and they have already reached the point where they have been put to practical use in gallium arsenide integrated circuits. It's in a stage. However, since it is difficult to make a single crystal of a -Y group compound large in diameter, the device is expensive, and the integration technology has not yet been fully developed. For this reason, silicon semiconductors and ■-Y group compound semiconductors have a complementary relationship, and when assembling a certain system, a combination of both is designed in consideration of performance and cost. . When designing, since integrated circuits are currently made as separate chips for each material, it is necessary to combine the separate integrated circuits as chips, and extra wiring between chips is also required. This prevents Synutem from becoming more sophisticated. In order to solve this problem, attempts have recently begun to be made to form semiconductor devices made of different materials on the same substrate. For example, IEEE GaAs IC
Symposium, +988. (See P, 239-242).

In order to specifically show how a semiconductor device having such a structure is manufactured, as an example, FIG. 3 shows the manufacturing process when a silicon MO8FET and a gallium arsenide MESFET are formed on the same chip. show. First, a source region 2, a drain region 3, a gate oxide film 4, and a gate electrode W5 are formed on a silicon single crystal substrate l by a normal MO8FET manufacturing process, and then the silicon substrate surface in a region where a gallium arsenide layer is to be formed is made reactive. Vertical etching is performed using the ion etching method (Fig. 3, 1). Next, a gallium arsenide layer of a predetermined thickness is grown on the etched portion by MBE. At this time, a monocrystalline gallium arsenide layer grows on the etched portion where the silicon surface is exposed, and a polycrystalline gallium arsenide layer grows on the oxide film. Thereafter, this unnecessary polycrystalline gallium arsenide layer is removed by etching (FIG. 3(b)). Furthermore, channel 1 and 7 are formed on the single crystal gallium arsenide layer 6 by a normal gallium arsenide MESFET fabrication process.
, a source electrode 8, a drain electrode 9, and a gate electrode 10 are formed (FIG. 3(C)). Finally, an insulating layer 11 is formed on the entire surface of the substrate, the insulating layer on the electrode for connecting the gallium arsenide MESFET 14 and the silicon MO8FET 13 is selectively removed, and the wiring electrode 12 is formed thereon.

In this way, gallium arsenide MESFET and silicon MOSFET having a structure arranged side by side on one silicon single crystal substrate
A semiconductor device consisting of 8 FETs was fabricated, but the grown single crystal gallium arsenide layer had protrusions as shown in FIG. 3(b) 15, and electrodes were wired across these protrusions. Since the electrode thickness at the protrusion is thinner, there is a high probability of wire breakage, which lowers the yield of device fabrication.

When a gallium arsenide compound is grown heteroepitaxially on the (100) plane of a silicon single crystal, the (
100) plane grows, but at the same time the (100) plane grows at the periphery of the groove.
One facet of the (311) plane inclined by 25° with respect to the 0) plane is created, which makes the peripheral part of the single-crystal gallium arsenide layer thicker. The protrusion shown in Figure 3(b) +5 is caused by the growth of this (311) plane, for example, and other ■-■ group compounds are similarly grown selectively on a silicon single crystal substrate. If you do this, similar protrusions will occur, so
This is a problem that must be solved when attempting to manufacture a semiconductor device in which a plurality of +nv group compound semiconductor elements and silicon semiconductor elements are integrated on a silicon single crystal substrate.

Such protrusions can be removed by etching or other methods, but this is undesirable as it adds a new process, and it is not preferable to remove tn -v in the depressions where protrusions have occurred during the growth process.
The purpose is to prevent the formation of protrusions when growing group compounds.

<Means for Solving the Problems> In the present invention, in order to solve the above problems, the shape of the depressions is devised when selectively growing [[-V group compound] in the depressions provided on the silicon single crystal substrate. In addition, the recess is formed so that the angle between the main surface of the substrate and the side surface of the recess becomes an acute angle where both surfaces meet.

Effect> When a ■-v group compound is heteroepitaxially grown on a silicon single crystal substrate, a specific crystal plane grows depending on the silicon single crystal plane of the growth site. Similarly, specific crystal planes appear at the ends of the grown crystals, and in the case of +n-v group compounds, the crystals often have a 1 flll (mesa-like shape). By using a concave shape, excessive crystal growth can be eliminated and the formation of protrusions can be prevented.

<Example> Hereinafter, the present invention will be explained in more detail with reference to Examples.

Example 1 FIG. 1 shows an example in which a silicon MO8FET and a gallium arsenide MESFET are formed on a silicon substrate having a plane orientation (100).

First, a silicon MO8FET is formed on a (+00) silicon substrate by a normal process. Next, the 5iOz layer 23 and the silicon substrate 20 in the region where the single-crystal gallium arsenide layer is to be formed are etched into a rectangular shape in the (110> direction.At this time, conventionally, the silicon (+00 ), the cross section in the direction perpendicular to the surface is rectangular, but in this example, the cross section is between the main surface of the substrate and the side surface of the recess, as shown in Figure 1(a). A 3 μm trench was dug using the ion rubber etching method, which allows directional etching, so that the angle α was 55°.
The lithium arsenide layer grows on the (10) surface.
0) faceno) is formed, and a (III) plane inclined at 55° with respect to the (100) plane grows at its end. The reason why α=55° in this example is to allow the gallium sheave crystal to grow while closely contacting the side wall of the groove with the (Ill) plane, and to prevent the occurrence of (311) facets. After this, as shown in FIG. 1(b), a 700 mm diameter is grown in the groove 35 previously formed by a two-step growth method using an MOCVD apparatus.
A gallium arsenide single crystal layer is grown to a thickness of 3 μm at 0°C. At this time, a polycrystalline gallium arsenide layer 25 is grown on the 5iOz layer 23.Furthermore, an impurity is added to the grown gallium sheave crystal upper layer to form an n-type gallium arsenide layer. In order to provide a resin protective layer in this area, the excess gallium arsenide polycrystalline layer 25 was removed by a chemical etching method (just before the end of etching, the etching solution touched the edge of the single crystal gallium arsenide layer 27, but the single crystal gallium arsenide polycrystal layer 25 Since the etching speed of gallium arsenide is slower than that of polycrystalline gallium arsenide, there was no practical problem due to etching of the edges. Through the above process, the high-resistance gallium arsenide 5 shown in FIG.
W26 and n-type gallium arsenide layer 27 which becomes channel/I/layer
is formed in the groove shown in FIG. 1, (a) 35, and the Si02
It was at the same height as the main surface of layer 23, and no protrusions were present.

Next, as shown in FIG. 1(c), the n-type gallium arsenide layer 27 is
Gate electrode 28, source electrode 29, drain electrode 3 on top
0 was formed and a gallium arsenide MESFET was completed.

Finally, as shown in Figure 1(d), an insulator XΔ34 is formed and the gallium arsenide MESFET3] and silicon MO3
32 were connected by wiring electrodes 33 to complete the desired device. Conventionally, when connecting two elements with the wiring electrode 33, disconnection was likely to occur due to the protrusions present at the ends of the gallium arsenide MESFET, but in this embodiment, since there were no protrusions, disconnection did not occur.

Embodiment 2 An embodiment in which the present invention is applied to a light emitting diode is shown in FIG.

First, a silicon MO8FET 40 was formed on a silicon single crystal substrate by a normal process. Next (Example I
An n-type gallium arsenide layer 41 was grown at 700°C in a depression formed in the same manner as above by a two-step MOCVD growth method.
Then, an n-type gallium arsenide layer 42 was formed. After the growth is completed, the polycrystalline gallium arsenide layer is selectively removed in the same manner as in Example 1, and the n-type electrode 43 is replaced with the n-type gallium arsenide layer 42.
Next, a p-type electrode 44 is formed in the p silicon region 45 previously formed by ion implantation. Finally, the electrode 43
and silicon MOS FET under the wiring tA・16;
I connected it better. In this case as well, the disconnection caused by the protrusions existing on the end of the upper surface of the gallium arsenide, which has been observed in the past, did not occur at all because there were no protrusions.

Above, in Examples 1 and 2, gallium arsenide compounds have been described, but the present invention can also be applied to other +n-
It is also effective for V group compounds. In addition, Examples 1 and 2
In this example, the angle between the side surface of the recess and the main surface of the substrate was set to 55° at the point where both surfaces touched, but in this example, this angle is valid as long as it is 55° or less, and in cases other than this example, Angles other than those mentioned in 55° are also valid.
Or, it is not limited to 55 degrees or less. Further, the shape of the recess in a cross section parallel to the substrate or the direction of the recess side surface is not limited to the rectangle or (110>) shown in the embodiment, and the inclination of the side surface is not necessarily an acute angle over the entire circumference of the recess. It is not necessary, and only the wiring part is sufficient.

<Effects of the Invention> As described above, according to the present invention, when selectively forming a 1■-V group compound on a silicon single crystal substrate, conventional l1
It is possible to eliminate the protrusions that occur on the surface of the 1-V group compound growth layer during the growth process, and it is possible to eliminate disconnections due to differences in the electrodes that connect elements, and it is possible to It has become possible to greatly increase the yield of semiconductor devices manufactured by integrating 1[-V group compound semiconductor elements and silicon semiconductor elements.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a semiconductor device for explaining the present invention in detail, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. 20: Si substrate 21: Sone region 22 Nidrain region 23: Gate oxide film 24: Gate electrode 25: Polycrystalline GaAsJfJ 26: High resistance GaAs layer 27: N-type GaAs layer 28: Gate electrode 29: Saone electrode 30 Nidrain electrode 31: GaAs MES FET 32, 40: Si MO8FET 33.46:
Wiring electrode 34.47: Insulating layer 41: P-type GaAs layer 42: N-type GaAs layer 43 2nd n-side electrode 44: 9wl electrode

Claims (1)

[Claims] 1. III in the recessed portion provided in the silicon single crystal substrate
- A method for manufacturing a semiconductor device in which a Group V compound is selectively grown, characterized in that an angle between the main surface of the substrate and a side surface of the recess is an acute angle where both surfaces meet.