JPH0350763A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0350763A JPH0350763A JP1185354A JP18535489A JPH0350763A JP H0350763 A JPH0350763 A JP H0350763A JP 1185354 A JP1185354 A JP 1185354A JP 18535489 A JP18535489 A JP 18535489A JP H0350763 A JPH0350763 A JP H0350763A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- amorphous silicon
- silicon layer
- lower electrode
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000011261 inert gas Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 abstract description 43
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 229910052786 argon Inorganic materials 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- 230000001747 exhibiting effect Effects 0.000 abstract 1
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、プログラム可能な記憶素子の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of programmable storage elements.
［従来の技術］
従来のプログラム可能な記憶素子の構造は、υ、Ｓ、Ｐ
ａｔｅｎｔ Ｎｏ、４４４２５０７の槌に、下部電極
上に、アモルファスシリコン層があり、上部電極の金属
層が積層される構造であった［発明が解決しようとする
課題］
しかし、前述の従来技術では、５１圧を電極間に印加し
、アモルファスシリコン層を絶縁破壊してプログラムを
行なった後の電極間の抵抗が高く、特に書き込み電流が
少ない場合は、１０にΩ〜１ＭΩと高（なるという問題
を有する。[Prior Art] The structure of a conventional programmable memory element is υ, S, P.
The mallet of client No. 4442507 had a structure in which an amorphous silicon layer was formed on the lower electrode, and a metal layer of the upper electrode was laminated. There is a problem that the resistance between the electrodes is high after programming is performed by applying pressure between the electrodes and dielectrically breaking down the amorphous silicon layer, and the resistance between the electrodes is as high as 10Ω to 1MΩ, especially when the write current is small. .
本発明は、このような問題を解決するもので、その目的
とするところは、プログラム可能な記憶素子における、
低く安定した、プログラム後の抵抗を得ることが可能な
半導体装置を提供するところにある。The present invention solves such problems, and its purpose is to provide a programmable storage device with
An object of the present invention is to provide a semiconductor device that can obtain a low and stable resistance after programming.
［課題を解決するだめの手段］
本発明の半導体装置は、半導体基板に第一の導電型を有
する下部半導体電極上に、不活性ガスがイオン打ち込み
され、かつ、前記下部電極と同じ導電型を示す不純物を
含んだアモルファスシリコン層と上部電極からなる事を
特徴とする。[Means for Solving the Problems] In the semiconductor device of the present invention, an inert gas is ion-implanted onto a lower semiconductor electrode having a first conductivity type in a semiconductor substrate, and the lower semiconductor electrode has the same conductivity type as the lower electrode. It is characterized by consisting of an amorphous silicon layer containing impurities shown in the figure and an upper electrode.
［実施例］
第１図は、本発明の実施例における半導体装置の断面図
を示す。１０１は、半導体基板、１０２は、Ｎ＋拡散層
、１０３は、層間絶縁膜、 １０４は、不活性ガスがイ
オン打込みされ、かつ、１０２ＯＮ＋拡散層と同じ導電
型を示す不純物とを含んだアモルファスシリコン層、１
０５は、バリアメタル層、１０６は、アルミニウム配線
層である以下、本発明の実施例を詳細に説明する。まず
、半導体基板１０１に、゛イオン打ち込み法を用いて、
Ｎ＋拡散層を形成する一例として、リンを６０ＫｅＶで
４ Ｘ １０１５ｃｍ”注入したのち、９００℃で２０
分間アニールし、Ｎ＋拡散層１０２を形成する。その後
、シリコン酸化膜を気相成長法により層間絶縁膜１０３
を形成し、その後、記憶素子を形成する箇所のみ、フォ
） ＩＪソ技術及びエツチング技術によりシリコン酸化
膜を除去する。その後、気相成長法により、アモルファ
スシリコン層１０４を１５００λ程度形成した後、イオ
ン打込法を用いて、アルゴンを１００Ｋｅ’Ｖで１×１
０１６ｃｒｎ−２注入し、Ｎ＋拡散層１０２を３００〜
４０ｏＸアモルファス化する。その後、リンを６０Ｋｅ
ＶでｌＸｌ０Ｉ’（７）−２注入することにより、１０
４のアモルファスシリコン層ヲより一部アモルファス化
スル。次に１０４のアモルファスシリコン層を所望の形
状にエツチングしたのち、その上にスパッター法により
、バリアメタル層１０５及びアルミニウム配線層１０６
を形成し、フォトリソ技術及びエツチング技術により、
所望のパターンに加工する。[Example] FIG. 1 shows a cross-sectional view of a semiconductor device in an example of the present invention. 101 is a semiconductor substrate, 102 is an N+ diffusion layer, 103 is an interlayer insulating film, 104 is an amorphous silicon layer into which an inert gas is ion-implanted and contains an impurity having the same conductivity type as the ON+ diffusion layer 102 ,1
05 is a barrier metal layer, and 106 is an aluminum wiring layer. Examples of the present invention will be described in detail below. First, the semiconductor substrate 101 is implanted using the ion implantation method.
As an example of forming an N+ diffusion layer, 4×1015 cm” of phosphorus was implanted at 60 KeV, and then 20 cm was implanted at 900°C.
Annealing is performed for a minute to form an N+ diffusion layer 102. Thereafter, a silicon oxide film is grown as an interlayer insulating film 103 by a vapor phase growth method.
After that, the silicon oxide film is removed only at the location where the memory element is to be formed using IJ etching technology and etching technology. After that, an amorphous silicon layer 104 of about 1500λ is formed by vapor phase growth, and then 1×1 argon is deposited at 100 Ke'V using ion implantation.
016crn-2 is implanted and the N+ diffusion layer 102 is
40oX amorphous. After that, 60Ke of phosphorus
By injecting lXl0I'(7)-2 at V, 10
Part of the amorphous silicon layer in No. 4 is amorphous. Next, after etching the amorphous silicon layer 104 into a desired shape, a barrier metal layer 105 and an aluminum wiring layer 106 are formed thereon by sputtering.
is formed, and by photolithography and etching technology,
Process into desired pattern.
以上の工程を経て、本発明のプログラム可能な記しホ素
子が形成される。Through the above steps, the programmable writing element of the present invention is formed.
上記の実施例のアモルファスシリコン層への第二の不純
物は、Ｎ 拡散Ｊ−の形成ではリンを用いたが砒素でも
構わない。又、Ｐ＋拡散層を形成した場合は、拡散層及
びアモルファスシリコン層への不純物添加は、ボロンで
も構わない。又、上記下部電極には拡散層を用いたが、
多結晶シリコン１０でも構わない。As the second impurity to the amorphous silicon layer in the above embodiment, phosphorus was used to form the N diffusion J-, but arsenic may also be used. Further, when a P+ diffusion layer is formed, boron may be added as an impurity to the diffusion layer and the amorphous silicon layer. Furthermore, although a diffusion layer was used for the lower electrode,
Polycrystalline silicon 10 may also be used.
第２図は、第１図に示した本発明の実施例による、アモ
ルファスシリコン層に、不活性ガス及び下部電極と同じ
導電型を示す不純物を添加した場合Ｂのプログラム電圧
と従来技術Ａ（アモルファスシリコン層のみ）によるプ
ログラム電圧を示すグラフであり、Ｂは高エネルギーの
不活性ガスの注入により、アモルファスシリコン層が広
がった事を示している。FIG. 2 shows the programming voltage of case B and conventional technology A (amorphous silicon layer) according to the embodiment of the present invention shown in FIG. This is a graph showing the programming voltage due to the silicon layer only), and B indicates that the amorphous silicon layer has expanded due to the injection of high-energy inert gas.
第３図は、上述、第２図に示したもののプログラム後の
抵抗を示すもので、アモルファスシリコン層に、不活性
ガス及び下部電極と同じ導電型を示す不純物を添加した
場合Ｂは、よりアモルファス状態が進行することにより
、従来技Ｗｆ Ａの場合に比ベグログラム後の抵抗が低
下することは明確である。Figure 3 shows the resistance after programming of the one shown above and in Figure 2. When an inert gas and an impurity having the same conductivity type as the lower electrode are added to the amorphous silicon layer, B becomes more amorphous. It is clear that as the condition progresses, the resistance after the comparison vegogram decreases in the case of the prior art Wf A.
［発明の効果］
以上、述べたように本発明によれば、下部電極上のアモ
ルファスシリコン層に不活性ガスを下部電極の一部を結
晶破壊゛する程度のエネルギーで打ち込み、かつ、下部
電極と同じ導電型を示す不純物を添加することにより、
アモルファスシリコン層がより一部アモルファス状態に
なり、電圧印加によるプログラム時にアモルファスシリ
コンが多結晶に転じ、不純物がとり込まれ低い書き込み
電流でもプログラム後の抵抗が低く安定するという効果
を有する。又、プログラム前の抵抗とプログラム後の抵
抗差においても、４〜５桁程度あり記憶素子としての機
能は充分満足させるものである[Effects of the Invention] As described above, according to the present invention, inert gas is injected into the amorphous silicon layer on the lower electrode with enough energy to cause crystal destruction in a part of the lower electrode, and By adding impurities that exhibit the same conductivity type,
Part of the amorphous silicon layer becomes amorphous, and during programming by voltage application, the amorphous silicon turns into polycrystalline, and impurities are incorporated, resulting in a low and stable resistance after programming even at a low write current. Also, the difference in resistance before programming and after programming is about 4 to 5 digits, which satisfies the function as a memory element.
第１図は、本発明の半導体装置の一実施例を示す断面図
。
第２図は、本発明の実施例による、アモルファスシリコ
ン層に不活性ガス及び下部電極と同じ導電型を示す不純
物を添加した場合と、従来技術のアモルファスシリコン
層のみによるプログラム電圧の比較を示すグラフ。
第６図は、第２図に示したもののプログラム後の抵抗を
示すグラフ。
１０１・・・・・・・・・半導体基板
１０２・・・・・・・・・Ｎ＋拡散層
１０３・・・・・・・・・層間絶縁膜
１０４・・・・・・・・・不活性ガスをイオン打ち込み
し、かつ、Ｎ＋拡散層と同じ導電型の
不純物を含んだアモルファスシリ
コン層
１０５・・・・・・・・・バリアメタル１０６・・・・
・・・・・アルミニウム配線層以上FIG. 1 is a sectional view showing an embodiment of a semiconductor device of the present invention. FIG. 2 is a graph illustrating a comparison of the programming voltage when an inert gas and an impurity having the same conductivity type as the lower electrode are added to the amorphous silicon layer according to an embodiment of the present invention, and when using only the amorphous silicon layer according to the prior art. . FIG. 6 is a graph showing the resistance after programming of the one shown in FIG. 101...Semiconductor substrate 102...N+ diffusion layer 103...Interlayer insulating film 104...Inactive Amorphous silicon layer 105 into which gas is ion-implanted and contains impurities of the same conductivity type as the N+ diffusion layer...Barrier metal 106...
...Aluminum wiring layer or higher
Claims (1)
の導電型を有する下部半導体電極上に、不活性ガスがイ
オン打ち込みされ、かつ、前記下部電極と同じ導電型を
示す不純物を含んだアモルファスシリコン層と上部電極
からなる事を特徴とする半導体装置。In a programmable memory element, an inert gas is ion-implanted onto a lower semiconductor electrode having a first conductivity type in a semiconductor substrate, and an amorphous silicon layer containing impurities having the same conductivity type as the lower electrode is formed. A semiconductor device characterized by comprising an upper electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185354A JP2870823B2 (en) | 1989-07-18 | 1989-07-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1185354A JP2870823B2 (en) | 1989-07-18 | 1989-07-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0350763A true JPH0350763A (en) | 1991-03-05 |
| JP2870823B2 JP2870823B2 (en) | 1999-03-17 |
Family
ID=16169321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1185354A Expired - Lifetime JP2870823B2 (en) | 1989-07-18 | 1989-07-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2870823B2 (en) |
-
1989
- 1989-07-18 JP JP1185354A patent/JP2870823B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2870823B2 (en) | 1999-03-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5043049A (en) | Methods of forming ferroelectric thin films | |
| KR100243286B1 (en) | Method for manufacturing a semiconductor device | |
| KR910000019B1 (en) | A method of fabricating poly crystalline silicon resistor | |
| JPS6010773A (en) | Method of forming 1-element fet-memory capacitor circuit | |
| JPH0614532B2 (en) | Method for forming a resistor in a polycrystalline semiconductor material | |
| EP0288681B1 (en) | Heterojunction bipolar transistor | |
| JPH04215424A (en) | Metal semiconductor ohmic contact point type formation processing method | |
| JP3539417B2 (en) | Silicon carbide semiconductor device and method of manufacturing the same | |
| JPH0350763A (en) | Semiconductor device | |
| JPS6197975A (en) | Manufacture of semiconductor device | |
| JPH02208962A (en) | Semiconductor device | |
| KR900005871B1 (en) | Etching method of semiconductor device | |
| JPH11238872A (en) | Semiconductor device | |
| JP3216559B2 (en) | Method for manufacturing semiconductor device | |
| JPH0235769A (en) | Semiconductor device | |
| JPH0567067B2 (en) | ||
| JPH0629543A (en) | Manufacture of semiconductor device | |
| JP3052489B2 (en) | Method for manufacturing thin film transistor | |
| JPH04307741A (en) | Manufacture of semiconductor device | |
| JPH01268047A (en) | Formation of polysilicon resistor | |
| JPS6213818B2 (en) | ||
| JPH1032311A (en) | Method for forming a capacity element | |
| JPH01109716A (en) | Formation of contact in semiconductor device | |
| JPS58122769A (en) | Manufacture of semiconductor device | |
| JPH01282862A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090108 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100108 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100108 Year of fee payment: 11 |