JPH0350635A - Generation method for in-circuit test program - Google Patents

Abstract

PURPOSE:To prevent the allocation of test pins to electronic components which are not used in a test program and to reduce the change quantity of a test system by providing a test program generation processing part. CONSTITUTION:Test pins and parts terminals corresponding information generation processing Ji inputs line connection information F1 and packaging information F2 and generates test pins and parts terminals corresponding information in test pins/parts terminals corresponding information F3. The test program generation processing part J2 inputs information J1 and information F3 and generates the test program in the test program F4. An in-circuit test is conducted by the program F4. Thus, the allocation of the test pins is prevented for the electronic components which are not used in the test program by using mounted information F2, and the change quantity of the test system can be reduced even if the number of the mounted electronic components is large and the number of the terminals of the parts increases.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an in-circuit test program, and particularly to a method for creating an in-circuit test program characterized by a test pin allocation method.

[Prior Art] A conventional method for allocating test pins in this type of in-circuit test program is to allocate test pins to all terminals of electronic circuit components mounted on an electronic circuit board.

That is, as shown in FIG. 2, the test program generation processing unit J3 is a processing unit that generates a test program, and
Circuit connection information F5 and test pin and component terminal correspondence information F6
A test program was created in the test program F7 using the input as input, and an in-circuit test was performed using this test program F7.

[Problems to be Solved by the Invention] The conventional in-circuit test program creation method described above assigns test pins to all terminals of electronic circuit components mounted on an electronic circuit board without using mounting information. Therefore, as electronic circuit packages become larger and the number of mounted components increases, there is a problem that test pins become insufficient.

[Means for Solving the Problems] The present invention has been made in view of the above problems, and provides electronic circuit components that are mounted without assigning test pins to electronic components that are not used in a test program. Even if the number of test pins and component terminals increases, the purpose is to reduce the amount of changes to the test system. A test pin and component terminal correspondence information creation processing section that creates correspondence information, and a test program generation processing section that creates a test program from the test pin and component terminal correspondence information and circuit connection information created by the test pin and component terminal correspondence information creation processing section. It is configured to provide.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a process diagram showing an embodiment of a method for creating an in-circuit test program according to the present invention.

In FIG. 1, a test pin and component terminal correspondence information creation processing unit J1 is a processing unit that creates correspondence information between test pins and component terminals, and inputs circuit connection information F1 and mounting information F2, and inputs test pin and component terminal correspondence information F3. Create correspondence information between test pins and component terminals.

The test program generation processing unit J2 is a processing unit that generates a test program, and creates a test program in the test program F4 by inputting the circuit connection information F1 and the test pin and component terminal correspondence information F3.

An in-circuit test is performed using this test program F4.

In this way, by using mounting information, you can avoid assigning test pins to electronic components that are not used in the test program, and you can avoid assigning test pins to electronic components that are not used in the test program. , making it possible to reduce the amount of changes to the test system.

[Effects of the Invention] As explained above, the present invention provides a test pin and component terminal correspondence information creation processing section that inputs circuit connection information and mounting information to create correspondence information between test pins and component terminals, and Since the configuration includes a test program generation processing section that creates a test program using the test pin and component terminal correspondence information and circuit connection information created by the terminal correspondence information creation processing section, it is possible to allocate test pins to electronic components that are not used in the test program. By avoiding this, it is possible to reduce the amount of changes to the test system even if the number of electronic circuit components to be mounted increases and the number of component terminals increases.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing an embodiment of an in-circuit test program creation method according to the present invention, and FIG. 2 is a process diagram showing a conventional in-circuit test program creation method. Fl...Circuit connection information F2...Mounting information F3...Test pin and component terminal correspondence information F4.
...Test program Jl ...Test pin and component terminal correspondence information creation processing section

Claims (1)

[Claims] A test pin and component terminal correspondence information creation processing section that inputs circuit connection information and mounting information to create correspondence information between test pins and component terminals; and a test pin and component terminal correspondence information creation processing section that creates correspondence information between test pins and component terminals. A method for creating an in-circuit test program, comprising a test program generation processing unit that creates a test program using the test pin and component terminal correspondence information and the circuit connection information.