JPH0350284B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an optical coordinate input device including a light emitting element array and a light receiving element array.

(Technical background of the invention) Optical coordinate input devices are
It is attached to the front of the display surface of an LCD (liquid crystal display), etc., and uses a scanning method in which the light signals output from each light emitting element of a light emitting element array are received by each light receiving element of a light receiving element array. Furthermore, when the optical signal is interrupted by a finger or the like, the position is outputted to a personal computer or the like as indicated coordinates.

FIG. 4 shows a circuit configuration for processing optical signals of a conventional optical coordinate input device. That is, in the figure, 10 indicates a light receiving element array, and this light receiving element array is formed from a plurality of phototransistors _PT1 to PTn. Each phototransistor PT ₁ ~
The emitters of PTn are commonly grounded, and the collectors are connected to the switches SW ₁ to SWn of the switching circuit 12. Each switch _SW1 to SWn is connected to an NPN transistor 14 via a coupling capacitor _C1 .
connected to the base of. This transistor 1
The collector of 4 is connected to the power supply Vcc via resistors R ₁ and R ₂ .
is also connected to the output terminal 16 via a coupling capacitor _C3 . The base of transistor 14 is connected to the power supply via base resistor _R3 .
Vcc is connected. Phototransistors PT _{1 to} PT are connected between resistors R ₁ and R ₂ via a switching circuit 12.
A resistor _R4 is connected to apply voltage to PTn. In addition, the power supply Vcc is connected between resistors _R1 and _R2 .
A capacitor _C2 is connected to bypass the fluctuations in .

Next, the light reception processing operation of the optical coordinate input device will be explained.

When the synchronizing pulse shown in FIG. 5a is input to the switching circuit 12, the switch _SW1 is closed and a voltage is applied to the collector of the phototransistor _PT1 via the resistors _R1 and _R4 . On the other hand, a light emitting element array (not shown) is scanned in response to the input of the synchronization pulse, and the LED corresponding to the phototransistor _PT1 emits light.
Therefore, since the optical signal Sp from the LED is received by the phototransistor _PT1 , the phototransistor _PT1 becomes conductive.

When the phototransistor PT ₁ becomes conductive, a negative pulse voltage is applied to the base of the transistor _{14 via the coupling capacitor C 1} and the transistor 14 is switched to the OFF state.
Since base current Ib stops flowing, its collector voltage rises. Therefore, the collector voltage is converted to the coordinate signal { _5th
It can be taken out from the output terminal 16 as shown in Figure e}. Note that since the LED corresponding to the phototransistor PT ₁ outputs at least two or more optical signals Sp during one run, the coordinate signal is composed of two or more pulse signals.

Similarly, each time a synchronization pulse is input, the switches SW ₂ to SWn of the switching circuit 12 are closed, and the phototransistors PT ₁ to PTn receive the optical signal Sp from the corresponding LED, so the coordinates indicating each coordinate position are Signals can be obtained continuously. Therefore, if the optical signal is blocked by a finger or the like and, for example, the optical signal is not received by the phototransistor PT ₃ , no coordinate signal is output from the output terminal 16, so that the scanning (phototransistor PT ₃ ) position and The indicated coordinates can be found from the relationship.

(Problems with the Background Art) Now, light emitting and light receiving elements such as phototransistors PT ₁ to PTn and LEDs that output optical signals Sp have variations in characteristics with respect to optical signals. Further, the phototransistors PT ₁ to PTn are affected by changes in light intensity from a CRT display, etc., and by ambient light. Therefore, the collector voltage Vp of each phototransistor varies greatly. Therefore, as shown in FIG. 5b, if the collector voltage Vp of the phototransistor PT ₂ decreases significantly due to external light or the like at the time when the phototransistor PT ₂ receives the optical signal Sp, the base of the transistor 14 Since the voltage Vb also decreases as shown in FIG. 5c, the transistor 14 may be held in the OFF state during the scanning period of the phototransistor _PT2 . Therefore, as shown in Figure 5e, the coordinate signal remains rising, so even though the phototransistor PT ₂ is receiving the optical signal Sp, the personal computer etc. does not receive the coordinate input. I mistakenly think that it is something that has happened.

In addition, a resistor R ₃ is connected to the base of the transistor 14.
Since a voltage is applied through the coupling capacitor _C1 , a charging current Ic flows into the coupling capacitor C1, as shown in FIG. Therefore, when the collector voltage Vp of the phototransistor decreases, the fifth
As shown by _PT2 and PT(n-1) in FIG. c, the falling level of the base voltage Vb of the transistor 14 increases. However, since the base voltage Vb only increases gradually based on the time constant of the resistor _R3 and the coupling capacitor _C1 , if the collector voltage Vp of the phototransistor decreases significantly,
As mentioned above, the coordinate signal remains rising. For example, as shown in FIG. 5b,
If the optical signal Sp is received at the time when the collector voltage Vp of the phototransistor PT ₃ has slightly increased,
Low level base current Ib in transistor 14
flow or distortion may occur in the rising waveform of the base current Ib (see waveform in FIG. 5d), making it difficult to determine whether the coordinate signal is output as a pulse waveform. Therefore, in this case as well, there is a risk that the personal computer or the like may make an erroneous judgment.

Furthermore, when the switches SW ₁ to SWn of the switching circuit 12 are switched by the synchronization pulse, each phototransistor PT ₁ to SWn is switched due to switching noise.
The collector voltage Vp of PTn falls momentarily,
The base voltage Vp of the transistor 14 also drops instantaneously. For this reason, switch SW ₁ ~
When SWn is switched, the base current Ib of the transistor 14 is momentarily reduced or cut off, and the noise signal N is added to the coordinate signal. Therefore,
There is a risk that a personal computer or the like will determine this noise signal N as a coordinate signal, which may also cause erroneous determination.

As explained above, the region between the base and emitter of the transistor 14 acts as a diode and forms a clamp circuit together with the coupling capacitor _C1 and the resistor _R3 , so that when the base voltage Vb decreases, the voltage Vb is adjusted to a specified level. Correct by clamping to match the level. However, as mentioned above, if the base voltage Vb fluctuates significantly due to variations in the optical characteristics of the light-emitting and light-receiving elements, disturbance light, and switching noise, the base voltage Vb cannot be maintained at a predetermined level even by clamping.
It is not possible to correct up to Vbl.

If the resistance value of resistor R ₃ is set to a small value, a large correction can be made by the clamp operation, but if the resistance value of resistor R ₃ is small, transistor 1
The excess stored carriers accumulated in the base of transistor 14 will increase and the impedance on the base side of transistor 14 will decrease. Therefore, with respect to the rise of the collector voltage Vp of the phototransistor,
The fall and rise of the base voltage Vb of the transistor 14 are delayed, and the waveform of the base voltage Vb is distorted. Therefore, when scanning the light-emitting and light-receiving elements at high speed, this may similarly cause erroneous judgments.

(Objective of the Invention) An object of the present invention is to provide an optical coordinate input device that accurately sends out coordinate signals without being affected by disturbance light or switching noise.

(Summary of the Invention) The present invention applies a predetermined voltage by a switching means to the base of a bipolar transistor for amplifying and outputting a coordinate signal when switching a switching circuit, and also adjusts the level of the coordinate signal applied to the bipolar transistor. is fixed at a predetermined level using clamp means.

(Embodiments of the Invention) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the overall configuration of an optical coordinate input device according to the present invention. That is, this coordinate input device includes a light emitting element array 20 and a light receiving element array 30. The light emitting element array 20 includes a plurality of LEDs ₁ to
It consists of LEDn and is arranged in an L-shape in front of the display surface of a CRT display (not shown). Further, the light receiving element array 30 includes a plurality of phototransistors.
These phototransistors consist of PT ₁ to PTn.
PT ₁ to PTn are arranged in an L-shape at opposite positions on the front surface of the display surface, facing LED ₁ to LEDn, respectively. The anode sides of LED ₁ to LEDn are connected to each switch of the switching circuit 22.
2 is connected to a drive circuit 24. A drive signal Sd from the CPU 40 is supplied to the drive circuit 24.

Phototransistors PT ₁ to PTn are switching circuits 12
It is connected to the amplifying section 50 via. That is, the emitters of the phototransistors PT ₁ to PTn are connected to the first
As shown in the figure, it is commonly grounded, and each collector is connected to a respective switch SW ₁ to SWn of the switching circuit 12.
It is connected to the. Each switch SW ₁ -SWn is connected to the base of the NPN transistor 14 via a coupling capacitor C ₁ . A power supply is connected to the collector of the transistor 14 via resistors R ₁ and R ₂ .
Vcc is connected. In addition, the transistor 14
An output terminal 16 is connected to the collector of the output terminal ₁₆ via a coupling capacitor C3. Output terminal 1
The coordinate signal Sxy from 6, which will be described later, is input to the CPU 40 as shown in FIG. The base of the transistor 14 is connected to the power supply Vcc via the base resistor _R3 .
is connected. Phototransistors PT ₁ to PTn are connected to the resistors R ₁ and R ₂ via a switching circuit 12.
A resistor R4 is connected to apply a voltage to the resistor _R4 , and a capacitor _C2 is connected between them to bypass fluctuations in the power supply Vcc. and,
The emitter and collector of a PNP transistor 52 used as switching means are connected to the collector and base of the transistor 14, respectively, and the pulse processing circuit 60 is connected to the base of the PNP transistor 52. The pulse processing circuit 60 receives the drive signal Sd output from the CPU 40, and similarly, the drive signal is held at the "L" level at the time of input of the synchronization pulse output from the CPU 40, so this drive signal Sd
is provided to the base of the PNP transistor 52 as a switching signal Ss. Also, transistor 1
The cathode side of a diode 54 is connected to the base of 4. The anode side of this diode 54 is grounded, and together with the coupling capacitor _C1 , it constitutes a lower end clamp circuit.

Next, the operation of the optical coordinate input device according to the present invention will be explained with reference to the waveform diagram of FIG.

First, when a synchronizing pulse {see FIG. 3a} is input from the CPU 40 to the switching circuits 12 and 22, switch SW _{1 of the switching circuit 12 and switch SW 1} of the switching circuit 22 are turned on.
Since the switch corresponding to LED ₁ is closed, the collector voltage Vp of phototransistor PT ₁ drops instantaneously due to switching noise, as shown in FIG. 3c. On the other hand, at the time when the synchronization pulse is input to the switching circuit, the drive signal Sd is held at the "L" level, and the synchronization pulse is simultaneously input to the pulse processing circuit 60. Therefore, the pulse processing circuit 60 supplies the "L" level drive signal Sd as the switching signal Ss to the base of the PNP transistor 52 only from the fall of the synchronizing pulse until the rise of the drive signal Sd, and the transistor 52 is switched to the ON state, a voltage is applied to the base of the transistor 14 via the resistors R ₁ and R ₂ and the emitter and collector of the PNP transistor 52, and a current Is flows as shown in FIG. Therefore, the base voltage Vb of the transistor 14
is a predetermined voltage, that is, the base-emitter voltage Vbe of the transistor 14, as shown in FIG. 3d.
(≒0.6V), which is held at a voltage slightly higher than the base bias voltage set by resistor _R3 . As a result, as shown in FIG. 3e, the transistor 1
4, the base current Ib (waveform shown by diagonal lines) flows and its collector voltage falls, so that the noise signal N shown by the broken line in FIG. 3f is no longer added to the coordinate signal.

This operation of erasing the noise signal N is performed by a pulse processing circuit 6 that performs an AND process between the drive signal Sd output from the CPU 40 and the synchronization pulse shown in FIG. 3a.
According to the switching signal Ss output from 0,
Even though the light-emitting element is switched and connected by the switching circuit 22 in the off state, the noise signal N generated when the switching circuit 12 switches and connects the light-receiving element corresponding to this light-emitting element, and this light-receiving element receives light. The transistor 52 generates disturbance light and the operating voltage that varies between the light receiving elements from the time the light receiving element is switched and connected until just before the light emitting element switched at the same time as the light receiving element starts lighting. Noise is eliminated by forcibly increasing the base voltage Vb and passing the base current Ib through the transistor 14 for dynamic clamping. The value of the base current Ib at this time is the resistance _R1 and
The maximum value is regulated by the series resistance value of R ₂ and the impedance between the emitter and collector of the transistor 52 that is in the energized state.

The drive signal Sd for lighting the light emitting element is
According to the synchronizing pulse shown in FIG. 3a output from the CPU 40, one selected light emitting element and one light receiving element are selected and connected by the pair of switching circuits 12 and 22. It consists of three pulse signals that repeat a set of "L" and "H" levels three times in order to cause the element to turn off and turn on only three times. When this drive signal is supplied to the drive circuit 24, the LED ₁ is driven and three optical signals Sp are output, so the phototransistor PT ₁ receives these optical signals and becomes conductive. That is, the resistances R ₁ , R ₄ ,
A current flows through the switch _SW1 and the collector/emitter of the phototransistor _PT1 , and the collector voltage Vp of the phototransistor _PT1 falls continuously in a pulsed manner. Therefore, ₃ is connected to the base of the transistor 14 via the coupling capacitor C1.
Since the negative pulse voltage {see FIG. 3 d} is applied, the base current Ib falls continuously in a pulsed manner as shown in FIG. 3 e. Therefore, the collector voltage of the transistor 14 rises, and a coordinate signal consisting of three pulse signals is output from the output terminal 16. The CPU 40 counts pulses by inputting this coordinate signal, and counts the pulses to a predetermined number of "3".
is obtained, so it is determined that there is no coordinate input.

When the collector voltage Vp of the phototransistor PT ₂ to be scanned next is reduced due to its characteristics, ambient light, etc. (see Figure 3c),
When the synchronization pulse is output from the CPU 40, the collector voltage Vp further drops significantly due to switching noise. In this case, the pulse processing circuit 6
Since the PNP transistor 52 is switched to the ON state by the switching signal Ss from 0, the current Is is applied as described above. On the other hand, when the level of the collector voltage Vp of the phototransistor PT ₂ decreases significantly, the cathode side of the diode 54 changes to the negative side, and the voltage that changes to the negative side from this anode-cathode voltage Vd (≒0.6V) Correspondingly, a current Id flows as shown in FIG. That is, the diode 54 has a forward Zener voltage value between the base and emitter of the transistor 14.
The base current Ib of the transistor 14 is lower than Vbe by the forward Zener voltage value Vd of the diode 54.
towards a clamp voltage value sufficient to interrupt the
Base voltage of transistor 14 becomes too low
A clamp operation is performed to correct Vb by applying a clamp current Id. Therefore, transistor 1
The base voltage Vb of 4 is increased by the current Is and Id.
It is corrected as shown in FIG. d and held at a predetermined voltage that is higher than its base bias voltage. Therefore, as shown in Figure 3e, the base voltage
Ib flows, and the noise signal N is no longer included in the coordinate signal.

Next, the CPU 40 outputs a pulse signal forming the drive signal Sd, and when the LED ₂ emits light, the phototransistor PT ₂ becomes conductive and its collector voltage Vp falls, so that the base voltage Vb of the transistor 14 also falls. In this case, the current Id flows through the diode 54 due to the clamping operation, as shown in FIG. 3d, and the voltage Vd is corrected.
The falling level of base voltage Vb is clamped (lower end clamp). Furthermore, when the pulse signal forming the drive signal Sd falls and the collector voltage Vp of the phototransistor PT ₂ rises, this rising voltage is applied to the base of the transistor 14 via the coupling capacitor C ₁ by the clamping operation of the diode 54. is applied to raise the base voltage Vb. Therefore, even if the collector voltage Vp level of the phototransistor PT ₂ is lowered, the base current flows through the transistor 14 with a predetermined waveform, so that the output terminal 16
A coordinate signal consisting of pulse signals is output.
Therefore, the CPU 40 side can accurately determine that there is no coordinate input.

Then, when the signal waveform (coordinate signal waveform) of the base voltage Vb of the transistor 14 is shaped by the clamping operation of the diode 54 and the coupling capacitor _C1 in this way, when the period of the optical signal Sp from _LED1 to LEDn is reduced, Even if the signal waveform of the collector voltage Vp of the phototransistors _PT1 to PTn is distorted, the optical signal is always transmitted to the transistor 14.
A base current Ib corresponding to Sp flows. Therefore,
Since the output terminal 16 outputs a coordinate signal consisting of a pulse signal corresponding to the optical signal Sp, the presence or absence of coordinate input can be reliably and accurately detected even when the input device of the present invention is operated at high speed (scanning). be able to.

Here, when the coordinate input operation is performed, for example, the LED ₂ which is a light emitting element and the phototransistor PT ₂ which is a light receiving element are connected to each SW ₂ of a pair of switching circuits 22 and 12.
When the phototransistor PT2 is closed and selected, a photo signal is generated via the switching circuit 12, which is a detection signal when three light pulses are intermittently generated between the LED ₂ and the phototransistor _PT2 , and the light is blocked by a finger or the like. The collector voltage Vp of the transistor PT ₂ is in a state in which the rectangular voltage waveform portion shown as oscillating at three points in the voltage decreasing direction in response to the light pulse of the LED ₂ shown in Figure 3c has been removed. . The collector voltage Vp in a state in which the three rectangular wave components caused by this optical pulse are removed is lower than the operating level of the phototransistor PT ₁ when it does not receive the optical pulses from the LEDs ₁ and ₃ shown in Figure 3c. A state is reached in which the noise signal N generated in the voltage drop direction at the time of switching the light receiving element is synthesized with a voltage component that has relatively little fluctuation due to disturbance light higher than the operating level of the transistor PT ₃ or element variations between phototransistors.

The collector voltage Vp of the phototransistor PT ₂ via the switching circuit 12 when the optical path of this optical pulse is blocked is the capacitor that is the AC coupling means.
The waveform is shaped via _C1 in the following steps.

First, when LED ₂ is connected to SW ₂ in the off state and the switching signal Ss is supplied at low level, the positive power supply terminal Vcc → resistor R ₁ → resistor R according to the low level switching signal Sd. ₂ → The base current Ib that follows the path from the emitter of the transistor 52 to the collector → the base to the emitter of the transistor 14 → the ground line is supplied as a dynamic clamp current Is. When this dynamic clamp current Is is applied, the components of the disturbance light, etc. and the noise signal N are corrected to a constant base voltage Vb that is slightly higher than the forward Zener voltage value Vbe between the base and emitter of the transistor 14. . and,
A collector current continues to be applied to the transistor 14 to which the base current Ib is applied along the path of the positive power supply terminal Vcc, the resistor R ₁ , the resistor R ₂ , the collector of the transistor 14, the emitter, and the ground line. Therefore, the voltage value of the output terminal 16 of the amplifier section 50 becomes low level.

Next, when the LED ₂ is turned on and the switching signal Ss changes from low level to high level, the dynamic clamp current of the transistor 52 is cut off in accordance with the switching signal Ss changed to high level. However, the light pulse from the LED ₂ is blocked by the coordinate input operation, and the collector signal VP of the phototransistor PT ₂ supplied via the switching circuit 12 consists only of components such as disturbance light. The base voltage Vb of the transistor ₁₄ is sufficiently high with respect to the clamp voltage Vd clamped by the diode 54 due to the voltage component of this disturbance light etc. via the capacitor C1 and the base bias voltage via the resistor _R3 . The voltage decreases toward the forward voltage Vbe of the transistor 14. However, the base voltage Vb when no optical pulse is received does not fall below the forward tunable voltage Vbe due to the base bias voltage via the resistor _R3 . Therefore, the base current Ib of the transistor 14
is not blocked by voltage components such as disturbance light. Then, the collector current of transistor 14 continues to be energized, and LED ₂ and phototransistor
During the period when PT ₂ is selected, the voltage output from the output terminal 16 of the amplifier circuit 50 remains at a low level indicating a state in which the optical pulse is cut off and does not change.

Furthermore, since the current Is from the transistor 52 is applied to the base of the transistor 14, excess accumulated carriers exist. Therefore, transistor 1
For example, even if electrical noise intrudes into the base of No. 4, it can be corrected by excess accumulated carriers.
Therefore, the coordinate signal can be accurately detected even in the presence of electrical noise.

In the above embodiment, the PNP transistor 52
An FET can also be used instead. In this case, it is possible to further operate the input device at high speed.

(Effects of the Invention) According to the present invention, when switching the switching circuit that connects the base of the bipolar transistor and the light receiving element array, a predetermined voltage is applied to the base by the switching means, and the coordinates applied to the base of the bipolar transistor are By fixing the signal level to a predetermined level using a clamping means,
Noise signals based on switching noise generated when switching the switching circuit are not included in the coordinate signal, and even if the level at which the light receiving element receives the optical signal changes due to disturbance light, etc., the base of the bipolar transistor remains unchanged. The applied coordinate signal level is held approximately constant. Furthermore, it is also possible to compensate for electrical noise penetrating the base with excess accumulated carriers in the base of the bipolar transistor.
Therefore, it is possible to provide an optical coordinate input device that can accurately send coordinate signals to a personal computer or the like.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the optical coordinate input device according to the present invention, FIG. 2 is a diagram showing the entire device of FIG. 1, and FIG. Diagrams showing signal waveforms of each part, Figures 4 and 5
The figure is a diagram showing a circuit configuration of a conventional optical coordinate input device and signal waveforms of each part thereof. 12, 22...Switching circuit, 14...NPN transistor, 52...PNP transistor, 20...
...Light emitting element array, 30... Light receiving element array, 5
4...Diode, _C1 , _C3 ...Coupling capacitor, _PT1 to PTn...Phototransistor.

Claims (1)

[Scope of Claims] 1. A plurality of light emitting elements, a plurality of light receiving elements arranged in correspondence to receive the optical signals from the light emitting elements, and the light emitting elements emitting light to the light receiving elements to receive the optical signals. a drive circuit that performs a drive operation to supply drive power based on a drive signal in order to blink the light emitting element; and the drive signal of the drive circuit causes the light emitting element to blink.
a first switching circuit that performs a switching operation to select a specific light emitting element only while the light emitting element is blinked at least once; a second switching circuit that switches and selects an element and outputs a detection signal from the light receiving element; an AC coupling means that removes a DC component from the detection signal via the second switching circuit; a bipolar transistor whose base is connected to a coupling means to amplify the detection signal; and a detection signal via the AC coupling means in an undesired state that occurs at the time of switching of the second switching circuit and the time of turning off the light emitting element. pulse processing means for generating a switching signal for correction based on the drive signal; and switching a dynamic clamp current whose maximum value is specified at the base of the bipolar transistor according to the switching signal of the pulse processing means. 1. An optical coordinate input device comprising: dynamic clamping means for energizing during operation and shaping a waveform to a desired constant voltage value. 2. The optical coordinate input device according to claim 1, wherein the dynamic clamp means includes a switching element that performs a closing operation in synchronization with the switching signal, and a switching element that is energized to the switching element. 1. An optical coordinate input device comprising: an impedance element that limits a current value of a mitsu clamp; and an impedance element that limits a current value. 3. In the optical coordinate input device according to claim 1, the AC coupling means is constituted by a capacitive element for AC coupling, and between the capacitive element and the base and emitter of the bipolar transistor for amplification. An optical coordinate input device characterized in that the connected diodes constitute a clamp circuit that is activated when the light emitting element is turned on.