JPS6215625A - Optical coordinate input device - Google Patents

Abstract

PURPOSE:To obtain an accurate coordinate signal by impressing the voltage of a prescribed level to the base of a bipolar transistor in a switch mode of a switching circuit and at the same time fixing the coordinate signal at a prescribed level. CONSTITUTION:When the synchronizing pulses are supplied to switching circuits 12 and 22 from a CPU 40, the collector voltage Vp of a phototransistor PT1 has a fall. Then, a drive signal Sd is supplied to the base of a transistor TR52 from a pulse processing circuit 60 in the form of a switching signal Ss. Thus, the TR52 is turned on and the base voltage of a TR14 is set at a prescribed level Vb. As a result, a base current flows and the collector voltage has a fall and therefore no noise signal is applied to the coordinate signal. Then, the collector voltage of the TR14 has a rise when the signal Sd is supplied to a drive circuit 24 from the CPU 40. Then, the coordinate signal is delivered through a terminal 16.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an optical coordinate input device including a light emitting element array (a) and a light receiving element array.

(Technical Background of the Invention) Optical coordinate input devices include CRT displays and LCDs.
(Liquid Crystal Display) etc., and employs a scanning method in which each light receiving element of a light receiving element array receives an optical signal output from each light emitting element of a light emitting element array. Furthermore, when the optical signal is interrupted by a finger or the like, the position is outputted to a personal computer or the like as indicated coordinates.

FIG. 4 shows a circuit configuration for processing optical signals of a conventional optical coordinate input device. In the figure, numeral 10 indicates a light receiving element array, and this light receiving element array is formed from a plurality of phototransistors PT+ to PTn. The emitters of each phototransistor PT+ to PTn are commonly grounded.

The collector is each switch S W t to S of the switching circuit 12
Connected to Wn. Each switch SW1~SW
n is connected to the base of the NPN transistor 14 via a coupling capacitor C1. The collector of this transistor 14 is connected to the power supply Vc via resistors R+ and Rz.
c is connected, and the output terminal 16 is also connected via a coupling capacitor C3. A power supply Vcc is connected to the base of the transistor 14 via a base resistor R3. A resistor R4 for applying a voltage to the phototransistors FT and -PTn is connected between the resistors RI and R2 via the switching circuit 12. Also, resistor R1
A capacitor C2 is connected between and R2 to bypass fluctuations in the power supply Vcc.

Next, the light reception processing operation of the optical coordinate input device will be explained.

When the synchronization pulse shown in FIG. 5(a) is input to the switching circuit 12, the switch SW is closed, and a voltage is applied to the collector of the phototransistor FT via the resistors R+ and R4. On the other hand, the light emitting element array (not shown) is scanned in response to the input of the synchronization pulse, and the phototransistor P T
The LED corresponding to + emits light. Therefore, since the optical signal Sp from the LED is received by the phototransistor FT, the phototransistor PTI becomes conductive.

When the phototransistor FT becomes conductive, a negative pulse voltage is applied to the base of the transistor 14 via the coupling capacitor C1.
switches to the OFF state and the base current Ib stops flowing, so its collector voltage rises. Therefore, the collector voltage can be taken out from the output terminal 16 as a coordinate signal (see FIG. 5(e)) via the coupling capacitor C3. In addition, the phototransistor F T +
Since the corresponding LED outputs at least two or more optical signals Sp during one scan, the coordinate signal is composed of two or more pulse signals.

Similarly, each time a synchronization pulse is input, the switches SW2 to SWn of the switching circuit 12 are closed, and the phototransistors PTz to PTn receive the optical signal SP from the corresponding LED. A coordinate signal indicating the coordinate position can be obtained continuously. Therefore, if the optical signal is blocked by a finger or the like and, for example, the optical signal is not received by the phototransistor PT3, the coordinate signal will not be output from the output terminal 16. You can know the indicated coordinates.

(Problems with Background Art) Now, light-emitting and light-receiving elements such as the phototransistor F T+ NP T n and the LED that outputs the optical signal Sp have variations in characteristics with respect to the optical signal. Furthermore, the phototransistors FT, -PTn are affected by changes in light intensity from a CRT display, etc., and by external light. For this reason,
The collector voltage Vp of each phototransistor varies greatly.

Therefore, as shown in FIG. 5(b), if the collector voltage Vp of the phototransistor P T 2 decreases significantly due to disturbance light etc. at the time when the photo transistor P T 2 receives the optical signal Sp, the transistor Since the base voltage vb of the phototransistor 14 also decreases as shown in FIG. 5(C), the transistor 14 may be held in the OFF state during the scanning period of the phototransistor P T z. Therefore, as shown in FIG. 5(e), since the coordinate signal remains high, the phototransistor P
Even though Tz is receiving the optical signal Sp, the personal computer or the like incorrectly determines that coordinates have been input.

Furthermore, since a voltage is applied to the base of the transistor 14 via the resistor R3, the coupling capacitor C
A charging current Ic flows into I as shown in FIG. Therefore, when the collector voltage Vp of the phototransistor decreases, P T z and FT (
, −〇, the base voltage v of the transistor 14
The falling level of b increases. However, since the base voltage vb only increases gradually based on the time constant of the resistor R3 and the coupling capacitor C7, if the collector voltage Vp of the phototransistor significantly decreases,
As mentioned above, the coordinate signal remains high.

For example, as shown in FIG. 5(b), if the optical signal Sp is received at the time when the collector voltage Vp of the phototransistor PTz has slightly increased, the transistor 14
Since the base current Ib with a small level may flow or the rising waveform of the base current Ib may be distorted (see the waveform in Fig. 5(d)), it is difficult to determine whether the coordinate signal is output as a pulse waveform or not. Judgment becomes difficult. Therefore, in this case as well, there is a risk that the personal computer or the like will make an erroneous judgment.

Further, at the time when the switch SWI"SWn of the switching circuit 12 is switched by the synchronization pulse, each phototransistor FT is affected by switching noise.

The collector voltage Vp of ~PTn falls instantaneously, and the base voltage vb of the transistor 14 also falls instantaneously. Therefore, when switching the switches SW + ~SWn, the base current Ib of the transistor 14 instantaneously drops. noise signal N to the coordinate signal.
Therefore, there is a possibility that a personal computer or the like will judge this noise signal N as a coordinate signal, which will also cause erroneous judgment.

As explained above, the base-emitter of the transistor 14 acts as a diode and forms a clamp circuit together with the coupling capacitor C1 and the resistor R3, so when the base voltage vb decreases, the voltage vb is kept at a predetermined level. Correct by clamping so that they are aligned.

However, as described above, when the base voltage vb fluctuates significantly due to variations in the optical characteristics of the light emitting and light receiving elements, disturbance light, and switching noise, it is difficult to correct the base voltage vb to a predetermined level Vbl even by a clamp operation. I can't.

If the resistance value of the resistor R3 is set to a small value, a large correction can be made by the clamp operation, but if the resistance value of the resistor R3 is small, the excess accumulated carriers accumulated in the base of the transistor 14 will increase, and the The impedance on the base side decreases, so
The fall and rise of the base voltage vb of the transistor 14 are delayed with respect to the rise of the collector voltage Vp of the phototransistor, and the waveform of the base voltage vb is distorted. Therefore, when scanning the light emitting and light receiving elements at high speed, can also cause misjudgment.

(Object of the Invention) An object of the present invention is to provide an optical coordinate input device that accurately sends coordinate signals without being affected by disturbance light or switching noise.

(Summary of the Invention) The present invention applies a predetermined voltage by a switching means to the base of a bipolar transistor for amplifying and outputting a coordinate signal when switching a switching circuit, and also applies a level of the coordinate signal applied to the bipolar transistor. is fixed at a predetermined level using clamp means.

(Embodiments of the Invention) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the overall configuration of an optical coordinate input device according to the present invention, that is, this coordinate input device includes a light emitting element array 20
The light emitting element array 20, which includes a light receiving element array 30 and a light receiving element array 30, is composed of a plurality of LEDs t to LED n, and is arranged in an L shape in front of the display surface of a CRT display (not shown). Further, the light receiving element array 30 is composed of a plurality of phototransistors PT+ to PTn, and these phototransistors FT+NPTn are LED+
to LEDn, and are arranged in an L-shape at opposite positions on the front surface of the display surface, respectively. LED+NLE
The 7th node side of Dn is connected to each switch of the switching circuit 22, and the driving circuit 24 is connected to the switching circuit 22. A drive signal Sd from the CPU 40 is supplied to the drive circuit 24.

Phototransistors FT, -PTn are connected to an amplifier section 50 via a switching circuit 12. That is, the emitters of the phototransistors P T t to PTn are commonly grounded as shown in FIG.
are connected to the respective switches SW, to SW n. Each switch SW, -SWn is connected to the base of an NPN run shifter 14 via a coupling capacitor C4. A power supply Vcc is connected to the collector of the transistor 14 via resistors R1 and R2.

Further, an output terminal 16 is connected to the collector of the transistor 14 via a coupling capacitor C3.

A coordinate signal Sx1, which will be described later, from the output terminal 16 is input to the CPU 40, as shown in FIG. A power supply Vcc is connected to the base of the transistor 14 via a base resistor R3. A switching circuit 1 is connected between resistors R1 and R2.
A resistor No. 8 for applying voltage to the phototransistors FT and PTn is connected through the phototransistors FT and PTn, and a capacitor C is connected between these to bypass fluctuations in the power supply Vcc.
2 are connected. The emitter and collector of a PNP transistor 52 used as a switching means are connected to the collector and base of the transistor 14, respectively, and the pulse processing circuit 60 is connected to the base of the PNP run shifter 52. This pulse processing circuit 60 uses a drive signal S output from the CPU 40.
d is input, and the drive signal is held at the "L" level at the time of input of the synchronization pulse output from the CPU 40, so this drive signal Sd is used as the switching signal Ss.
is supplied to the base of the PNP transistor 52 as a signal. Furthermore, a diode 54 is connected to the base of the transistor 14.
The cathode side of is connected. The anode side of this diode 54 is grounded, and together with the coupling capacitor C1, it constitutes a lower end clamp circuit.

Next, the operation of the optical coordinate input device according to the present invention will be explained with reference to the waveform diagram of FIG.

First, when a synchronizing pulse from the CPU 40 (see FIG. 3(a)) is input to the switching circuits 12 and 22, the switching circuit 1
2 switch S W + and switching circuit 22 L E D
Since the switch corresponding to + is closed, the collector voltage Vp of the phototransistor P T I is changed to
As shown in C), it falls momentarily due to switching noise. On the other hand, at the time when the synchronization pulse is input to the switching circuit, the drive signal Sd is held at the "L" level, and the synchronization pulse is simultaneously input to the pulse processing circuit 60. Therefore, from the pulse processing circuit 60, the "L" level drive signal Sd is supplied to the base of the PNP run shifter 52 as a switching signal/signal Ss only from the fall of the synchronizing pulse to the rise of the drive signal Sd. Since the transistor 52 is turned on, a voltage is applied to the base of the transistor 14 via the resistors R1, Rz, and the emitter and collector of the run shifter 52 (PNP), and a current Is flows as shown in FIG. Therefore,
As shown in FIG. 3(d), the base voltage vb of the transistor 14 is determined from a predetermined voltage, that is, a base bias voltage set by the base-emitter voltage Vbe (=0.6V) of the transistor 14 and the resistor R3. is also held at a slightly higher voltage. As a result, as shown in FIG. 3(e), the base current Ib (the waveform shown by diagonal lines) flows through the transistor 14, and its collector voltage falls, so that the coordinate signal is shown by the broken line in FIG. 3(f). The noise signal N shown in FIG.

Next, a drive signal Sd consisting of three pulse signals is output from the CPU 40, and when this drive signal is supplied to the drive circuit 24, the LED+ is driven and three optical signals Sp are output. Transistor FT receives these optical signals and becomes conductive. That is, the resistors R1, R, the switch SW, and the collector of the phototransistor PTI.
Current flows through the emitter and the phototransistor FT
.

The collector voltage Vp falls continuously in a pulsed manner.

Therefore, three negative pulse voltages (the third
(see FIG. 3(d)), the base current Ib falls continuously in a pulsed manner as shown in FIG. 3(e).

Therefore, the collector voltage of the transistor 14 rises, and a coordinate signal consisting of three pulse signals is output from the output terminal 16. The CPU 40 counts pulses upon input of this coordinate signal and obtains a predetermined number of "3", so it determines that there is no coordinate input.

The collector voltage Vp of the phototransistor P T 2 to be scanned next decreases due to its characteristics and disturbance light (third
(see figure (C)), when the synchronization pulse is output from the CPU 40, the collector voltage Vp further drops significantly due to switching noise. In this case, the PNP transistor 52 is switched to the ON state by the switching signal Ss from the pulse processing circuit 60, so that the current Is is applied as described above. On the other hand, when the level of the collector voltage Vp of the phototransistor FT decreases significantly, the cathode side of the diode 54 changes to the negative side, and the voltage Vd between the seven nodes and the cathode changes.
As shown in FIG. 1, a current Id flows in response to the voltage that changes to the negative side from (0.6V). That is,
The diode 54 performs a clamping operation. Therefore, the base voltage vb of the transistor 14 is corrected by the currents Is and Id as shown in FIG. 3(d), and is maintained at a predetermined voltage higher than the base bias voltage. Therefore, as shown in FIG. 3(e), the base current Ib flows, and the noise signal N is no longer included in the coordinate signal.

Next, when the CPU 40 outputs a pulse signal forming the drive signal Sd and the LEDz emits light, the phototransistor P T 2 becomes conductive and its collector voltage Vp falls, so that the base voltage vb of the transistor 14 also falls. In this case, as shown in FIG. 3(d), the current id flows through the diode 54 due to the clamping operation and the voltage Vd is corrected, so that the falling level of the base voltage vb is clamped (lower end clamp). Furthermore, when the pulse signal forming the drive signal Sd falls and the collector voltage Vp of the phototransistor P T z rises, this rising voltage is applied to the base of the transistor 14 via the coupling capacitor C1 by the clamping operation of the diode 54. is applied to raise the base voltage vb. Therefore, even if the collector voltage Vp level of the phototransistor P T 2 is lowered, the base current flows through the transistor 14 with a predetermined waveform.
A coordinate signal consisting of three pulse signals is output from the output terminal 16. Therefore, the CPU 40 side can accurately determine that there is no coordinate input.

When the signal waveform (coordinate signal waveform) of the base voltage vb of the transistor 14 is shaped by the clamping operation of the diode 54 and the coupling capacitor C+ in this way, the period of the optical signal Sp from LED+ to LEDn is reduced. In case of phototransistor FT, NPT
Even if the signal waveform of the collector voltage Vp of n is distorted, the base current Ib corresponding to the optical signal Sp always flows through the transistor 14.

Therefore, since a coordinate signal consisting of a pulse signal corresponding to the optical signal Sp is output from the output terminal 16, even if the input device of the present invention is operated at high speed (scanning), the presence or absence of coordinate input can be detected reliably and accurately. can be detected.

Further, a transistor 52 is connected to the base of the transistor 14.
Since more current Is is applied, there are excess accumulated carriers. Therefore, even if, for example, electrical noise enters the base of the transistor 14, it can be compensated for by excess accumulated carriers. Therefore, coordinate signals can be accurately detected even in the presence of electrical noise.

In the above embodiment, an FET may be used instead of the PNP run shifter 52. In this case, it is possible to further operate the input device at high speed.

(Effects of the Invention) According to the present invention, when switching the switching circuit connecting the base of the bipolar transistor and the light receiving element array, a predetermined voltage is applied to the base by the switching means, and the coordinates applied to the base of the bipolar transistor are By fixing the signal level to a predetermined level using the clamping means, noise signals based on switching noise generated when switching the switching circuit are not included in the coordinate signal, and the optical signal of the light receiving element is not received. Even if the signal level changes due to disturbance light or the like, the level of the coordinate signal applied to the base of the bipolar transistor remains almost constant. Furthermore, electrical noise penetrating into the base can be corrected by excess carrier accumulation in the base of the bipolar transistor. Therefore, it is possible to provide an optical coordinate input device that can accurately send coordinate signals to a personal computer or the like.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the optical coordinate input device according to the present invention, FIG. 2 is a diagram showing the entire device of FIG. 1, and FIG. Figures 4 and 5 are diagrams showing the circuit configuration of a conventional optical coordinate input device and signal waveforms at each part. 12.22----All switching circuits, 14-------NPN) Run shifters, 52--
-1-----PNP) run shifter, 20-------
1 light emitting element array, 30 - 1 light receiving element array 54 , diode, c, , c3 - 1 coupling capacitor, PTI
~PTn---Phototransistor.

Claims (1)

[Claims] a light-receiving element array that is arranged to face the light-emitting element array and receives optical signals from each light-emitting element and outputs coordinate signals;
a switching circuit that switches and connects the light-receiving element array to the light-emitting element in accordance with scanning thereof; and a bipolar transistor whose base is connected to each of the light-receiving elements via the switching circuit and which amplifies and outputs the coordinate signal. , an optical coordinate input device comprising a coupling capacitor coupling the switching circuit and the base of the bipolar transistor, the coupling capacitor being closed when the switching circuit is switched, and applying a predetermined voltage to the base of the bipolar transistor. 1. An optical coordinate input device comprising: a switching means for controlling a base of the bipolar transistor; and a clamping means for fixing a coordinate signal applied to the base of the bipolar transistor at a predetermined level.