JPH0350256U - - Google Patents
Info
- Publication number
- JPH0350256U JPH0350256U JP11087689U JP11087689U JPH0350256U JP H0350256 U JPH0350256 U JP H0350256U JP 11087689 U JP11087689 U JP 11087689U JP 11087689 U JP11087689 U JP 11087689U JP H0350256 U JPH0350256 U JP H0350256U
- Authority
- JP
- Japan
- Prior art keywords
- switch group
- setting
- cpu
- setting switch
- switching control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Input From Keyboards Or The Like (AREA)
Description
図は本考案に係る一実施例の設定スイツチ用ポ
ート回路図である。
図中、１ａ〜１ｎ……ハイインピーダンスデイ
ツプスイツチ、２ａ〜２ｎ……ローインピーダン
スデイツプスイツチ、Ｔｒ１……ＰＮＰトランジ
スタ、Ｔｒ２……ＮＰＮトランジスタ、Ｔｒ３…
…インピーダンス設定用トランジスタ、ＣＰＵ…
…マイクロプロセツサ、ａ〜ｎ……入力ポート、
ＳＥＴ……ポートインピーダンス設定用の出力ポ
ート、ＣＯＮ……スイツチ選択制御用の出力ポー
トである。
The figure is a setting switch port circuit diagram of an embodiment of the present invention. In the figure, 1a to 1n...high impedance deep switch, 2a to 2n...low impedance deep switch, Tr1...PNP transistor, Tr2...NPN transistor, Tr3...
... Impedance setting transistor, CPU...
...Microprocessor, a~n...Input port,
SET: Output port for port impedance setting, CON: Output port for switch selection control.
Claims (1)
回路であつて、 一方の端子がＣＰＵのそれぞれのポートに接続
される第１の設定スイツチ群及び第２の設定スイ
ツチ群と、 コレクタ端子が前記第１の設定スイツチ群のそ
れぞれの他方の端子間を接続するコモンラインに
接続され、ベース端子がＣＰＵのスイツチ群切替
制御ポートに接続され、エミツタ端子が所定電圧
源に接続されたＰＮＰトランジスタと、 エミツタ端子が前記第２の設定スイツチ群のそ
れぞれの他方の端子間を接続するコモンラインに
接続され、ベース端子がＣＰＵの前記スイツチ群
切替制御ポートに接続され、コレクタ端子が所定
電圧源に接続されたＮＰＮトランジスタとを備え
、 前記ＣＰＵのスイツチ群切替制御ポートがハイ
レベルのとき前記ＮＰＮトランジスタに接続され
た前記第２の設定スイツチ群の設定状態を読み込
み可能とするとともに、前記ＣＰＵのスイツチ群
切替制御ポートがロウレベルのときＰＮＰトラン
ジスタに接続された前記第１の設定スイツチ群の
設定状態を入力可能に構成することを特徴とする
設定スイツチ用入力ポート回路。[Claims for Utility Model Registration] An input port circuit for setting switches for the operating state of a CPU, comprising a first setting switch group and a second setting switch group, one terminal of which is connected to each port of the CPU. , the collector terminal is connected to a common line connecting the other terminals of each of the first setting switch group, the base terminal is connected to the switch group switching control port of the CPU, and the emitter terminal is connected to a predetermined voltage source. The PNP transistor has an emitter terminal connected to a common line connecting the other terminals of each of the second setting switch group, a base terminal connected to the switch group switching control port of the CPU, and a collector terminal connected to a predetermined setting switch group. and an NPN transistor connected to a voltage source, the setting state of the second setting switch group connected to the NPN transistor can be read when a switch group switching control port of the CPU is at a high level, and the setting state of the second setting switch group connected to the NPN transistor can be read. An input port circuit for a setting switch, characterized in that the setting state of the first setting switch group connected to a PNP transistor can be input when a switch group switching control port of a CPU is at a low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11087689U JPH057642Y2 (en) | 1989-09-25 | 1989-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11087689U JPH057642Y2 (en) | 1989-09-25 | 1989-09-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0350256U true JPH0350256U (en) | 1991-05-16 |
| JPH057642Y2 JPH057642Y2 (en) | 1993-02-25 |
Family
ID=31659382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11087689U Expired - Lifetime JPH057642Y2 (en) | 1989-09-25 | 1989-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH057642Y2 (en) |
-
1989
- 1989-09-25 JP JP11087689U patent/JPH057642Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH057642Y2 (en) | 1993-02-25 |
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