JPH0349448A - Inter-processor communication equipment - Google Patents

Abstract

PURPOSE:To realize high speed communication between processors with less hardware by utilizing the result of count at data frame transmission and reception of a reply frame with a frame counter by reception buffer capacity. CONSTITUTION:A data frame transmission processor 1 in a means recognizing a busy state of a reception buffer of an opposite processor coupled with a bit serial transmission line is provided with a frame counter 112 by the capacity of a reception buffer of a data frame receiver side processor which is incremented by 1 at data frame transmission and decremented by one at the reception of a reply frame and recognizes the reception buffer state at the data frame receiver side depending on the count. On the other hand, a data frame receiver side processing 108 returns a reply frame automatically with the end of frame processing. Thus, the opposite reception buffer state is managed easily with less hardware and step number of the microprogram and the communication at fast speed between processors 1 is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is utilized as a communication means between microprogram control processing devices connected via a bit serial transmission path. In particular, the present invention relates to busy recognition management means for a reception buffer on the other side receiving an information frame.

〔overview〕

The present invention utilizes the results of counting when transmitting data frames and when receiving reply frames using a frame counter corresponding to the capacity of the receiving buffer as a means for recognizing the busy state of the receiving buffer of a processing device on the other side connected via a bit serial transmission path. By doing so, high-speed communication between processing devices can be realized with a small amount of hardware.

[Conventional technology]

In general, in communication between processing devices controlled by a microprogram, when one processing device sends information to another and then sends new information, the processing device on the information receiving side is in a receivable state. You have to make sure that. This is because the time required for the information receiving processing device to be able to receive the next information is not constant depending on the type of received information or the state at the time of reception. Conventionally, between processing devices that are connected by a bit serial interface and communicate by sending and receiving frames, (1) the information sending processing device assumes that the receiving buffer of the other party is in a busy state when it sends an information frame. On the other hand, the information receiving side processing device receives the information frame and returns a reply frame after completing the processing of the information frame. After that, when the information sending side processing device receives a reply frame, it considers that the receiving buffer busy state of the other side has been released; and (2) a structure in which the receiving buffer of the information receiving side processing device can store multiple information frames. When the number of data frames in the receive buffer exceeds a certain value (determined by the delay time of the transmission path and the capacity of the receive buffer 7), the information receiving side controller sends a buffer busy status notification. Send L...-frame and write data frame in the receive buffer.
- When the number of frames falls below a certain value, a frame notifying the buffer 7 free state is sent out, and the information sending processing device manages the receiving buffer state of the information receiving processing device by receiving two types of frames. was taken.

[Problems to be Solved by the Invention] However, in (1) of the conventional example, the reply frame is not returned until the receiving processing device finishes processing the information frame in the reception buffer, so this time is used as is for communication. There are disadvantages that cause the rate to decrease, and (2) has the disadvantage that the control is complicated and the amount of metal objects and the number of microprogram steps increase.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks, and provides an inter-processing unit reply device that can suppress a drop in reply rate due to the time required to return a reply frame with a simple structure. .

[Means for solving problems]

The present invention provides processing included in a pair of processing devices that includes a control means for microprogram-controlling the own device and a transmitting/receiving means for transmitting and receiving frame data having a data length shorter than a predetermined data length via a bit serial transmission path. In an inter-device communication device, a storage means capable of retaining a predetermined number of frames arriving at the own device, a counter capable of counting the number of frames when the predetermined number of frames are taken, and a counter counter that can count the number of frames that arrive at the device, each time frame data is transmitted to the other device. a first counter control means for incrementing the first counter control means, a reply sending means for sending a reply frame pattern to the other device each time the processing of one frame is completed, and a first counter control means for decrementing the counter means each time the own device receives a reply frame. The apparatus is characterized in that it includes a second counter control means, and the control means includes means for prohibiting transmission of frame data from its own device when the counter means counts the predetermined number.

[Effect]

In this system, predetermined data is transmitted via a first transmission path and a second transmission path that interconnect a first processing device and a second processing device that are controlled by a microprogram and perform bit serial transmission. Frames of less than or equal to this length are transferred to each other.

Up to N information frames from the first transmission path are sent to the second processing device.
A first reception buffer that can store up to ' (N is a natural number) and a first count that can count up to N are provided in the first processing unit, and information is sent to the first transmission path by an information frame transmission instruction from the microprogram of the first processing unit. At the same time, the first counter is incremented by 1. A live frame is sent to the second transmission line in response to an instruction to complete one frame processing of the microprogram of the second processing device. When the first processing device receives the reply frame, the first counter is decremented by one. When the value of the first counter is N, it is displayed to the first microprogram as a first reception buffer busy state.

In addition, the first processing device is provided with a second reception buffer that can store up to M (M is a natural number) information frames from the second transmission path, and the second processing device is provided with a second counter that can count up to M. An information frame is sent to the second transmission path according to an information frame transmission instruction from the microprogram of the processing device, and the second counter is incremented by 1.An information frame is sent to the first transmission path according to an instruction to complete processing of one frame from the microprogram of the first processing device. Sends the frame. When the second processing device receives the live frame, the second counter is decremented by 1. When the value of the second counter is M, the second reception buffer is busy for the second microprogram. Display as status.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are diagrams of a data processing system that includes an embodiment of the present invention. In this embodiment, as shown in FIGS. 1 and 2, processing device 1 and processing device 2 are connected by bit serial transmission paths 1161 and 216l. The processing device 1 is controlled by a microprocessor 110 and includes a serial-to-parallel converter 101, a parallel-to-serial converter 1i6, a receive buffer 108 capable of storing four frames, and a transmit register 111.

Furthermore, the processing device 2 has a similar structure. That is, in this embodiment, the microprocessor 110 (210), which is a control means for microprogram-controlling the own device, and frame data having a data length shorter than a predetermined data length are exchanged via a bit serial transmission path. Serial-to-parallel converter 101 (201) as a transmitting/receiving means
, a receiving buffer 108 (208), which is a storage means that is included in a pair of processing devices 1 (2) equipped with a parallel-serial converter 116 (216>) and can hold a predetermined number of frames arriving at the own device; A frame counter 112 (2
12) A write counter 107 (207), which is a first counter control means that increments the counter means each time frame data is transmitted to the other device, and a reply frame pattern to the other device each time the processing of one frame is completed. The selector 113 (21
3) The self-device includes a reading output counter 106 (206>) which is a second counter control means for decrementing the counter means each time it receives a reply frame, and the control means includes:
The apparatus includes means for prohibiting transmission of frame data from the own device when the counter means counts the predetermined number.

Next, the operation of transmitting an information frame from the processing device 1 to the processing device 2 will be explained. Frame data to be sent is outputted from the microprocessor 110 through a signal line 1102, and is written into the transmission register 111 in response to a control signal on a signal line 1103. After that, a frame transmission instruction is sent from the microprocessor 110 through the signal line 1104, and the frame data in the transmission register 111 is sent to the signal line 1ll1, the selector 113, and the signal line 1.
131 to the parallel-to-serial converter 116, and at the same time the frame counter 112 is incremented. The output of the frame counter 112 is used by a busy detection circuit 114 to determine whether or not the data frame can be sent, and this determination result is sent to the microprocessor through a signal line 1141.
Recognized at 10. Here, the frame counter 112 is a counter that can count up to a maximum value of 4, and indicates the number of transmitted data frames waiting for a corresponding reply.

That is, it represents the apparent number of data frames in the reception buffer 208, and when the value is 4, it is assumed that the other party is in a busy state. The frame data taken into the parallel-serial converter 116 is converted into a bit-serial signal and sent to the processing device 2 through the bit-serial transmission path 1161. On the other hand, on the processing device 2 side, the signal sent through the bit-serial transmission line 1161 is taken into the serial-parallel converter 201, where it is converted to parallel data, and the signal is sent to the reception buffer 201 through the signal line 2012.
8 and also sends out a frame reception signal through the signal line 20l1. Data is taken into the reception buffer 208 by the frame reception signal, and the write counter 2
07 is incremented. As the write counter 207 is incremented, the receive buffer valid state is recognized by the microprocessor 210 through the signal line 209l from the receive buffer valid detection circuit 209 which detects the difference between the write counter 207 and the read output counter 206. The microprocessor 210 connects the signal line 203 when the reception buffer is valid and reception processing is possible.
1 to read one frame data in the receive buffer. After that, the microprocessor 210 connects the signal line 21 to the signal line 21 when the read frame data is no longer needed.
A frame processing completion instruction is issued through 0l, and this signal increments the read output counter 206. At the same time, the libri frame pattern is taken into the parallel-to-serial converter 216 through the selector 213, and then converted into a bit serial signal. Bit serial transmission line 216
1 to the processing device 1. Here, if a plurality of frame data exist in the reception buffer 208, even if the readout counter 206 is incremented by the frame processing completion instruction from the microprocessor 210, it will not match the value of the write counter 207, so the signal line 2091
continues to indicate the receive buffer valid state, and the microprocessor 210 repeats the read process if the receive process is possible. The processing device 1 side, which receives the live frame through the bit serial transmission line 2161, converts it into parallel data in the serial parallel converter 101 and outputs it to the common code line 1012 in the same way as when receiving the information frame, and also transmits the frame to the signal line 1011. Send out the received signal. signal line 10
The data output of No. 12 is compared with the reply frame pattern by the comparator 102, and in this case, since they match, the AND gate 104 inhibits the increment of the write counter 107 and the loading of the frame data into the receive buffer 108, and instead Frame counter 112 is decremented through gate 105.

During the above operations, after the processing device 2 receives the data frame, the microphone processor 210 enters the receive buffer valid state! ! 2 Time to consciousness and microprocessor 2
The time from when 10 recognizes the valid state of the receive buffer until it issues an instruction to complete frame processing is arbitrary. This means that even if the microprocessor 210 is performing other controls unrelated to frame reception, the frame reception processing can be delayed until the control is completed, and furthermore, there is no time restriction on the frame reception processing. do. On the other hand, the microprocessor 110 on the processing device I side can send up to four data frames in advance regardless of the processing time on the processing device 2 side and the delay time of the transmission lines 1161 and 2161. Furthermore, if the reply frame returns within that time, data frames can be sent out continuously, and the processing time on the processing device 2 side becomes invisible due to the communication rate.

Although this explanation is for transmitting an information frame from processing device 1 to processing device 2, similar operations are performed when transmitting an information frame from processing device 2 to processing device 1.

〔Effect of the invention〕

As explained above, the present invention provides a data frame sending processing device with a frame counter equal to the reception buffer capacity of the data frame receiving processing device, increments it by +1 when a data frame escapes, and -1 when a live frame is received. , the reception buffer status on the data frame receiving side is recognized based on the value, and on the other hand, the data frame receiving side processing device automatically returns the live frame upon completion of frame processing, so it is easy to use with a small amount of hardware and the number of microprogram steps. This has the advantage of being able to manage the receiving buffer status of the other party and realizing high-speed communication between processing devices.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the structure of an embodiment of the present invention. 1, 2... Processing device, 101, 201... Serial parallel converter, 102, 202... Comparator, 10
3, 203...Knot Gate, 104, 105
, 204 , 205 ... and gate, 106 , 2
06...Reading output counter, 107, 20? ...Write counter, 108, 208...Receive buffer, 109
, 209...reception buffer validity detection circuit, 110,
210... microprocessor, 111, 211.
...Transmission register, 112, 212...Frame counter, 113, 213...Selector, 114, 2
14... Busy detection circuit, 115, 215... OR game}-, 116, 216... Parallel-serial converter.

Claims (1)

[Claims] 1. A pair of processing devices equipped with a control means for microprogram-controlling the own device and a transmitting/receiving means for transmitting and receiving frame data having a data length shorter than a predetermined data length via a bit serial transmission path. In the inter-processing device communication device included in the processing device, there is provided a storage means capable of holding a predetermined number of frames arriving at the own device, a counter means capable of counting the number of frames up to this predetermined number, and each time frame data is transmitted to the other device, the counter means a first counter control means for incrementing the number; a reply sending means for sending a reply frame pattern to the other device each time the processing of one frame is completed; and a first counter control means for decrementing the counter each time the own device receives a reply frame. 1. A communication device between processing devices, comprising two counter control means, wherein the control means includes means for prohibiting transmission of frame data from the own device when the counter means counts the predetermined number.