JPH0349318A - Programmable logic device - Google Patents

Abstract

PURPOSE:To offer a programmable logic device having a wide general-purpose application in a way of forming various synchronizing signals used for an electronic instrument or the like by providing plural counters using an AND output formed through programming an optional product term line as its clock input, and wired to supply its output to a proper input signal line of an AND matrix. CONSTITUTION:Output contacts of counters CR1-CRn are connected to prescribed input signal lines b1-bn of an AND matrix and each clock signal input contact connects to prescribed product term lines F1-Fn. Furthermore, plural output circuits transferring an AND output obtained functionally by programming a grating point of other product term lines of the AND matrix via an AND matrix programmed in advance are formed. Thus, various synchronizing signals with different frequency, phase and waveform are very easily generated by having only to connect the counters in cascade through the proper program of the grating point of the product term lines.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is a programmable logic device that allows circuit designers to easily incorporate their own circuit specifications.
In particular, the present invention relates to a programmer full logic device suitable for generating various synchronization signals used in video equipment, etc.

[Conventional technology]

As is well known, programmable logic devices can realize an appropriate logic circuit with an AND-OR two-stage configuration by programming each lattice point of the AND matrix and the OR matrix, and are highly versatile. It is an excellent device in terms of

Conventionally, a programmer full logic device having a configuration as shown in FIG. 6 has been common. That is, in the same figure, the input signal is composed of a group of vertical lines in the figure.

A product term line consisting of a group of horizontal lines arranged to intersect ~L1 and these input signal lines! 1~! and a logical product matrix that realizes an arbitrary logic circuit by appropriately programming the grid points formed at each of these intersections, and a logical product output (see FIG. It includes an OR matrix (functionally shown as a multi-input OR gate in the figure) connected through an AND gate (functionally shown as an AND gate). Furthermore, a general-purpose input port for supplying logic signals from the outside to some input line groups of the input signal lines ~L, a clock input terminal for supplying clock signals, and a clock input terminal for supplying control signals. Control signal input terminals and the like are provided. An output port is formed for outputting the output signal of the OR matrix (multi-input OR gate in the figure) to the outside.

To represent the output circuit related to the output terminal PI of the output port, the logical sum (indicated by ORI in the figure) output is D.
It is connected to a data input contact of a type flip-flop FFI, and its output contact Q is connected to an output terminal P1 via an output buffer circuit B1. Also, flip-flop FFI
The clock input contact of B1 is wired so that the clock signal from the clock input terminal is supplied via the input buffer circuit, and the output buffer circuit B1 outputs the clock signal according to the logic level of the control signal supplied from the control signal input terminal. Transfers the output signal of the flip-flop FFI to the output terminal P1 or puts it in a high impedance state. Furthermore, the inverted output Q of the flip-flop FFI is connected to an input signal line via a buffer circuit FBI.

~L, is wired so as to feed back to some of the input line groups. The output circuits related to the remaining output terminals P2 to Pk also have a similar configuration, and for example, these output circuits have a cell structure.

For example, when a conventional programmable logic device having such a configuration is used to realize a signal generation device for generating various synchronization signals with different frequencies, phases, and waveforms for use in various electronic devices. By programming the appropriate lattice points of the AND matrix, the flip-flops described above are formed in the output circuit to form a shift register, counter, etc., and at the same time, by feeding back the output to the AND matrix, complex I was trying to form a synchronization signal.

[Problem to be solved by the invention]

However, in such conventional programmable logic devices, a plurality of 1-bit flip-flops provided in the output circuit are used to configure the above-mentioned shift registers and counters, so high-frequency signals and low-frequency signals are There is a limit to the number of bits (number of flip-flops) in order to simultaneously generate signals with different frequencies or multiple types of signals with different waveforms, so it is difficult to realize such a signal generator with a single programmable logic device. It was often difficult. In addition, flip-flops are designed to have the function of registers that temporarily hold output signals and then transfer them to the output terminal, so when applied to shift registers and counters such as those mentioned above, However, since a large number of output terminals are left unused, there is a problem in that the efficiency of using internal resources becomes extremely poor.

The present invention has been made in consideration of these problems, and an object of the present invention is to provide a programmable logic device that is especially versatile in forming various synchronization signals used in electronic equipment and the like.

[Means to solve the problem]

To achieve such an object, the present invention uses a logical product (AND or NAND) output created by programming appropriate product term lines provided in a logical product matrix as a clock input, and outputs a logical product. The configuration includes a plurality of at least one type of arbitrary modulo counters wired so as to be supplied to appropriate input signal lines of the matrix.

Here, it is preferable that the modulo counter is a prime number modulo counter.

Preferably, these modulo counters are Johnson counters.

[Effect]

In the programmable logic device of the present invention having such a configuration, by programming the built-in counters in a cascade connection, it is possible to easily divide the frequency of a reference clock signal etc. supplied from an external source into a plurality of clock signals. It is possible to generate multiple types of synchronization signals, and is effective in integrating synchronization signal generation devices required for electronic devices and the like into a single chip.

Also, the modulo number is 2.3.5, 7. ... By incorporating a plurality of counters set to prime numbers such as songs, it is possible to easily generate a signal of a desired frequency.

Furthermore, by using a Johnson counter, no glitches occur when the internal operating state is reversed, so it is possible to prevent the generation of noise components.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

First, the configuration of the embodiment will be explained based on FIG.
Blocks indicated by symbols CRI to CRn in the figure are suitably modulo counters each composed of Johnson counters. For example, Fig. 2 (A), (B), (D)
, a prime number modulo counter as shown in (E) and a relatively basic counter as shown in FIG. 2(C) are used.

In this example, counters CRI and CR2 are set modulo 2.
Johnson counter, counter CR3゜CR4 is Johnson counter of modulo 3, counter CR5, CR6
, CR7, CR8 are Johnson counters of modulo 5,
Counter CR9CRIO is a Johnson counter of modulo 7, CRII is a Johnson counter of modulo 13,
The last counter CRn is a Johnson counter modulo M (M is an appropriate natural number).

The output contacts (indicated by Q contacts in the figure) of the respective counters CRI to CRn are connected to predetermined input signal lines S, -b of the AND matrix, and the respective clock signal input contacts (indicated by the IN ) is the predetermined product term line F, ~F
7 is connected.

Furthermore, the input signal line a in the AND matrix is a signal line for applying a clock signal of an appropriate frequency from the outside via a clock input terminal, and the external input terminals ■, ~I, The input signal lines C5 to C4 are provided for inputting input signals applied to the input signal through a buffer circuit.

Furthermore, by programming the lattice points of other product term lines in the AND matrix, the AND (ANDN-gate group in the figure) outputs obtained functionally are transferred to the pre-programmed OR matrix (ANDN-gate group in the figure). A plurality of output circuits are formed which forward to the output port via a multi-input OR gate (functionally represented by a multi-input OR gate). Since these output circuits are formed in a cell structure, the output circuit 0UTI related to the output terminal P1
To explain this as a representative example, the wiring is such that the logical sum (indicated by OR1) output is transferred to the output terminal PI via the buffer circuit B1, and the output is transferred to the other buffer circuit I.
It is fed back to the other input signal line e1 of the AND matrix via VI. The output terminals related to the other output terminals P2 to Pr have a similar configuration and are wired so that the output signals of the respective circuits are fed back to the other input signal lines e2 to er.

And these input signal lines a, b, ~b.

Product term lines F, -F, and other product term lines mentioned above are provided to intersect with CI"" CJ l e I"" e r, and lattice points formed at their respective intersections are programmed. is configured to do so.

Note that the above output circuit may be a circuit similar to that shown in FIG. 6, and the number of output terminals of the output port may be set as appropriate.

Further, this embodiment is implemented as an IC as a semiconductor integrated circuit device.

According to a programmable logic device with such a configuration, by appropriately programming the lattice points of the product term lines, various synchronization signals with different frequencies, phases, and waveforms can be generated extremely easily simply by cascading each counter. can do. In particular, internal elements can be used more efficiently than in the conventional case where a counter is realized by connecting flip-flops for each bit. Furthermore, since each counter can be formed with a high degree of integration, the chip area can be reduced. Furthermore, even when using a reference clock signal obtained from an oscillation element whose oscillation frequency cannot be changed, such as a crystal oscillator, it is possible to easily set a fine division ratio, making it extremely easy to select a crystal oscillator. It becomes easier.

Next, a case in which the programmable logic device of this embodiment is applied to a synchronization signal generating apparatus for generating a synchronization signal for vertical scanning of the NTSC system will be described with reference to FIG.

In FIG. 3, for example, by programming the grid points indicated by X marks in the figure, counters CR5, CR6, C
If R4 and CR9 are connected in sequence and the output signal of counter CR5 corresponding to the final stage is selected to be output to output terminal P9, the clock signal of frequency f, 1111131.5 KHz applied to the clock input terminal is
By dividing the frequency by 25 (=5×5×3×7), a synchronizing signal corresponding to the field vertical scanning frequency of frequency fo=60 Hz can be generated from an appropriate output terminal. Note that this programming method and the frequency of the clock signal are merely examples, and it goes without saying that other selections are possible.

Next, a case in which the programmable logic device of this embodiment is applied to a synchronization signal generation apparatus for generating a synchronization signal for vertical scanning of an HDTV system will be described with reference to FIG.

In FIG. 4, for example, counters CR3, CR4, C
R5, CR6, and CRT are connected in sequence, and the output signal of counter CR7 corresponding to the final stage is connected to output terminal P.
7, the clock signal of frequency fz -67.5KHz applied to the clock input terminal is divided by 1125 (-3X3X5X5X5), and the field vertical scanning frequency of frequency fo = 60Hz is output from the appropriate output terminal. A corresponding synchronization signal can be generated.

Note that this programming method and the frequency of the clock signal are merely examples, and it goes without saying that other selections are possible.

Next, a case in which the programmable logic device of this embodiment is applied to a synchronization signal generator for generating synchronization signals for vertical scanning and horizontal scanning of the NTSC system will be explained in the fifth example.
This will be explained based on the diagram.

In FIG. 5, for example, by programming the lattice points indicated by X marks in the figure, counters CR5, CR9, C
RII and CRI are connected in order, and the counter C
The output signal of R5 is selected to be output to the output terminal P1, and further, CR6 and CRT are selected following the counter CRII.
, CR3, CR11, and CR2 are connected in the order of cascading, and the output signal of counter CR2 is selected to be output to output terminal P2. First, from output terminal P1, the frequency f, which is applied to the clock input terminal, is 14°. 318MHz
A synchronizing signal corresponding to the horizontal scanning frequency of IZ can be generated by dividing the clock signal by 910 (=5X7X13X2) (frequency f□=15.7K), and on the other hand, from output terminal P2, it is applied to the clock input terminal. frequency f
,=14.318MHz clock signal 477750
(=5X7X13X5X5X3X7X2) It is possible to generate a synchronization signal corresponding to the frame vertical scanning frequency of the divided frequency fv=30Hz. Note that this programming method and clock signal frequency are just examples, and it goes without saying that other selections are possible.You can also apply an appropriate signal from a general-purpose input port, or feed back an output signal from the output circuit side. By programming it to
Furthermore, it is possible to form signals with complex waveforms, and to
You can perform complex @adjustments such as

〔Effect of the invention〕

As explained above, according to the present invention, the logical product (AND or NAND) output created by programming appropriate product term lines provided in the logical product matrix is used as the clock input, and the output is the logical product of the logical product matrix. Since the configuration is equipped with a plurality of counters of at least one type of arbitrary modulo that are wired so as to be supplied to appropriate input signal lines, by programming the built-in counters in a cascade connection, it is possible to supply signals from the outside. It is possible to easily generate a plurality of multiple Ll 14 type synchronization signals by frequency-dividing the reference clock signal, etc., which is effective in creating a single-chip synchronization signal generation device required for electronic equipment and the like. Also, the modulo number is 2.3, 5, 7. By incorporating a counter set to a prime number such as -1-, it is possible to efficiently generate a signal of a desired frequency.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the configuration of an embodiment of the present invention; Fig. 2 is a circuit diagram showing an example of the configuration of a counter in the embodiment; Fig. 3 is a usage explanatory diagram showing a first concrete example using the embodiment. ; Fig. 4 is a usage explanatory diagram showing a second specific example using the embodiment; Fig. 5 is a usage explanatory diagram showing a third specific example using the embodiment; Fig. 6 is a conventional configuration showing a conventional example. It is an explanatory diagram. F1~F,,; Product term line 11~! ,; Input terminal P1~Pr; Output terminal code in diagram: CR1~CRn; Counter a+ bl ""bn + C+ ~ Cj +81
"" e r: Input signal line (D) t5-A No. (C)

Claims (2)

[Claims] (1) In a programmable logic device that configures an arbitrary logic circuit by programming lattice points of product term lines provided in an AND matrix, programming appropriate product term lines provided in the AND matrix. A plurality of arbitrary modulo counters of at least one type are provided, each of which is wired to take the logical product (AND or NAND) output produced by the above as a clock input and supply the output to an appropriate input signal line of the logical product matrix. A programmable logic device characterized by: (2) In the programmable logic device according to claim (1), the modulo counter is a prime number modulo counter.