JPH0349241A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify manufacture by a method wherein a region for generating electron (hole) gas is regulated by using ion implantation. CONSTITUTION:With a molecular beam crystal growth apparatus, an undoped AlGaAs layer 12 and an undoped GaAs protective layer 13 are formed on an semi-insulating GaAs substrate 11. Then, the substrate 11 is moved into an focused ion beam apparatus with vacuum maintained. Then Si<++> ions being n-type dopant are injected into the layer 12 to form an injection region 15. The shape of this region 15 corresponds to a region for generating electron gas. Then with vacuum maintained the substrate 11 is returned into the previous apparatus to form an undoped AlGa spacer layer 16, an undoped GaAs channel layer 17 and an n-GaAs cap layer 18 on the layer 13. Then an AlN protective layer is formed on the layer 18 and injected Si is activated with lamp annealing performed. With such manufacture electron gas 19 is generated only in an upper section of the region 15 in the layer 17. Thus resist lithography process can be eliminated in this method.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, more specifically, a method for manufacturing a transistor (device) using electron gas or hole gas. region(
The purpose of the present invention is to provide a method for manufacturing semiconductors that can be produced in stripes, lines, or dots, and that can be manufactured more easily than conventional methods (without the need for resist adhesive paste), and the following steps (A) to (T): ( A) Step of forming an undoped first semiconductor layer on a semiconductor substrate; (B) Step of implanting an n-type or ρ-type dopant into a predetermined region of the first semiconductor layer by ion implantation; (T) First semiconductor layer above,
forming an undoped second semiconductor layer with a semiconductor having a higher electron affinity or a lower sum of electron affinity and Tamana-Lugyganop than the first semiconductor;
The structure is such that low-dimensional electron gas or hole gas is formed in the second semiconductor layer near the interface between the semiconductor layer and the second semiconductor layer.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a transistor (device) using electron gas or hole gas.

(Prior art) GaAs-based HEMT (high electron mobility transistor) is known as a device that uses two-dimensional electron gas (for example, Abe, three-phase, near fi: HEMT device, electronic materials, 1987). January issue, pp, 58-63
,reference). A reverse HEMT structure has also been proposed, in which an undoped GaAs channel layer is stacked on a Si-topped A I GaAs electron supply layer.

In the case of a GaAs/AI GaAs-based inverse structure HEMT, it is manufactured as follows. First, as shown in FIG. 2A, a semi-insulating GaAs substrate 1 is coated with an MBE method.
e to n- by epitaxial growth method such as CVD method.
GaAs electron supply layer 2, non-doped AI GaAs
Spacer layer 3, non-doped GaAs channel layer 4, n
- Laminating a GaAs cap layer 5. Next, a resist layer 6 having a predetermined pattern is formed in accordance with a conventional gluing process for isolation between elements in the active region. Then, as shown in FIG. 2B, the portions not covered with the resist layer 6 are removed up to the n-A I GaAs layer 2 by etching. Instead of this etching process, the element M (isolation) region can also be formed by ion implantation of oxygen (0°) using the resist layer 6 as a mask.

Next, source and drain electrodes are formed, a gate electrode is formed, and two electrodes are formed near the lower interface of the GaAs channel layer 4.
An inverse) IEMT that generates a dimensional electron gas 7 is obtained.

[Problems to be Solved by the Invention] As described above, conventionally, the two-dimensional electron gas generation region (that is, the active region) has been defined by etching processing or ion implantation processing through a resist coating process. , These series of tasks are time-consuming, and
Miniaturization is limited by lithography precision and etching (ion implantation) control.

An object of the present invention is to produce a semiconductor manufacturing method that can generate electron gas (or hole gas) in a predetermined area (stripe, stripe, or dot) with high precision, and that can be manufactured more easily than before (without the need for resist glue and glue failure). The goal is to provide the following.

[Means to solve the problem]

The above purpose is achieved by the following steps (a) to (t): (a) forming an undoped first semiconductor layer on a semiconductor substrate;
(b) A step of implanting an n-type or ρ-type dopant into a predetermined region of the first semiconductor layer by the ion implantation method;
forming an undoped second semiconductor layer on the semiconductor layer using a semiconductor having a larger electron affinity or a smaller sum of electron affinity and energy gap than the first semiconductor;
This is achieved by a method of manufacturing a semiconductor device comprising: forming a low-dimensional electron gas or a hole gas in the second semiconductor layer near the interface between the first semiconductor layer and the second semiconductor layer.

Preferably, the dopant ion implantation is performed using a focused ion beam, and the dopant implantation region can be formed only in a predetermined region (fine region) with high precision without forming a resist mask by ordinary lamination lithography. Then, we define this dopant implanted region as (two-dimensional), a line (-dimensional), and a point (
(0 dimension), it is possible to generate electron gas (hole gas) in a shape corresponding to the shape.

It is desirable to perform a series of steps of forming the first and second semiconductor layers on the semiconductor substrate and implanting ions in an ultra-high vacuum without breaking the vacuum.

In this way, impurities (oxygen, carbon, etc.) that adhere to the surface (especially the surface of the first semiconductor layer) during the process are reduced as much as possible, and the interface between the first and second semiconductor layers is cleaned.
As a result, the adverse effects of attached impurities on device characteristics can be suppressed.

The material composition of semiconductor devices is GaAs /^l G
aAs system, InGaAs/ lnA Q As system,
It can be manufactured using a 1nGaAs/GaAsSb system, an InAs/GaSb system, or the like.

When an n-type dopant is implanted into the first semiconductor layer, the electron supply region 6a becomes an electron supply region 7, and the second semiconductor layer is made of a semiconductor having a higher electron affinity than the semiconductor of the first semiconductor layer. On the other hand, when a p-type dopant is used, the injection region becomes a hole supply region, and the second semiconductor layer is made of a semiconductor having a smaller sum of electron affinity and electron affinity than the first semiconductor layer.

[Function] Conventionally, an undoped channel layer is formed on the entire surface of a doped electron (hole) supply layer, so two-dimensional electron (
Hole) gas will be generated over the entire surface of the channel layer,
The generation area is defined by etching removal or ion implantation. In contrast, in the present invention, non-doped electrons (
(Ball) Ions are selectively implanted into the supply layer to define the generation region. If selective ion implantation is performed with a focused ion beam, the fineness of the beam can be used to achieve high precision.
An arbitrary shape of the implanted (doped) region can be created under computer control, and a desired electron (hole) gas generation region can be obtained accordingly.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of embodiments with reference to the accompanying drawings.

1A to 1C are schematic cross-sectional views of a semiconductor device (reverse structure+1EMT) for explaining the manufacturing process according to the present invention, and are in the case of a GaAs/AI GaAs system.

First, as shown in FIG. 1A, a semi-insulating GaAs substrate l
1, undoped A j! o, zGao, ffn5 layers (first semiconductor layer, thickness: 600r+m) 12 followed by undoped GaAs protective layer (thickness: 1.5 nm) 13
is formed epitaxially.

Although this protective layer 13 may not be necessary in principle, A I
It has the function of preventing impurity adsorption to GaAs.

Next, the F
The GaAs substrate is moved into the IB (single bundle ion beam) device while maintaining the By state. At the FlB device, the first
As shown in Figure B, the SIo" ion, which is an n-type dopant, is heated to 72 XIO" cm-2 at an energy of 80 keV.
The injection region 15 is formed by injecting into the Al GaAs layer 12 at a dose of 1'. The shape of this injection region 15 corresponds to the electron gas generation region (active region), and although it is striped (two-dimensional and narrow in width) in FIG. 1B, it can be made into a linear shape (narrow and close to one-dimensional). I can do it.

After the ion implantation, GaAsJl was added while maintaining the vacuum state.
(Return the temporary If into the MBE apparatus. On the GaAs protective layer 13, as shown in FIG. 1C, an undoped A 1 o
, , ,Gao, 78S spacer layer (thickness: 17n
m) 16 is an undoped GaAs channel layer (second
Semiconductor layer, thickness: 50 nm) 17, followed by n-G
aAs +7 layers (1 x 10"cm-', thickness: lo
onm) 18 is epitaxially formed. Although the spacer layer 16 may not be necessary in principle, it has the function of further increasing electron mobility. This spacer layer is 81 o, 1G
If we create a superlattice structure of ao, Js and GaAs, S1
It has the additional effect of suppressing diffusion. The growth temperature (substrate heating temperature) of the spacer layer 16, channel layer 17, and cap layer 18 is kept constant at 540°C.

The reason for setting the temperature low in this way is to suppress the diffusion of the implanted Si.

Next, an IN protective layer (thickness:
10100n is formed, and lamp annealing is performed at 1000°C for 6 seconds to activate the implanted Si.

The Aj2N layer has the function of preventing As from volatilizing. Then, according to the usual process, source and drain electrodes (^nGe/^n) are formed on the GaAs cap layer 18, alloyed annealed, and gate electrodes (TiPtAn or AA) are formed on the GaAs channel layer 17. Form. In the inverted structure 11EMT manufactured in this manner, electron gas 19 is generated in the GaAs channel layer 17 only above the injection region Mirs in its lower part.

In the embodiment described above, the n-type dopant is /r, but when helium ions, which are the p-type dopant, are implanted, the manufacturing process is similar to that described above except for forming the p-GaAs cap layer. Reverse structure that generates hole gas)! EMT is obtained.

(Effects of the Invention) As described above, according to the present invention, the region where electron (hole) gas is generated can be precisely and precisely defined using a focused ion beam, and the conventional resist lithography process can be omitted. Semiconductor devices can be manufactured. Then, a narrow two-dimensional electron gas, a linear one-dimensional electron gas, and even a dot-like zero-dimensional electron gas can be formed.

[Brief explanation of drawings]

1A to 1C are schematic cross-sectional views of a semiconductor device in a process according to the method of manufacturing a semiconductor device according to the present invention, and FIGS. 2A and 2B are a conventional reverse structure) IEMT mold structure. FIG. 1 is a schematic cross-sectional view of a semiconductor device in a process. 11... GaAs317i, 12... Non-doped AI GaAs layer (first semiconductor layer), 15... Ion implantation region, 16... Non-doped AI GaAs spacer layer, 1
7...Non-type GaAs channel layer (second semiconductor layer), 18...n-GaAs cap layer, 19...electronic gas. Figure 1A Heat B cause □] 256-

Claims (1)

[Claims] 1. The following steps (a) to (c): (a) forming an undoped first semiconductor layer on a semiconductor substrate; (b) implanting ions into a predetermined region of the first semiconductor layer; (c) Injecting an undoped dopant onto the first semiconductor layer with a semiconductor having a larger electron affinity or a smaller sum of electron affinity and energy gap than the first semiconductor; forming an electron gas or a hole gas in the second semiconductor layer near the interface between the first semiconductor layer and the second semiconductor layer; Method of manufacturing the device.