JPH0348930A - Programmable logic device - Google Patents

Abstract

PURPOSE:To attain the effective use of a chip area by providing (n) FFs cascaded to each other, and AND matrix for a program including the product member lines crossing the inverted and non-inverted output lines of those FFs, and a feedback wiring applied to the first FF. CONSTITUTION:For the FF D1 - Dn, the non-inverted output points Q of the FFs equivalent to the low-order bits are connected to the data input contacts D of the FFs equivalent to the high-order bits respectively together with a clock input contact connected to a clock input terminal Ck. The reset input contacts R and the set input contacts S of the FF D1 - Dn are connected to the terminal of a prescribed product member line. Simultaneously, the functions of AND gates a1 - a2n are obtained from proper grid points. Thus the set and reset signals decoded by an AND matrix 1 are fed back to the FF D1 - Dn. The output contact of a buffer circuit Ba connected to the terminal of a product member line l1 is connected to the data input point D of the first FF D1. Thus the output signal of the matrix 1 is fed back. The proper grid point of the matrix 1 is programmed and a clock signal is applied to the terminal CK. Thus it is possible to obtain a Johnson counter having the 50% duty.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a programmable logic device that allows circuit designers to easily incorporate their own circuit specifications.
In particular, the present invention relates to a programmable logic device for efficiently internally realizing a sequential circuit necessary for a sequential controller, a signal generation circuit, etc.

[Conventional technology]

As is well known, programmable logic devices can realize an appropriate logic circuit with an AND-OR two-stage configuration by programmatically connecting each lattice point of an AND matrix and an OR matrix, and are particularly versatile. It is excellent in that it enriches.

A conventional example has a structure as shown in FIG. That is, in the figure, the respective input signals 11 to 1 are input from the general-purpose input ports.

buffer circuits 81-B that invert and non-invert and output;
input signal line L A I of the AND matrix l via
``L A j , L I + '''' L l j , and the AND matrix 1 includes input signal lines L r+ to L yw , which are supplied with feedback signals from the output circuit side, which will be described later. Furthermore, the terminals of the product term lines 1.-1. which intersect with these signal lines are connected to the input signal line group of the OR matrix 2, and these input signal lines The sum term lines gI to g, which intersect with the group, are connected to the respective manual contacts of the flip-flops FF+ to FFk in the output circuit via OR gates ORI to OR.
The output of +""Fh (for example, the inverted output shown in the figure) is fed back to the input signal lines of the AND matrix l, ~L□, L□ ~L□, for example, through buffer circuits F1 to Fk as shown in the figure. ing.

Note that the sum term lines g and ~g shown as thick lines in the figure indicate an arbitrary number of signal line groups, and the OR game) OR, ~O
R has a plurality of manual contacts corresponding to each signal line group. Also, a, ~a, shown as an AND gate
This functionally shows that an AND operation can be obtained when the later-described lattice points (indicated by O marks in Figure 7) are programmed, and an AND gate is separately installed at the end of the product term line. is not being formed.

Then, appropriately program the intersections, or grid points, of the respective signal lines in AND matrix 1 and OR matrix 2 (for a fixed OR matrix in which the grid points are programmed in advance, only the AND matrix). By performing AND operations and OR operations, these matrices 1.2 can function as a decoder, etc., to realize a desired circuit.

[Problem to be solved by the invention]

However, such conventional programmable logic devices have the following problems.

First, conventional built-in flip-flops are mainly used as registers that temporarily hold output signals to be transferred to output ports, so
It is formed within the output circuit as shown in the figure. Therefore,
When these flip-flops are used in sequential circuits,
The output ports that are connected in advance to the output contacts of the flip-flop remain unused, which poses problems in terms of effective use of internal resources and a shortage of output ports.

Furthermore, when connecting these flip-flops using a program to form a binary counter and decoding and outputting each flip-flop output (Q, Q), the output signal of each flip-flop changes from O to 1 at the same time, as is well known. or 1
→ When the value changes to 0, a glitch occurs at the point of change, leading to malfunctions in the circuit.Therefore, there is a problem in that a removal circuit for removing this glitch must also be considered in the design.

The present invention has been made in view of such conventional problems, and is particularly a programmable logic device suitable for realizing a sequential controller, a signal generation circuit, etc., and is a programmable logic device suitable for realizing a sequential circuit that uses many flip-flops. An object of the present invention is to provide a programmable logic device that can effectively utilize chip area even when forming a programmable logic device.

Means for Solving Problem C] In order to achieve such an object, the present invention provides n flip-flops connected in cascade, and a product that intersects with the inverting output line and the non-inverting output line of these flip-flops. It is provided with a logical product matrix for programming including a term line, and wiring for feeding back an appropriate signal generated on the product term line to the input contact of the first flip-flop by program connection.

Note that the present invention does not limit the types of flip-flops, and for example, D flip-flops, JK flip-flops, and other types can be used.

[Effect]

In the programmable logic device of the present invention having such a configuration, a plurality of cascade-connected flip-flops are built in separately from those in a conventional output circuit, and a logical AND operation is performed with these flip-flops. By connecting matrices appropriately using a program, sequential circuits such as Johnson counters, ring counters, and shift registers can be easily formed. Inefficiency of internal resources such as having to implement a sequential circuit can be eliminated.

Furthermore, when decoding each output signal of the Johnson counter, it does not generate glitches like a binary counter, so malfunctions can be eliminated, and
Since a removal circuit or the like for removing this glitch is not required, internal resources can be used effectively.

C Example] An embodiment of the present invention will be described below with reference to the drawings.

First, to explain the basic structure based on FIG. 1, the logical product matrix 1 includes vertical signal lines LXI to LX11+.
LYI〜L Ya + L Al−L Aj +
L II~LllJ, LFI""L□, Lo, ~LDk
and the horizontal product term line f, − which intersects these signal lines.
1 (indicated by thick lines in the figure). Furthermore, the product term line f
, -1° is an arbitrary number of signal line groups.

D1-D7 are D-type flip-flops, each of which has a non-inverting output contact Q connected to signal lines LXI-Lllfi, and an inverting output contact Q connected to signal lines LVI-L77.

81 to Bj are input signals supplied to the general-purpose input port ■1
~I, is a buffer circuit that inverts and non-inverts and outputs, and each output contact is connected to a signal line LAI~1. Aj, 1. □
~ Connected to Lllj.

Signals MAL, v+ to Lrm, and Lot-Lnh are signal lines to which feedback signals from the output circuits MCI to MC2 are supplied.

Then, the intersections between each signal line and the product term, that is, the grid points (indicated by 0 marks in the figure) are connected by program.

Each of the flip-flops D1 to D,1 is connected in cascade by connecting the non-inverting output contact Q of the flip-flop corresponding to the lower bit to the data input contact of the flip-flop corresponding to its upper bit, and A clock input contact C is connected to a clock input terminal CK. In addition, the reset input contact R and set input contact S of each of the flip-flops D, ~D, and l are connected to the terminal end of a predetermined product term line, and appropriate grid points are programmed to form the AND gate in the figure. By obtaining the function as aI”atn, the set signal and/or reset signal decoded by the AND matrix 1 are transferred to the flip-flops D1 to D.
You can now return to fi.

In addition, a buffer circuit Ba connected to the terminal end of the product term line IlI
The output contact of the first stage flip-flop D1 is connected to the data input contact of the first stage flip-flop D1, so that the output signal of the AND matrix 1 can be fed back.

The output circuits MCI, MC2 to MCk connect signals generated on appropriate product term lines of the AND matrix 1 to predetermined output terminals of the output ports. That is, as represented by the output circuit MCI, a combinational circuit (formed by programming an OR matrix) consisting of fixed OR gates connected to the ends of appropriate product term lines and an output buffer circuit B0 The output signal is transferred to the output terminal via. Note that the output buffer circuit B. is another product term line (for example, 2□ in the figure
)'4!1. The signal output is controlled by the output signal of the product term line (AND) connected to the end. or,
The signal to the output terminal is inverted and non-inverted by the buffer circuit F, and then fed back to the signal lines LFI to L□ and L□ to LDk.

In a programmable logic device having such a configuration, if appropriate lattice points of the AND matrix 1 are programmed and a clock signal of a predetermined frequency is applied to the clock input terminal CK, the result will be as shown in FIG. 2, for example. A Johnson counter with an equivalent duty of 50% can be realized, and by appropriately decoding the output signal of this Johnson counter with the AND matrix l, it is possible to obtain signals of various waveforms from the output port.

If a sequential circuit to which a Johnson counter is applied is configured in advance as in this embodiment, glitch-free decoding can be achieved by taking the product (AND) of at least two of the outputs of each bit of the Johnson counter. Since an output can be obtained, and unlike a binary counter, it is not necessary to decode multiple output signals from flip-flops, the sum of currents flowing through the grid points is reduced, and power consumption can be reduced. In particular, since the Johnson counter does not generate glitches, it can be designed without considering the occurrence of malfunctions or erroneous signals, and the degree of freedom in design can be improved.

Next, another embodiment of the present invention will be described based on FIG. This embodiment is also a programmable logic device for realizing a Johnson counter. However, to explain the difference from the previous embodiment shown in FIG. It is connected to the output contact of a combinational circuit A, which has a

Then, by programmatically connecting appropriate bean paste points in the product term lines 21 to Z3, a combinational circuit A that exhibits the action of an AND-OR gate as shown in the figure is configured, and the non-inverting output of an appropriate flip-flop is configured. Alternatively, by feeding back the inverted output to the data input contact of the first stage flip-flop DI through the combinational circuit A, it is possible to realize a Johnson counter with different duties as shown in FIG. Furthermore, by providing a plurality of cascade-connected blocks of flip-flops, two or more types of Johnson counters with an appropriate number of bits can be realized, and the degree of freedom in design can be further increased.

Still another embodiment will be described based on FIG. 5.

The program logic device of this embodiment is also for realizing a sequential circuit using a Johnson counter, and to explain the difference from the previous embodiment shown in FIG. A flip flop is formed, and each flip flop D1~
The output contact of the logical product (AND) A, obtained from the product term line XI intersecting the inverted output lines Q, ~Q7 of D, is connected to the J input contact of the JK flip-flop D, and the flip-flop D I'' ” D-'s non-inverting output line Q, ~Q,.

The logical product (A N
D) Ant's output contact is JK flip-flop D
+ is connected to the input contact.

Then, by programmatically connecting appropriate lattice points on the product term lines X, ,
At the same time, the inverted output of the appropriate flip-flop is fed back to the input contact of the first stage flip-flop D through the combinational circuit AX□.
It is possible to realize a Johnson counter of arbitrary bit length with a trap prevention function as shown in the figure.

As explained above, according to these embodiments, a predetermined number of cascade-connected flip-flops are built in to realize a sequential circuit, and the flip-flops provided in the output circuit as in the conventional circuit are not used. Therefore, it is possible to ensure effective use of the output terminal of the output boat.

Further, since these flip-flops are directly fed back from the product term line of the AND matrix, a high-speed sequential circuit can be realized.

The circuit configurations of the output circuits MCI-MCk shown in the embodiments of FIGS. 1, 3, and 5 are merely examples, and are not limited to these. As shown in the conventional example of FIG. It may be of any other configuration including a built-in flip-flop as an output register.

Further, in the above embodiment, the Johnson force outputter is constructed as a one-sequence circuit, but it may also be constructed as a ring counter or a shift register.

According to these embodiments, it is possible to efficiently realize a signal generating device and the like for forming various high-speed sequential circuits.

(Effects of the Invention) As described above, according to the present invention, there are n flip-flops connected in cascade, which can configure a maximum of n-bit Johnson counter, ring counter, shift register, etc. by program connection; a programmable AND matrix including a product term line that intersects the inverting output line and the non-inverting output line of the flip-flop;
Since the configuration is equipped with wiring that returns appropriate signals generated on the product term line to appropriate flip-flop tubes for various sequential circuits by program connection, it can be formed by connecting flip-flops in multiple stages. Not only is it suitable for realizing sequential circuits, but it also has advantages such as improved integration and more effective use of internal resources compared to conventional programmable logic devices.

In addition, since the Johnson counter can be easily formed, unlike a binary counter, the internal states of the flip-flops corresponding to each focus do not change at the same time, so fewer signal lines are required when decoding the outputs of these flip-flops. A desired waveform can be formed using (two or more) waveforms, and therefore, power consumption can be reduced because the number of program points for decoding is small.

In particular, the programmable logic device according to the present invention is suitable for realizing a sequence controller, a signal generation circuit for generating signals of various waveforms, and the like.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of the configuration of a Johnson counter according to the embodiment of FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is an explanatory diagram showing an example of the configuration of the Johnson counter according to the embodiment of FIG. 3; FIG. 5 is an explanatory diagram showing the configuration of still another embodiment of the present invention. , FIG. 6 is an explanatory diagram showing a configuration example of the Johnson counter according to the embodiment of FIG. 5, and FIG. 7 is a configuration explanatory diagram showing the structure of a conventional programmable logic device. Codes in the figure: 1: Logical product matrix D I """Dll; Flip-flop B+ -B=
, F+ , Ba; buffer circuit a l"" a
za + h + ~b, 1+71, X, -, AXI
+Product term line (AND) output AW; combinational circuits 11 to f-, Z+ to Z,. X,,Xt; Product term line LXI """ L XFI + Ly+ ~L%
'rl r L A I ””” LAj +L1~
” lj + L F l〜Lym + L+++=L
oh; Input signal line MCI to MC2; Output circuit

Claims (1)

[Scope of Claims] A logical product matrix for a program including n flip-flops connected in cascade, and a product term line intersecting the inverting output line and non-inverting output line of these flip-flops, and the above product term. A programmable logic device comprising: a wiring for feeding back an appropriate signal generated on the line to an input contact of a first flip-flop by a programmed connection.