JPH0348547A - Reception control circuit - Google Patents

Abstract

PURPOSE:To prevent a synchronizing signal character detected erroneously, to shorten a time required for communication, and to simplify a device by performing the retrieval of the synchronizing signal character in reception data after all the initial values of a reception shift register are shifted. CONSTITUTION:When a synchronism detecting state setting instruction EH is issued, the reception shift register SR1 is initialized, and the reception data is read in the SR1 synchronizing with a reception clock signal, and its output is compared and collated 21 with the synchronizing signal character from a register 4 at a synchronism detecting part 2. When the content of the SR1 is changed and coincides with the synchronizing signal character, the reset of a counter 24 for the reception clock is cancelled being delayed by one clock, and hereafter, the content of the SR1 is shifted to an SR3 at every time when the count value of the counter 24 arrives at 7. Therefore, after the fact that all the contents of the SR1 are shifted is detected by supervising the output of the last digit of the SR1, the synchronizing signal character can be retrieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reception control circuit, and more particularly to a reception control circuit that performs a synchronization signal character search in a synchronous data communication system.

[Conventional technology]

In the synchronous data communication system, as is well known, the reception processing of reception data consisting of a synchronization signal character and a data string in which communication contents are encoded is performed by a reception control device and a data transmission system, as shown in FIG. This is carried out by a system consisting of a processing device. Fig. 6(b) shows an example of a data string used in the synchronous data communication system. Here, SYN
O + S YN l +...S YN7 is a synchronization signal character. Also, B IO+ B 1 1 ,
. . . B17 indicates the first data to be divided among the data strings following the synchronization signal character.

In the data string reception control circuit, C searches for a synchronizing signal character, converts the serial data string after detecting this into parallel data, and sequentially sends it to the data processing device.

FIG. 7 shows an example of a reception control circuit in a conventional synchronous data communication system.

Referring to FIG. 7, the conventional reception control circuit of this type is
It has an elliptical configuration consisting of a reception shift register 1, a synchronization detection section 2, a parallel shift register 3, and a synchronization character storage register 4.

The reception shift register 1 is an 8-bit shift register consisting of well-known flip-flops 1FF11 to 18 that perform a delay operation in synchronization with the reception clock signal input from the terminal TD. It is read sequentially in synchronization with the received clock signal.

The synchronization detection section 2 is comprised of an 8-bit comparator 21, an RS flip-flop 22, a D flip-flop 23, a counter 24, and an AND gate 25.

The comparator 2l converts the output (sign) of each of the eight flip-flops making up the reception shift register 1 and the output (sign) of each of the eight flip-flops making up the synchronous character shift register 4 into bits. This is an 8-bit length data comparator that compares each time.

If the output signs of both match, a logic value "1" is output, and if they do not match, a logic value "O" is output. The RS flip-flop 22 uses the synchronization detection state setting command (EH) input from the terminal TE as a set (S) input, and uses the output of the comparator 21 as a reset (R) input. Here, the synchronization detection state setting command EH is a signal issued by the data processing device, which initializes the synchronization detection operation of the reception control circuit and prepares to receive a new series of data strings.

The D flip-flop 23 is the RS flip-flop 22
This is to delay the Q output of the terminal TC by one clock of the reception clock signal from the terminal TC.

The counter 24 is a 3-bit long counter that uses the output of the D flip-flop 23 as a reset input and counts the received clock signal.

The AND gate 25 is an AND gate that receives the outputs Q1, Q2, and Q3 of the counter 24 as inputs.
It outputs "1" when the count value of 4 or 7, that is, Q1 to Q3 become r 1 j.

The parallel shift register 3 has eight flip-flops FF.
The corresponding outputs of the seven flip-flops FFII to FFII of the reception shift register 16 are input, and the output of the AND gate 25 is set to "1".
When , read, that is, shift the contents.

The synchronization character storage register 4 is an 8-bit shift register consisting of eight flip-flops FF41 to FF48, and stores an 8-bit code that is a synchronization signal character. FIG. 8 is an operation time chart of the conventional reception control circuit shown in FIG.

Next, the operation of the conventional reception control circuit will be explained with reference to FIGS. 7 and 8. Here, as an example, the synchronization signal characters are 01 1001 10 and 8 from the most significant bit (MSB) to the least significant bit (LSB).
Assume that the bit length is encoded. It is assumed that this code is stored in the synchronization character storage register 4. At time TO, the aforementioned synchronization detection state setting command EH is issued and input from terminal Tt. This is applied to the S input of each flip-flop FFI1 to FFI18 of the receiving shift register 1, and initializes these outputs to "1". At the same time, since it is also applied to the S input of the RS flip-flop 22, this output Q is also initialized to "1".

After time T1, the received data input from terminal TD is
In synchronization with the reception clock signal input from terminal Tc,
Read into receive shift register 1. As mentioned above, the output of the receiving shift register 1 is applied to the comparator 21,
Here, it is compared and verified with the synchronization signal character from the synchronization character storage register 4. In this example, as shown in FIG. 8, at time T12, the contents of the receiving shift register 1 match the synchronizing signal character, so the comparator 21 outputs rlJ, and the R input of the RS flip 7 lop 22 is applied to and resets it to set the Q output to "o". The Q output "OJ" of the RS flip-flop 22 is applied to the R input of the D flip-flop 23, and the output rQJ is applied to the counter 24 with a delay of one clock, that is, at time T13.
Apply this to the R input of , and reset it. Therefore, the counter 24 starts counting the received clock signals from time 13. At time T20, the count value of the counter 22 is "7".
'', and the outputs Q1 to Q3 each become ``1-1'', so the AND gate 25 outputs ``1''. The contents of the reception shift register l at this time T20 are:
First data string, B 17+ B 16+...Elt
o, and this first data string is shifted to the parallel shift register 3 by the “1” output of the AND gate 25. From then on, every time the count value of the counter 24 reaches 7,
The contents of receive shift register 1 are transferred to parallel shift register 3.
will be shifted to The above is a case where everything progresses smoothly, but with the conventional reception control circuit shown here, there is a possibility that the synchronization signal character will be erroneously detected. This is caused by the combination of the code content of the synchronization signal character, the initial value of receive shift register 1, and the content of the received data, causing the user to mistakenly think that a regular synchronization signal character has been detected, even though the data string is originally meaningless. This is because there is a possibility.

As an example, the synchronization signal character is 00111111
(MSB→LSB). FIG. 9 shows an operation time chart of the conventional reception control circuit in this case.

At time TO, when a synchronization detection state setting command is issued, the reception shift register 1 is initialized and all digits of 8 bits become 1. After time T1, reception shift register 1
reads the received data sequentially in synchronization with the receive clock signal. Here, if each of the received data at times Tl and T2 happens to be "O", the contents of the receive shift register l at time T3 are 00111111
, that is, it has the same sign as the synchronization signal character. As a result, at time T3, the comparator 21 determines that this is a synchronization signal character, outputs "1", and R
The S flip-flop 22 is reset, and thereafter, reading of the received data from T4 to the parallel shift register is started in the same process as in the normal case described above.

However, if we take the first data read time T10, the contents of the receive shift register 1 are the original data string B.
17+ ・++ B to instead of 0011111
The received data of 0 is completely meaningless. Naturally, the received data read into the parallel shift register 3 after time Tll is also meaningless.

[Problem to be solved by the invention]

The above-described reception control circuit for the conventional synchronous data communication method does not perform a combination of the contents of the synchronization signal character, the initial value of the reception shift register, and the contents of the reception data at a certain moment even if a synchronization detection state setting command is issued. Therefore, this received data is often erroneously detected as a regular synchronization signal character. As a result, at the above-mentioned instant, the synchronization state is assumed to have been established, and the received data string is converted into parallel data and transmission to the data processing device is started. However, it goes without saying that the data that follows is completely meaningless as a communication content.

In order to eliminate this erroneous synchronization, in addition to the original communication data processing function, the data processing device also returns the received data as is to the sending side in order to check the effective data length and content of the received data. This method has the drawback of requiring extra processing functions such as checking for abnormalities. As a result, there have been problems such as an increase in communication time, an increase in data processing time, an increase in the complexity of the device, and an increase in equipment costs.

[Means to solve the problem]

The reception control circuit of the present invention searches for a synchronization signal character included in received data of a synchronous data communication method consisting of a serial digital code string, and after detecting the synchronization signal character, converts the received data into a predetermined manner. In a reception control circuit that divides data into parallel data and converts it into parallel data, the reception control circuit is initialized to a predetermined value by a synchronization detection state setting command signal that sets a synchronization detection operation for the reception control circuit. a first storage means for sequentially reading and storing serially received data in synchronization with a reception clock signal for synchronously performing the operations; a second storage means for storing the code of the synchronization signal character; code comparing means for comparing the memory contents of the first memory means and the memory contents of the second memory means and generating an output indicating that when they match; , further comprising a prohibition signal generating means for disabling the operation of the code comparison means for at least a period of the code length of the synchronization signal character. [Example] Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

As an example of the target reception control circuit, one for a system with an 8-bit synchronization signal character, which is currently widely used, will be taken as an example.

In FIG. 1, the reception control circuit of this embodiment includes a reception shift register 1, a synchronization detection section 2, a parallel shift register 3, and a synchronization character storage register 4.

Among the above-mentioned structural elements, the flip-flop 11 that connects the reception shift register 1 has the following features: a synchronization detection state setting command is applied to the R input instead of the S input in the conventional example, and the synchronization detection state setting command of the synchronization detection section 2 Components other than the configuration and functions are common to those shown in the example of the prior art described above, and the explanation will be omitted here since the explanation will be redundant.

The synchronization detection unit 2 includes an 8-bit comparator 21, an RS flip-flop 22, a D flip-flop 23, a counter 24, and an AND gate 25, which are common parts to those shown in the example of the prior art described above. In addition, it includes a D flip-flop 26, an inverter 27, an RS flip-flop 28, and an AND gate 29.

The D flip-flop 26 delays the output of the FF 18, which is the last digit of the reception shift register 1, by one clock of the reception clock signal, and when reset by the synchronization detection state setting command EH, it is in the initialization state. There is r1”
Output.

Inverter 27 is an inverter that inverts the output of D flip-flop 26. The RS flip-flop 28 has the output of the inverter 27 applied to the set input (S>) and the synchronization detection state setting command applied to the reset input (R).When reset by the synchronization detection state setting command, it enters the initialization state. , that Q
The output will be rQJ. The two AND gates are AND gates that receive the output of the comparator 21 and the output of the RS flip-flop 28 as inputs.

The structural elements of the synchronization detection unit 2 other than those described above are the same as those shown in the example of the prior art described above, and the explanation will be redundant, so they will be omitted here.

Next, the operation of this embodiment will be explained.

FIG. 2 is a time chart of the reception control circuit of this embodiment shown in FIG.

Here, as an example, the synchronization signal character 00111111 (
LSB→MSB) is used again for comparison.

At time To, when the synchronization detection state setting command EH input from the terminal TI1: is issued, it is applied to the R input of the flip-flop FFII of the receiving shift register 1, setting this output to "O", and setting the S of FFs 12 to 18. applied to the inputs to initialize these outputs to ``1''. At the same time, it is also applied to the R input of the D flip-flop 26, the R output of the RS flip-flop 28, and the S input of the RS flip-flop 22, so these outputs are also initialized to "1". After time T1, the received data input from terminal TD is
In synchronization with the reception clock signal input from terminal Tc,
Read into receive shift register 1. As mentioned above, the output of the receive shift register 1 is applied to the comparator 21;
Here, it is compared with the synchronization signal character from the synchronization character storage register 4.

In this example, as shown in FIG. 2, at time T1, the contents of the reception shift register 1 match the synchronization signal character, so the comparator 21 outputs "1".

However, during the period from time TO to T6, the output of the last digit FF 18 of the reception shift register 1 remains at "1", as is clear from FIG. Therefore, the output of the D flip-flop 26 is "1" from time TO to T7 with a delay of one clock, the output of the inverter 27 is "Oj", and therefore the output of the RS flip-flop 28 is "0".
Therefore, the output of the AND gate 29 is rQ at time T1 when the comparator 21 outputs "1". As mentioned above, the RS flip-flop 22 is set to time To by the synchronization detection state setting command EH, and its Q output maintains rl, ? Therefore, the output of the D flip-flop 23 is also delayed by ↓ clocks and reaches the time Tl.
From now on, "{" will be retained. Therefore, the counter 24 is
Reset status continues.

At time T7, the initial value "0" of the flip-flop 11, which is the first digit of the reception shift register l, is output from the D flip-flop 26 and inverted by the inverter 27. r1j, sets the RS flip-flop 28, and outputs r.

When the above state continues and the time T12 is reached, the contents of the reception shift register 1 are changed to 0011 1 1 1 again.
1 (MSB-4LSB), which matches the synchronization signal character of this example, and therefore the comparator 21
" is output. As described above, at this time T12, the output of the RS flip-flop 28 is "1", so the two AND gates output "1" as the AND of both signals is established. This means that the synchronization signal character has been detected.

? The output "1" of the AND gate 29 is applied to the R input of the RS7 flip-flop 22, resetting it and
Let the output be r■. As a result, after time T1B, which is delayed by one clock, the D flip-flop 23 outputs "o", so the counter 24 is released from reset and starts counting the received clock signal applied from the terminal Tc. At time T20, the count value of the counter 24 reaches 7, and the outputs Ql, Q2, Q3 become "
1'', the AND gate 25 performs an AND operation, and outputs r1. The contents of the reception shift register 1 at this time T20 are the first data string, B 17
, B 16. "' B 10, and this first data string is shifted to the parallel shift register 3 by the "1" output of the AND gate 25. Counter 24 thereafter
The contents of the receive shift register 1 are shifted to the parallel shift register 3 every time when the count value of 7 reaches 7.

As is clear from the above description, according to this embodiment, the output of the last digit FF 18 of the reception shift register 1 is processed by a logic circuit consisting of a D flip-flop 26, an inverter 27, an RS flip-flop 28, and two AND gates. By monitoring, after detecting that the contents of the receiving shift register 1 have been completely shifted, a search for a synchronization signal character is performed.

As mentioned above, in this embodiment, a specific synchronization signal character, for example, a specific 8-bit code, has been taken up as an example, but other application examples, such as a 16-bit synchronization signal character, etc. can also be applied. Of course, the invention can be applied as long as it does not depart from the gist of the invention.

Furthermore, various modifications can be made to the components such as the reception shift register, for example, using a RAM instead of a flip-flop, a JK flip-flop instead of a D flip-flop, etc., but without departing from the gist of the present invention. Of course, it can be applied as long as possible.

Next, a second embodiment of the present invention will be explained. FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In FIG. 3, the receiving shift register 1, parallel shift register 3, and synchronization character storage register 4 are common to the first embodiment of FIG. 1 except for details. Here, the first digit flip-flop F of receive shift register 1
In the FII, a synchronization detection state setting command is applied to the S input instead of the R input in the first example.

The synchronization detection unit 2 also includes a comparator 21, an RS flip-flop 22, a D flip-flop 23, a counter 24,
AND gate 25, RS flip-flop 28, and AND gate 29 are common to the first embodiment of FIG. 1 except for details. Therefore, here, we will focus on explaining the parts that are different from the first embodiment to avoid duplication.

In addition to the above, the synchronization detection section 2 also includes a counter 30, an AND gate 31, and a D flip-flop 32.

The counter 30 is a 3-bit long counter to which a synchronization detection state setting command is applied to the R input and counts the received clock signal input from the terminal Tc.

The AND gate 31 outputs the outputs Q1, Q2, and Q2 of the counter 3o.
It is an AND gate that takes the AND of Q3, and these Q1~
When all outputs of Q3 become "1", that is, when the count value of the counter 3o reaches 7, it outputs "1".

D flip-flop 32 is a D flip-flop that delays the output of AND gate 31 by one clock.

Next, the operation of this embodiment will be explained.

FIG. 4 is a time chart of the reception control circuit of this embodiment shown in FIG.

Here, as an example, the synchronization signal character 001 1 1 1 1 (LSB → MSB
) is used again for comparison. At time TO, when the synchronization detection state setting command EH input from the terminal TE is issued, FFs 11 to 18 of the reception shift register 1 are activated.
is applied to the S input of , and the output of all these 8 bits is ``
Initialize to 1. At the same time, the R input of the counter 30, R
Since it is also applied to the R input of the S flip-flop 28 and the S input of the RS flip-flop 22, these outputs are also initialized to rlJ.

After time T1, the received data input from terminal TD is
In synchronization with the reception clock signal input from terminal Tc,
Read into receive shift register 1. As mentioned above, the output of the receive shift register 1 is applied to the comparator 21;
Here, it is compared and verified with the synchronization signal character from the synchronization character storage register 4. In this example, as shown in FIG. 4, at time T4, the contents of the reception shift register 1 match the synchronization signal character, so the comparator 21 outputs "1".

On the other hand, the counter 30 starts counting the received clock signals at time T1, and at time T8, the counted value reaches 7, and the outputs Q1 to Q3 become "1". As a result, AND
The gate 31 outputs "1" when the AND is established, and the next D flip-flop 32 outputs the time T with a delay of one clock.
9, the RS flip-flop 28 is set, and from then on, "1" is output.

Therefore, at time T4 when the comparator 21 first outputs "1", the output of the RS flip-flop 28 remains at "0", which is the state reset by the synchronization detection state setting command, and the AND gate 2 The AND on both is not valid and the output is rQj.

When the above state continues and the time T12 is reached, the contents of the reception shift register l are changed to 00111111 (MS
B→LSB), it matches the synchronization signal character of this example, and therefore, the comparator 21 outputs "1". As mentioned above, at this time T12, the output of the RS flip-flop 28 is "1", and therefore, the AND gate 29 outputs "AND" of both signals.
1" is output. This means that the synchronization signal character has been detected.

Thereafter, reading of received data into the parallel shift register 3 is started from time T13 in the same process as in the first embodiment.

As is clear from the above explanation, according to the present embodiment, from the time when the synchronization detection state setting command is issued, the received clock signal is divided by the number of bits of the synchronization signal character to 8 in this embodiment.
bits> force counter 30. AND gate 3
1 and D flip-flops 32. Meanwhile, by inhibiting the detection of sync signal characters,
After the contents of the receive shift register 1 have been completely shifted and there is no possibility of false detection, a search for a synchronization signal character is performed.

As mentioned above, in this embodiment, a specific synchronization signal character, for example, a specific 8-bit code, has been taken up as an example, but other application examples, such as a 16-bit synchronization signal character, etc. can also be applied. Of course, the invention can be applied as long as it does not depart from the gist of the invention.

Furthermore, various modifications can be made to the 'vi-command elements such as the reception shift register, such as a JK flip-flop instead of a D flip-flop, but these can of course be applied as long as they do not depart from the spirit of the present invention.

Next, a third embodiment of the present invention will be explained. FIG. 5 is a circuit diagram showing a third embodiment of the present invention.
In FIG. 5, a reception shift register 1, a synchronization detection section 2
, parallel shift register 3, and synchronization character storage register 4 are common to the first embodiment of FIG. 1 except for details.

Here, for the flip-flops 1FFII to FF18 of all digits of the reception shift register 1, an initial setting signal is applied only to the R input instead of the R and S inputs in the first example.

In this embodiment, a combination of a reception start command signal and a reception stop command signal issued from the data processing device is used as the initial setting signal instead of the synchronization detection state setting command signal.

For this reason, an RS flip-flop 5, which is set by a reception start command signal and reset by a reception stop command, and a D flip-flop 6, which delays the reception clock signal by one clock, are added to the circuit of the first embodiment. There is.

Therefore, the output of the D flip-flop 6 functions as an initial setting command signal in place of the synchronization detection state setting command in other embodiments. Other than the above, this embodiment is completely the same as the first embodiment shown in FIG. 1, and since the explanation will be repeated, details will be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, after detecting that all the initial values of the reception shift register have been shifted,
Performs a search for synchronization signal characters in received data.

Therefore, it is possible to prevent erroneous detection of a synchronization signal character caused by a combination of the above-mentioned initial value of the reception shift register, contents of the synchronization signal character, and received data at a certain moment. As a result, the communication data processing procedure is simplified, improving the communication data processing speed, thereby reducing the communication time, and simplifying the equipment, reducing equipment costs, etc. The effects of the invention are enormous.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is a diagram showing an operation time chart of the circuit shown in Fig. 1, and Fig. 3 is a diagram showing a second embodiment of the invention. Circuit diagram, Figure 4 is a diagram showing the operation time chart of the circuit shown in Figure 3, Figure 5 is a diagram showing the operation time chart of the circuit shown in Figure 3.
FIG. 6 is a circuit diagram showing a third embodiment of the present invention, FIG. 6 is a diagram showing an example of reception processing and data strings in a synchronous data communication system, and FIG. 7 is a circuit diagram showing an example of a conventional reception control circuit. 8 and 9 are diagrams showing operation time charts of the circuit shown in FIG. 7. 1... Reception shift register, 2... Synchronization detection section, 3
...Parallel shift register, 4...Synchronization character storage register, 5...RS flip-flop, 6...
D flip-flop, 21... comparator, 22... R
S flip-flop, 23...D flip-flop,
24...Counter, 25...AND gate, 26.
...D flip-flop, 27...Inverter, 28
...RS flip-flop, 29...AND gate, 30...Counter, 31...AND gate, 32
...D flip-flop.

Claims (1)

[Claims] 1. After searching for a synchronization signal character included in received data of a synchronous data communication method consisting of a serial digital code string and detecting the synchronization signal character, the received data is In a reception control circuit that divides data into parallel data and converts it into parallel data, the reception control circuit is initialized to a predetermined value by a synchronization detection state setting command signal that sets a synchronization detection operation for the reception control circuit. a first storage means for sequentially reading and storing serially received data in synchronization with a reception clock signal for synchronously performing the operations; a second storage means for storing the code of the synchronization signal character; code comparison means for comparing the memory contents of the first memory means and the memory contents of the second memory means and, if they match, outputting an output indicating the same; and from the time when the synchronization detection state setting command signal is applied. ,
A reception control circuit comprising inhibit signal generation means for disabling the operation of the code comparison means for at least a period of the code length of the synchronization signal character. 2. The first storage means is a shift register having a number of digits equal to the code length of the synchronization signal character, and the prohibition signal generation means is reset by the synchronization detection state setting command signal, and the least significant digit of the shift register is reset by the synchronization detection state setting command signal. 2. The reception control circuit according to claim 1, further comprising delay means to which the output of the reception clock signal is applied and delays the output by one clock of the reception clock signal. 3. The prohibition signal generating means is reset by the synchronization detection state setting command signal, and includes a counter having a count length at least equal to the code length of the synchronization signal character, which counts the received clock signal. A reception control circuit according to claim 1. 4. Claim 1 or 2, wherein the prohibition signal generating means includes an AND gate that takes an AND of the output of the delay means or the counter and the output of the sign comparison means.
or the reception control circuit described in 3. 5. Third storage means for storing a reception start command signal and a reception stop command signal issued from the data processing device to the reception control circuit, and the output signal of the third storage means is in accordance with the synchronization detection state. 5. The reception control circuit according to claim 1, wherein the signal has the same function as the setting command signal.