JPH0347623B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a solid-state camera that is effective for use in an electronic still camera that captures images using a solid-state image sensor instead of a silver halide film and records the obtained video signal electronically or magnetically. The present invention relates to an image sensor and an apparatus.

One of the problems that arises when attempting to use various solid-state imaging devices that have been developed and used for video cameras in electronic still cameras is the shutter function. The major advantage of systems that do not use silver halide film, such as electronic still cameras, is that they do not necessarily require complete light shielding, and at the same time can eliminate the need for mechanical shutters, which can cause vibration and noise. be. To achieve this, the image sensor itself needs to have a shutter function, and interline transfer CCDs and frame transfer CCDs that have an overflow drain (OFD) and an overflow control gate (OFCG) already meet this requirement to some extent. It has been confirmed that the requirements are met.
Among them, interline transfer CCD with OFD is
Prepares for exposure by discharging unnecessary charges from all light-receiving elements to the OFD at once, and completes exposure by transferring signal charges generated by exposure to the light-shielded vertical transfer CCD in the same batch. Therefore, it can be said to have an ideal shutter function, and in principle, it is possible to achieve a shutter time of several microseconds, which was not possible with conventional mechanical shutters. In contrast, frame forwarding
In the case of a CCD, since the transfer from the light-receiving area to the storage area is performed under exposure, in principle, as long as the shutter function of the CCD itself is used, the S/N ratio cannot be avoided during high-speed shutter, and in practice it is 1/500. The limit is considered to be around seconds.

As described above, when using the shutter function of the solid-state image sensor itself, the high-speed shutter side has almost satisfactory performance, but some problems still remain with the low-speed shutter side.

The main cause of this is dark current, which is a factor that significantly degrades image quality, especially in low-light photography. This dark current has a strong temperature dependence, and becomes smaller as the temperature decreases. Therefore, a method of cooling the image sensor itself to reduce the dark current may also be considered. In this case, the Peltier effect is used as a cooling method, but it requires a large current, increases power consumption, and has many disadvantages such as the time constant until cooling and dew condensation, etc., when incorporating it into a small camera. There is.

It has also been considered to discharge the dark current charges generated in the transfer area during exposure or just before the completion of exposure to the outside, but even this has not been a measure against the dark current generated in the light receiving area.

In addition to cooling the image sensor described above, as a means of compensating for dark current, the light-receiving area corresponding to a part of each horizontal scanning line is shielded from light, and after reading out the signal charge to the outside, the light-shielded portion is It has been common practice in video cameras to remove dark current components by clamping the dark current level to a reference level, but in this case, for long periods of time required for electronic still cameras, In addition to increasing the dark current and narrowing the dynamic range, it also has the disadvantage that the dark current component cannot be accurately removed because the dark current of not only the light-receiving area but also the transfer area is added and read.

SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional drawbacks, prevent signal deterioration due to dark current during long exposure, and provide an effective imaging device for use in electronic still cameras that enables a slow shutter function. This is what we are trying to provide.

The apparatus according to the present invention has a detection means for detecting unnecessary charges accumulated in a photodiode during long exposure on the same substrate of a two-dimensional solid-state image sensor having an electronic shutter function. There is one characteristic.

FIG. 1 is an overall conceptual diagram showing an example of a solid-state imaging device according to the present invention, FIG. 2 is a cross-sectional view taken from FIG. 1, and FIG. 3 is a cross-sectional view taken from FIG. 1.

In these figures, H.BCCD is the horizontal transfer register to which transfer clocks φ _H1 and φ _H2 are applied,
V.BCCD is the transfer clock φ _V1 , φ _V2 , φ _V3 , φ _V4 (these are collectively indicated as φ _V in Figures 2 and 3)
is applied to the vertical transfer register. 1 is an overflow drain (OFD) for discharging unnecessary charges, and 2 is a PN junction photodiode for receiving light, which are arranged in a matrix. 3 is
Overflow control gate (OFCG) formed between OFD1 and photodiode 2
Then, the charge accumulated in photodiode 2 is
Controls emissions to OFD1. V.BCCD is the buried channel 4 in the N-type region and the transfer clock φ _V
The signal charge is transferred (vertical transfer) in the direction perpendicular to the plane of the paper (in the case of FIG. 2). A transfer gate 6 is formed between the photodiode 2 and V.BCCD, and transfers signal charges from the photodiode 2 to the V.BCCD side by applying a required voltage TG here. 7 is a clear gate formed between OFD ₁ , which is in charge of the next vertical line adjacent to V.BCCD, and buried channel 4 of V.BCCD. The charge of V.BCCD can be discharged to the outside of the element via OFD1. Reference numeral 9 denotes a light shielding member, which covers all areas except the photodiode 2 area, but basically, if it covers only the V.BCCD area formed by the buried channel 4 and the electrode 5. good.

In FIG. 1, a region 21 surrounded by a broken line (a cross-sectional view of this region is shown in FIG. 3) constitutes a dark current detection region, and is formed on the same substrate as the other regions. The region is in a temperature equilibrium state, and its structure is such that the entire upper surface of the region 21 is covered with the light shielding member 1.
The cross-sectional view is substantially the same as the cross-sectional view shown in FIG. 2 except that it is covered with 9. That is, 11 is OFD ₁ , 12
is a photodiode, 13 is OFCG, 14 is V.
BCCD embedded channel area, 15 is V.
The transfer electrode of BCCD, 166 is a transfer gate, and 17 is a clear gate for discharging the charge of V.BCCD to CFD ₂ 18.

In the device configured in this way, a clear gate 7 is provided for each V.BCCD, and a clear gate 7 is provided for each V.BCCD.
In addition, in the dark current detection area 21, the OFD ₂ that discharges V.BCCD charges can be separated from the OFD 1 in other areas, and the lead wire 22 can be discharged in a more bulk manner. It differs from conventional interline transfer CCDs in that it is configured to be taken out to the outside via the CCD.

FIG. 4 is a configuration diagram showing an example of a peripheral circuit when the solid-state imaging device according to the present invention shown in FIG. 1 is used in an imaging device for an electronic still camera.

In this figure, 28 is the solid-state imaging device (hereinafter simply referred to as CCD) shown in FIG. 1, and each symbol corresponds to the symbol assigned to each terminal in FIG. Appropriate DC voltages V _RD , V OD , and V _OG are applied to the reset drain RD, output drain _OD , and output gate OG of the output circuit, respectively. 29-3
5 are clock drivers, respectively, which amplify the output voltages from the analog switches 36 to 43;
Each terminal of CCD28 CG ₁ , CG ₂ , OFCG, RG, φ _H ,
Apply to φ _V and TG. Analog switch 36~
43 is off, zero voltage is applied to each terminal of the CCD 28.

Here, the transfer clocks φ _H1 , φ _H2 of the horizontal transfer register H.BCCD are collectively φ _H , and the transfer clocks φ _V1 , φ _V2 , φ _V3 ,
φ _V4 is collectively referred to as φ _V. Therefore, there are actually two clock drivers 33 and two analog switches 41, and two clock drivers 33 and two analog switches 41 exist.
4. There are actually four analog switches 42.

44 is a timing pulse generation circuit, CCD2
Pulse groups φ _CG1 , φ _CG2 , necessary to drive 8
φ _OFCG1 , φ _OFCG2 , φ _RG , φ _H1 , φ _H2 , φ _V1 , φ _V2 , φ
_V3 ,
In addition to _{φ V4} , φ _TG and _{the pulse} group _φ Outputs a gate signal φ _RECG , etc. indicating a signal area.

Reference numeral 45 denotes a shutter time calculation circuit which supplies an exposure start instruction pulse φ _ST and an exposure completion pulse φ _ED as timing signals to the timing pulse generation circuit 44 . Here the exposure start pulse φ _START
is given by pressing the camera shutter button (not shown), and the exposure completion pulse _φED is given by the photometry photo provided in the optical system (not shown) based on the shooting condition information such as the aperture value detection resistor 46. This occurs after the shutter time calculated from the photometric element output by the diode 47. Although the photodiode 47 for photometry is provided here, photometry may be performed using the CCD 28 itself. In this case, in Fig. 2, apply a high voltage to OFCG3,
By detecting the output currents from all photodiodes 2, average photometry over the entire surface can be performed.

48, 49, 50, and 51 are all operational amplifiers, and 53 is a sample-and-hold circuit, which is composed of a switch element 54, a capacitor 55, and a high input impedance amplifier 56. These arithmetic circuits and sample-and-hold circuits are
A circuit for performing dark current compensation is configured inside the CCD 28.

The first stage operational amplifier 48 applies a bias voltage to the OFD 18 provided along the V.BCCD of the light-shielded area 21 of the CCD 28 (see FIG. 1).
This is a circuit that applies V _OFD , detects the current ID flowing into the OFD 18, and converts it into a voltage, and outputs a voltage e ₀ as shown in equation (1) at its output terminal.

e ₀ = V _OFD + R ₀ · Id ...(1) R ₀ is the value of the feedback resistor (current detection resistor) of the operational amplifier 48, that is, when the dark current charge of the CCD 28 is accumulated, the pulse When analog switch 37 is turned on with φ _CG and voltage V _CG is applied, all dark current charges of V.BCCD in region 21 are discharged at the same time, dark current Id flows through OFD ₂ , and arithmetic amplification is performed. At the output terminal of the device 48, there is a voltage as shown in equation (1).
You can get e ₀ .

The operational amplifier 49 uses the output voltage of the operational amplifier 48.
The bias voltage V _OFD in e ₀ is subtracted, and the output voltage proportional to the current Id is applied to the output terminal - (R ₂ /R ₁ )・R ₀・
It constitutes a subtraction circuit that obtains Id.

One aim of the present invention is to use this dark current proportional output voltage to reduce the voltage V _TG that should be applied to the transfer gate TG during high-speed shutter, for example.
The purpose is to change the dark current, and as the dark current increases,
Subtract a large voltage from V _TG and use the resulting voltage V _TG ′ to convert V from the photodiode.
It is configured to control the transfer of signal charges to the BCCD. Two operational amplifiers 50 and 51 constitute a subtraction circuit for this purpose. At the output terminal of the operational amplifier 51, a voltage e ₀₁ as shown in equation (2) is obtained, and the resistor R ₄
By changing , the coefficient of Id is changed and the effect on the transfer gate voltage is adjusted.

e ₀₁ =V _TG −R ₂・R ₃・R ₀ /R ₁・R ₄・Id ...(2) In this example, a linear element is used, but the transfer gate voltage V The potential change between the photodiode and V.BCCD due to _TG ' is nonlinear, and this is solved by using a nonlinear element in place of resistor _R4 . Furthermore, logarithmic compression can be performed by replacing the current detection resistor R ₀ with a nonlinear circuit including a diode.

The sample-and-hold circuit 53 is provided to cope with a time delay between the timing of current detection by φ _CG and the timing of charge transfer by φ _TG . In this embodiment, the overflow control gate OFCG is configured to select and use two voltages V _OFCG1 and V _OFCG2 , and this is achieved by turning on either φ _OFCG1 or φ _OFCG2 . ing.

There is a relationship between the two voltages: V _OFCG2 > V _OFCG1 ,
In the normal exposure state, V _OFCG1 is applied to OFCG, and in this case, when the blooming state occurs and the charge overflows from the photodiode,
This can be discharged to the adjacent OFD ₁ . Also,
When V _OFCG2 is applied to OFCG, the boundary potential between the photodiode and OFD ₁ becomes sufficiently low that any charge present in the photodiode above the reference potential is drained to OFD ₁ .

The operation of the circuit shown in FIG. 4 will be described below with reference to the waveform diagram shown in FIG.

As shown in FIG. 5a, when the exposure start pulse φ _START is generated by pressing the shutter button at time t= _t0 , the shutter time calculation circuit 45 starts the exposure start pulse φ START given by the timing control circuit 44. Photometry is started in synchronization with the vertical synchronization signal VD shown in FIG. 5b, and the exposure start instruction pulse _φST to the timing control circuit 44 is
This occurs as shown in Figure c. The timing control circuit 44 that receives the pulse φ _ST sets φ _OFCG2 to “H” (High) level and φ _OFCG1 to “L” (Low) level in synchronization with φ _ST , as shown in FIG. 5 e and f. As a result, the charges existing in V.BCCD are discharged from the photodiode to OFD, and the two clear gates φ _CG1 and _{φ CG2} shown in FIG. Discharge to ₂ . The above operation can be completed in a short time of about 10 μsec because only a single pulse is applied.

Here, the CCD 28 will be explained as being able to be used also as a video camera, and even in the case of still image shooting, the video signal is read out as a field image on a TV.

The vertical synchronization signal VD shown in Figure 5b is generated continuously at a 1/60 second period, and is within 1/60 seconds from the start of exposure at time t= _t1 to the next vertical synchronization signal VD. When the exposure is completed in , the influence of the dark current is small and no practical problem arises due to normal clamping of the light-shielded portion.

Figure 5 shows that unlike such high-speed shutter operation, when the shutter time exceeds 1/60 seconds, that is, the exposure does not end even if it exceeds 1/60 seconds.
A case is shown in which the exposure completion signal _φED shown in FIG. 5d is not generated from the shutter time calculation circuit 45 within a period width of 1/60 second. In such a case, the pulse _indicated by _φ do.

This pulse _φX controls the on/off of the analog switch 57 in the circuit shown in FIG.
If _φX is “H” level, analog switch 57
is turned on, and the voltage V' _TG shown in FIG. 5h to be applied to the transfer gate TG becomes V' _TG =
_V.TG , and complete transfer from photodiode 2 to V.BCCD is achieved. _{On the} other hand, _{if φ} becomes.

Next, the operation in the vicinity from time t= _t3 to t= _t5 will be explained. After transitioning to dark current compensation mode, a preset time (for example, 4 cycles of VD 1/
If the exposure completion signal φ _ED is not generated even after 15 seconds) have elapsed, at that time t= _t3 , pulses φ _CG1 and φ _CG2 are applied to the two clear gates CG ₁ and _{CG 2} . Generate and apply voltage V _CG , V.BCCD
Dark current charges are discharged from all of the this house,
The charge discharged from the OFD ₂ becomes a pulse current, which produces a voltage change in V _TG ' from time t= _t3 to t= _t4 in FIG. 5h at the input of the sample-and-hold circuit 53 in FIG. . In order to store and hold this voltage change in the sample-and-hold circuit 53, the pulse φ _S is set to the "L" level at t= _t4 . Note that this sample-and-hold circuit 53 may be replaced with a peak-hold circuit.

This held voltage V _TG ' is lower than the voltage V _TG and therefore results in an incomplete transfer from photodiode 2 to V.BCCD, and while the voltage V' _TG is held, the time t Between = t ₄ and t = t ₅ , this voltage is applied to the transfer gate TG.
If the signal is transferred using the pulse _φTG shown in FIG. 1, it becomes possible to transfer only the signal charge from the total signal charge of the dark current charge generated in the photodiode 2 to V.BCCD. In this case, V _TG ′ is Id
Adjust the voltage level accordingly. Here, the dark current generated in the V.BCCD of the light-shielded area 21 and the photodiode 2 of the light-receiving area
It is assumed that there is a certain relationship between the dark current and the dark current generated.

As a result, V.BCCD adjacent to photodiode 2 which is not light-shielded has a range from t=t ₁ to t=t ₄
Only the signal charge generated in the photodiode during the period up to this point can be transferred. In this case, it is practical to adjust so that some dark current charge is also transferred to V.BCCD along with the signal charge, and this charge acts as a bias charge to reduce signal charge loss in areas where the signal charge is minute. It has the effect of
Furthermore, this slight amount of dark current charge is transferred to V.BCCD within the dark current detection region 21 in exactly the same way, so it can be removed by clamp processing when reading out from the CCD 28.

The signal charge is transferred from the photodiode 2 to V.BCCD, and _the remaining dark current charge changes φ _OFCG2 and φ _OFCG1 shown in FIG. Apply _OFCG2 to OFD ₁
to be discharged.

After this, the photodiode starts accumulating light-receiving charges again. Also, the time required for the above operation is
This is sufficiently short compared to the previous exposure time starting from time t= _t1 and ending at time t= _t3 , and the exposure time error can be practically ignored.

In the timing chart in Figure 5, t = t ₆ to t
The operation from t=t ₈ to t=t 8 is almost the same as the operation from t=t ₃ to t=t ₅ .

In this case, since the signal charge has already been transferred to the V.BCCD adjacent to the light-receiving photodiode 2 at t= _t4 , it is no longer possible to discharge the charge from this V.BCCD. , φ _CG1 is not changed, a pulse is simply applied to φ _CG2 only, and the signal charge is transferred from the photodiode to V.BCCD. The dark current charge generated in V.BCCD during the period from time t = t ₅ to time t = t ₆ is no longer
It cannot be removed inside the CCD28, and this
This is one of the constraints on long-time exposure in this embodiment. In other words, the dark current of V.BCCD is
Determine the maximum possible exposure time.

If the exposure continues thereafter, the process from t=t ₆ to t=t ₈ will be repeated at appropriate time intervals. Note that in this case, the dark current charge of V.BCCD alone cannot be removed, so as a countermeasure, for example, use a light-shielded photodiode 1.
2 and V.BCCD are provided in multiple rows, some of them operate in the same way as other light-receiving groups to hold the dark current accumulated in V.BCCD, and the others are used for dark current detection. By performing clamp processing externally using the partially held output, the dark current compensation of V.BCCD can be achieved.

Finally, the operation after the exposure completion pulse _φED is generated at a certain time, t= _t9 in FIG. 5, will be described.

As shown in FIG. 5d, the exposure completion pulse _φED generated at t= _t9 is the timing control circuit 4
4, this timing control circuit 44 immediately applies a voltage V _CG to the clear gate CG ₂ of the dark current detection region 21 by a pulse φ _CG2 , and thereby
The change in V' _TG is sampled and held in the same manner as described above, and at t=t ₁₀ a transfer gate pulse φ _TG is generated to transfer only the signal charge to V.BCCD. During the exposure starting at t= _t1 , the charges of V.BCCD which are divided into multiple times and integrated are read out from t= _t11 in synchronization with the subsequent vertical synchronization signal VD.

In this case, the gate signal φ _RECG to the external electrical or magnetic recording medium is output at "H" level from t= _t1 to t= _t12 as shown in FIG. 5m. . At the same time, dark current charges were accumulated
The clamp pulse φ _CP corresponding to the position of V.BCCD is also
It is output for each horizontal scanning line and used for final dark current compensation outside the CCD 28.

In the above embodiment, the configuration of the area 21 for detecting dark current provided in the CCD 28 is not limited to that shown in the cross-sectional view of FIG. 3, and may have another configuration.

As explained above, according to the present invention, at a stage before reading signal charges from an image sensor,
This eliminates dark current charges inside the image sensor and makes it possible to divide and transfer only the signal charge from the same photodiode to the same transfer channel multiple times, allowing extremely long exposure times. Still images with good S/N ratio can be obtained even in the case of

[Brief explanation of drawings]

FIG. 1 is an overall conceptual diagram showing an example of a solid-state image sensor according to the present invention, FIG. 2 is a cross-sectional view in FIG. 1, FIG. 3 is a cross-sectional view in FIG. 1, and FIG. A connection diagram showing an example of the peripheral circuit of such an imaging device, and FIG. 5 is an operation waveform diagram for explaining its operation. 1... Overflow drain (OFD), 2...
... Photodiode for light reception, 3 ... Overflow control gate (OFCG), 6 ... Transfer gate, 7 ... Clear gate, 21 ...
Dark current detection area, H.BCCD...horizontal transfer register, V.BCCD...vertical transfer register, 4...embedded channel, 5...electrode.

Claims (1)

[Scope of Claims] 1. A light-receiving region that generates and accumulates signal charges according to the intensity of incident light, an unnecessary charge discharge region arranged in parallel on one side of the light-receiving region, and an unnecessary charge discharge region arranged in parallel on the other side of the light-receiving region. and a signal charge transfer region, which enables discharge of unnecessary charges from the light receiving region to the unnecessary charge discharging region and transfer of signal charges from the light receiving region to the transfer region at any time. In an imaging device using a two-dimensional solid-state image sensor, a transfer means capable of controlling the amount of charge transferred from the light receiving area to the transfer area and a dark current charge detection means are provided on the two-dimensional solid-state image sensor. ,
An imaging device characterized in that the transfer means is controlled by the dark current charge detection means. 2. The imaging device according to claim 1, wherein the dark current detection means includes a light-shielded light receiving region, a light-shielded signal charge transfer region, and a dark current detection overflow drain. 3. Prior to photographing exposure, the charges existing in the light-receiving area and the transfer area are discharged to the outside of the device all at once, and then exposure is started, and after the appropriate exposure time has elapsed, the dark current charges are discharged from the transfer area of the dark current detection current. death,
The imaging device according to claim 2, which is driven to detect this and subsequently control the amount of charge transfer from the light receiving area to the transfer area. 4. The unnecessary charge discharge region is adjacent to the light receiving region and the signal charge transfer region through gates, respectively, and unnecessary charges can be discharged from both the light receiving region and the signal charge transfer region. The imaging device according to scope 1. 5 When exposure lasts for a long time, the signal charge generated in each light-receiving area is divided into multiple times and transferred to the same transfer area, and the unnecessary charges generated in the light-receiving area are transferred to the unnecessary charge discharge area after each transfer. An imaging device according to claim 1, which is driven to do this.