JPH0346840A - Frame synchronizing signal detector - Google Patents

Abstract

PURPOSE:To easily and programmably set the number of bits of a frame synchronizing signal and a frame synchronizing condition, etc., by performing the processing of serial data synchronously with the frame synchronizing signal after detecting the frame synchronizing signal from serial data. CONSTITUTION:A sub-CPU 7 which receives demodulated data at every bit retrieves a frame synchronizing signal having preliminarily determined bit length and bit pattern from this data. At this time, the bit length and the bit pattern of the pertinent frame synchronizing signal can be arbitrarily set and programmed. In the case of receiving the instruction of reception start, a serial I/O 3 starts the reception of data from an MSK MODEM 9 and transfers received data to a main CPU 1 at every 8 bits. The main CPU 1 analyzes the received data to perform the data processing such as the storage of required data to a memory.

Description

Detailed Description of the Invention (Field of application in fL industry) The present invention relates to a frame synchronization signal detection device, and particularly to a frame synchronization signal detection device for detecting a frame synchronization signal during data reception in serial data transmission using a digital modulation/demodulation method. Regarding a detection device.

(Conventional technology) A conventional frame synchronization signal detection method will be explained.

First of all, in addition to the 5 main CP IJ, the sub-C
Some use a briprocessor as P[J. In this case, first, a frame synchronization signal is detected using the sub CPU, and data received according to this frame synchronization signal is demodulated by the sub CPU. This demodulated data is sent to the main CPLI via an interface device.

As a second method, there is a method in which data is received only by the main CPU. In this case, the main CPU receives serial data for each pit by interrupt, and the main CPU υ also detects a frame synchronization signal.

A third method uses a serial interface IC. In this case, the frame synchronization signal is detected using the function of the serial interface IC.

A fourth method is to configure the frame synchronization detection function with hardware. In this case, the frame synchronization signal is detected by hardware, and after detecting the frame synchronization signal, the main CPU
U receives data.

However, each of the conventional methods described above has the following drawbacks.

First, the first method requires hardware such as serial data as an interface device for communication between the sub CPtJ and the main CPU. Further, since the sub CPU is required to have a function of transmitting the received data to the main CPU after once receiving all the data, it is required to be large-scale and expensive. In addition, sub CPU
As the communication software between the computer and the main CPU becomes large-scale, the development process for the software becomes complicated, and the need for debugging increases, resulting in a decrease in development efficiency and reliability. It is also undesirable from a sexual standpoint.

In the case of the second method, the main CPU (1) usually performs processing related to other communications in general, such as reading the setting states of various switches or controlling the display state of the display device, so that the main CPU is further received. Performing interrupt processing for each bit in order to process serial data places a heavy burden on the main CPU, and in some cases, there is a risk that serial data reception or the above processing may not be completed in time.

In the case of the WE system, there are usually many restrictions, such as the algorithm for detecting the 1G frame synchronization signal for the serial interface. For example, the data bit length handled by 1c for normal serial interface is 6.8.1
When detecting a frame synchronization signal, frame synchronization is determined to be established when all bits of the frame synchronization signal match. Therefore, if the condition for establishing frame synchronization is that synchronization is established when 14 bits out of 15 bits of data bit length match, the serial interface tC cannot be used.

In the case of the fourth method, for example, the number of pits of the frame synchronization signal and the conditions for establishing frame synchronization are set such that synchronization is established when 14 bits of the 15 data bit length of the frame synchronization signal mentioned above match. - Configuring the system using software has low versatility, and it is difficult to configure it programmably. In other words, in order to configure a full programmer with hardware, it is necessary to add more circuits, so the space occupied by a single circuit board cannot be minimized. If such a system were to be constructed, a great deal of effort and expense would be required to design these circuits, and there would be some oversight in terms of profitability.

[Object of the Invention] The present invention has been made in view of the above, and it is an object of the present invention to provide a frame synchronization signal detection method in which the number of pits of a frame synchronization signal, frame synchronization establishment conditions, etc. can be easily configured by a programmer. It is an object.

[Summary of the Invention] In order to achieve the above object, a frame synchronization signal detection device of the present invention detects a frame synchronization signal from received serial data, and in synchronization with the frame synchronization signal,
A frame synchronization signal detection device configured to process data subsequent to the frame synchronization signal, comprising: a first data processing means for detecting a frame synchronization signal from the serial data; and a frame synchronization signal detected by the first data processing means. and second data processing means for processing input data after synchronization is established.

In the frame synchronization signal detection device according to the present invention,
After detecting the frame synchronization signal from the serial data received by the first data processing means, the second data processing means processes the serial data on the frame synchronization signal in synchronization with the frame synchronization signal. ing.

[Example] The present invention will be described in detail below based on an example shown in one figure.

FIG. 1 is a block diagram showing an embodiment of the present invention,
Digital modulation and demodulation system, for details MSK (Minimu
m Phase 5hift Key ing
) shows the data receiving side in serial data transmission using the method.

In the figure, a main CPU 1 not only controls transmission and reception of serial data, but also controls switches, displays, etc., and performs data calculations.

A serial number 103 is a serial interface device, which is connected to the main CPU 1 via a bus, and transmits and receives serial data.

The parallel 1105 is a parallel interface device, and is connected to the main CPU described in vI via a bus, and sends and receives signals between the sub CPUs 7, which will be described later.

The sub CPU 7 detects a frame synchronization signal of the received serial data and instructs the serial data 103 to start receiving data.

The MSK modem 9 demodulates the input MSK signal and converts it to T'T.
L (Transistor
(Logic) level data and clock are regenerated.

Next, the operation of this embodiment will be explained according to the data reception procedure.

First, the MSK modem 9 demodulates the incoming MSK signal and regenerates the TTL level data and clock.Next, the sub CPU 7, which receives this demodulated data bit by bit, reads the data in the data. A frame synchronization signal having a bit length and bit pattern determined from t is searched. At this time, the bit length and bit pattern of the frame synchronization signal can be arbitrarily set and programmed. Therefore 1 out of the set bit length for example! Prepare multiple sets of frame synchronization signal types that allow bit errors up to 1 bit, or are set according to bit length and bit pattern, and select any frame synchronization signal from these multiple sets based on instructions from the main CPU, etc. You can set complex conditions such as 1st place.

When the sub CPU 7 detects a frame synchronization signal from the reproduced data, it instructs the serial number 103 to start receiving, and also notifies the main CPU 1 of the establishment of frame synchronization via the parallel number 105. .

When the serial [103 receives an instruction to start receiving, MSK
It starts receiving data from the modem 9 and delivers the received data to the main CPU I every 8 pits.

The main CPU 1 analyzes the received data and performs data processing such as storing necessary data in memory, and when it is determined that the received data is unnecessary, the main CPU 1 performs data processing such as storing the necessary data in memory. serial! 103 to suspend reception and enter a standby state.

Further, when the main CPU t has finished receiving all the necessary data, it instructs the sub CPU and the serial 1103 to stop receiving data and enter a standby state.

As described above, according to this embodiment, the bit length of the frame synchronization signal,
A completely arbitrary bit pattern can be programmed, and complex conditions such as allowing a 1-bit error among the bit lengths can be set.

Furthermore, it is possible to easily accommodate complex system configurations such as preparing a plurality of types of frame synchronization signals and selecting an arbitrary one based on instructions from the main CPU.

The sub-CPU can use a small-scale single F-tube microcomputer, and the software of the sub-CPU can be converted into firmware, so development efficiency is excellent and the configuration can be small and inexpensive.

Furthermore, the communication between the sub CPU and the main CPLI can be carried out using simple hardware and software.

In addition, it goes without saying that the present invention can be modified in various ways without departing from the gist of the present application.

[Effects of the Invention] As explained above, according to the present invention, the frame synchronization signal is detected in the first data processing means, and the second data is detected in accordance with the frame synchronization signal detected by the first data processing means. The processing means processes the input data.

This has the advantage that the number of pits of a frame synchronization signal, conditions for establishing frame synchronization, etc. can be easily configured in a programmable manner.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the invention in detail. 1...Main CPU 3...Serial l10 5...Parallel l10 7...Sub CPU

Claims (1)

[Scope of Claims] A frame synchronization signal detection device that detects a frame synchronization signal from received serial data, and processes data following the frame synchronization signal in synchronization with the frame synchronization signal. The device includes a first data processing means that detects a frame synchronization signal from data, and a second data processing means that processes data detected by the first data processing means and input after synchronization is established. A frame synchronization signal detection device characterized by: