JPH0346051A - Interruption control system for multiprocessor system - Google Patents

Abstract

PURPOSE:To improve system processing efficiency by permitting a processor with low processing priority to execute an interruption processing when interruption occurs. CONSTITUTION:When interruption occurs, signals PRI0-7 showing the priority of the processing decided from the propriety of the interruption of the processor, the priority level of a task in the middle of execution, a processor number and the like are outputted from the processing parts 8 of respective processors 1. An interruption control part 9 compares the signals PRI0-7 with signals XPRI0-7* for comparing processing priority, which arrive from the other processor, and the processor with the lowest priority is caused to execute the interruption processing. Thus, an interruption control system superior in system processing efficiency can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method in a computer system having a multiprocessor configuration.

[Prior Art] FIG. 2 is a block diagram showing a configuration example of a conventional interrupt control system disclosed in Japanese Patent Laid-Open No. 61-75453.

From the input/output device 2 to the plurality of processors 1-1.1-2. l
Interrupt at -3,... This interrupt control is performed by peripheral circuits of the processor.

AND circuit 5-1.5-25-3 configuring the peripheral circuit
... performs an operation that disables interrupts. Also, OR circuit 3
-2.3-3...and AND circuit 4-2.4-3
. . . determines the priority order and performs an operation of selectively giving the interrupt request IRQ of the input/output device 2 to each processor.

Among these, OR circuit 3-2, 3-3... of each processor
The control by ... is performed by connecting these in a chain,
It is called a daisy chain method because the priority of each processor is fixed in the order in which it is connected. The priority of processor 1-1 is high, and the priority is sequentially 1-2. l-3...
・It is lowering in the direction of .

Also, the control by the AND circuits 4-2, 4-3...
SK terminal), and in this system, the interrupt destination processor is determined by a combination of this control element and the above-mentioned fixed priority based on the daisy chain connection.

Now, processor 1-1 is not interrupting, processor l-2
is interruptible. Then, NON of processor 1-1
The interrupt rejection signal "L" output from the MASK terminal is inverted and input to the AND circuit 4-2. Further, since the interrupt enable signal "H" output from the NONM A S K terminal of the processor 1-2 is directly input to the AND circuit 4-2, the AND circuit 4-2 is energized and its output is "H++". Make it.

On the other hand, the human input to the interrupt terminal (INT terminal) of the processor 1-2 is initially "L", and this "L" signal and the "H" signal inverted by the inverting circuit 7-2 are combined into an exclusive OR circuit. 6-2, the exclusive OR circuit 6-2 makes its output "H".

The “H” output of the AND circuit 4-2 described above and exclusive OR
The AND circuit 5-2, to which the "H" output of the circuit 6-2 is input, waits for an interrupt signal IRQ from the input/output device 2.

Here, when the interrupt signal IRQ of the input/output device 2 is output, the output of the AND circuit 5-2 becomes "H", and the "H"
Since the signal is input to the INT terminal of processor 1-2, interrupt processing is performed by processor 1-2.

The "H" signal input to the INT terminal of the processor 1-2 is also input as is to the exclusive OR circuit 6-2, and is also inverted by the inverting circuit 7-2 and sent to the same exclusive OR circuit 6-2. Exclusive OR circuit 6-
The output of No. 2 does not change and remains at "H". At the same time, the "L" output of the inverting circuit 7-2 is input to the AND circuit 5-1 on the host processor side, thereby putting the AND circuit 5-1 in a disabled state.

In addition, the interrupt enable signal “
"H" sets the output of the OR circuit 3-2 to "H", inverts it and sets the output of the AND circuit 4-3 as input to "L++", and further outputs this to the AND circuit 5-3 on the lower processor side.
AND circuit 5-3 is also set to a prohibited state in order to perform manual input.
In this way, when the processor 1-2 is performing interrupt processing, the upper and lower AND circuits 5-1.
Since the processors 5-3, .

[Problems to be Solved by the Invention] However, in the conventional interrupt control method described above, the interrupt destination processor is determined by a combination of only two factors: - Interrupt enable/disable status of each processor - Fixed priority by daisy chain connection. As a result, it had the following drawbacks:

Assume that there is a processor that is not performing any processing, such as a wait state or an idle state.

However, if there is an interrupt-enabled processor that has a higher priority in the daisy chain than that processor, then the processor with the higher priority in the daisy chain will interrupts the processor. The reason why the processor with the higher priority in the daisy chain is interrupted in this way is to simplify the circuit configuration. Furthermore, even if the processor with a higher daisy chain priority is performing some processing, the above-mentioned interrupt is performed regardless of that processor. As a result, there was a problem in that the processing efficiency of the system decreased.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art by comparing the processing priorities of each processor and determining the interrupt destination processor. An object of the present invention is to provide an interrupt control method that does not interrupt a processor and has excellent system processing efficiency.

[Means for Solving the Problems] The present invention provides an interrupt control method for a multiprocessor system that controls interrupt requests to a plurality of processors. means for indicating processing priority of each processor determined by combining elements;
The processor is configured to include comparison means for comparing the processing priorities between the respective processors and transmitting an interrupt request to the processor with the lower processing priority.

[Operation] For example, when an interrupt request is issued from an input/output device, the processing priority of each processor is output from the processing priority indicating means.

Then, in each processor, its own processing priority and other processing priorities are compared by comparison means, and if the own processing priority is higher than the other processing priority, an interrupt request to the own processor is rejected. Conversely, if the processing priority of one's own processor is lower than the processing priority of any of the other processors, the interrupt request is transmitted to the own processor.

Therefore, a processor with a low processing priority receives and receives an interrupt request, and the interrupt processing is performed in this processor with a low processing priority.

[Example] An example of the present invention will be described below with reference to FIGS. 1 and 3 to 7.

FIG. 1 shows an example of an interrupt control method of the present invention applied to a computer system having a multiprocessor configuration.

In the illustrated example, three processors l-1, 1-2゜1-3
This figure shows a multiprocessor system consisting of one input/output device 2 and one input/output device 2. Since the internal structure of each processor is the same, -N (N=1.2.3) is attached to the code of each processor and the elements constituting each processor to distinguish them. For processors, this −N
Common explanations will be made using the symbols excluding .

The processor 1 is composed of a processing section 8 that performs numerical calculations, etc., and an interrupt control section 9 that performs interrupt control.

Between these, there is a signal line 12 that transmits the interrupt request IRQ from the interrupt control section 9 to the processing section 8, and a signal PRI from the processing section 8 to the interrupt control section 9 indicating the priority of the processing being performed by the processing section 8. 7 is connected by a signal line 13 that transmits the signal. The signal P RI ov representing the priority of this process is
Since the 8-bit configuration is used here, it is possible to distinguish between a maximum of 256 levels of processing priority.

The processors are interconnected by a signal line IO that transmits a signal INT indicating the occurrence of an interrupt from the input/output device 2. Further, the processors are interconnected by a signal line 11 that transmits signals xPRI, , * (* indicates a negative logic signal) for comparing the processing priorities of each processor. This comparison signal XPRI. ~, * are input/output signals of each processor.

Next, the operation in such a configuration will be explained using FIG. 3.

First, when an interrupt request is generated in the input/output device 2, a signal INT indicating the occurrence of an interrupt is used to notify all processors of the occurrence of the interrupt via the signal line 10. All the processors detect the occurrence of an interrupt by the rising edge of the INT signal, that is, the transition from the "L" level to the "H" level (step 301). When the occurrence of an interrupt is detected, the processing unit 8 sends the PRIG signal. -7 Processing priority PRr of the processor transmitted through the signal line 13, -
7 is held (step 302).

Next, XPRI0 to .
*Output the held processing priority PR1°-7 with its polarity inverted to the signal line 11 (Step 3o3), and output the value PRr held by the own processor. -7, and a signal XPRIQ taken in from another processor to compare processing priorities.
(step 304).

As a result of the comparison, if it is found that there is another processor that is performing a process with a lower processing priority than the own processor, that is, the retained PRI. ~7≠XPRI0. ．． So,
The processor with higher processing priority is X P RI ,...
*Stop outputting the held priority to the signal line 11 (step 306).

On the other hand, as a result of comparing the processing priorities between each processor,
When it is determined that a certain processor is performing a process with the lowest processing priority, the interrupt control unit 9 of that processor transmits an interrupt request to the processing unit 8 using the IRQ signal (step 305).

The processing priority of each processor, which consists of 8 bits, is determined by combining the processor's interrupt enable/disable status (detected by hardware), the priority level of the task being executed (set by software), etc. . Also, with these values alone, there is a possibility that the processing priority will be the same among multiple processors, so to avoid this,
A processor number fixedly determined by the hardware is also used.

Note that among the above-mentioned factors that determine the priority level, there is an interrupt disable state of the processor, and in this case, an interrupt is not performed, but the processor accepts and processes the interrupt.

In other words, if all processors are in an interrupt disabled state,
When an INT is issued to a processor, the interrupt processing unit 9 of the processor with the lowest processing priority processes the interrupt reception and issues an interrupt request IRQ to the processing unit 8, but the processing unit 8 interrupts the request. It will be put on hold until the situation is met.

Next, the interrupt control unit 9 and the processing priority of the processor will be explained in more detail.

FIG. 4 is a block diagram showing the configuration of the interrupt control section 9. As shown in FIG. The interrupt control unit 9 includes a latch circuit 41 and a comparator circuit 42 .
It mainly consists of an AND circuit 44.

The latch circuit 41 holds the processing priorities PR1 to PR7 of the processing section 8 when the INT signal is input through the signal line 1o.

The comparison circuit 42 inverts the polarity of LPRro-7, which is the processing priority of its own processor held in the latch circuit 41, and outputs it to the xPRI G-7 signal line 11, thereby comparing its own output signal with that of the other processor. XPRI output from. ~7
Compare with 7 pieces. The processor that outputs the largest LPRl signal acquires the interrupt and outputs the acquisition signal "H" from the comparison circuit 42, while the other processors fail in acquisition and output the acquisition signal "L" from the comparison circuit 42. In addition,
The arbitration start signal input to the comparison circuit 42 is always at the "H" level.

The AND circuit 44 outputs the IN signal from the timing control circuit 43 when the acquisition signal "H" is output from the comparison circuit 42.
After the T signal rises, the comparison circuit waits for a period of time to stabilize, and then outputs the IRQ signal to the processing unit 8 to cause the processor to perform interrupt processing.

FIG. 5 shows a concrete block diagram of the comparison circuit 42. It has eight determination circuits 50 to 57 corresponding to the 8-bit configuration indicating processing priority. The internal structure of each determination circuit is the same. The eight determination circuits 50 to 57 are connected in series by arbitration start signal lines, and the eight L PRI o+ from the latch circuit 41.

Signal line 45 and 8 external xPRf, *Signal line 1
1 and are respectively connected to the corresponding lines. In addition,
XPRI. , the oven collector method is adopted for the seven signal lines.

Here, the configuration of the highest-level determination circuit 50 will be explained. When the arbitration start signal is “H”, the signal held by itself is L
NAND circuit 50 that inverts PR1, (LPRIo*) L and outputs it to the XPRIo* signal line via the driver 504.
1, the signal LPR1 it is holding, or another XPRI sent via the driver 505, and an OR circuit 502 that outputs an "H" signal when any of the *signals is "H". , when the arbitration start signal is “H”, the OR circuit 502
and an AND circuit 503 that outputs the output of . to the arbitration start signal terminal of the lower determination circuit 51.

In this example, the digit of LPRl7 is the lowest. Upper digit - (L
PRr. ) to your own holding signal and XPRl o-7
Judge this signal. The signal you are holding (for example, LPR)
T,) is at L” level, and the x PRI O-?* signal (
For example, when x PRI + *) is "L", the arbitration start signal is not output to the lower digit determination circuit.

Therefore, it is determined that this processor has a high processing priority, and the acquisition of the interrupt fails. In this way, the processor with the lowest processing priority handles the interrupt.

FIG. 6 shows the bit configuration for determining the processing priority of the processor. Among the 8 bits, the PRrO bit is the most significant digit, and the values decrease in the order of PRIl, PRI2, . . .

ENB is a 1-bit configuration of PRIO and indicates whether or not an interrupt is enabled. rOJ indicates no interrupt (interrupt mask), and Ill indicates interrupt is enabled.

LEVEL a+4 consists of 5 bits PRII to PRI5 and indicates the priority level of the task. "
00000J indicates that the task with the highest priority is running, that is, it is the most difficult to interrupt. r
When it is lllllJ, it indicates that the task with the lowest priority is running, that is, it is in a state where it is most likely to be interrupted.

Last CPUN0. ~1 consists of 2 bits PR16~PRI7 and indicates the processor number. “○0JTO
IJrl 0Jrl IJ is each processor NO.
,0,NO,1,NO,2,NO,3. That is, this bit configuration allows interrupt control for up to four processors.

FIG. 7 shows a specific setting example of the above-mentioned LEVEL. The priority of the task can be set to the kernel operating system (O3,), I10 driver O8, or O8 other than the above.
8. Then assign the most important bits to the top two bits, such as user application.

If the above-mentioned allocation is made to all 8-bit PRI or (M) in this way, the processing priority of the processor will be as follows.

PRI,,=rOO000000J Highest processing priority (least susceptible to interrupts) PR1,,
,=rl 1111111J Lowest processing priority (easiest to receive interrupts) As described above, according to this embodiment,
At the time of occurrence of an interrupt, the processing unit 8 of each processor outputs a signal PR1, which indicates the priority of the process determined from the interrupt availability of the processor, the priority level of the task being executed, the processor number, etc. A signal for comparing the processing priorities coming from the processors X PRI O-?
* and is compared by the interrupt control unit 9, and the processor with the lowest priority is made to handle the interrupt. Therefore, for example, if a processor with a high processing priority is performing some processing, if there is a processor that is not processing at all, that processor has a lower processing priority and is not processing at all. Therefore, a processor with a higher processing priority will not be interrupted.

Note that in this embodiment, there are three processors and one input/output device.
Although the case has been described with respect to the number of processors, the present invention is not limited to this, and a larger number of processors may be used, and the number of processors may be two. Further, a device that outputs a signal indicating the occurrence of an interrupt is not limited to an input/output device, and may be any other device.

Further, in this embodiment, the processor with the lowest processing priority is made to process the interrupt, but any processor with a relatively low processing priority may be selected.

[Effects of the Invention] According to the present invention, since a processor with a low processing priority is caused to process the interrupt when an interrupt occurs, system processing efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an interrupt control method according to the present invention, FIG. 2 is a block diagram showing an example of a conventional interrupt control method, and FIG. 3 explains the operation of the interrupt control section of this embodiment. Flowchart, FIG. 4 is a block diagram of the interrupt control unit of this embodiment, FIG. 5 is a circuit diagram of the same specific interrupt control unit, FIG.
The figure is also a more detailed explanatory diagram. 1-1.1-2.1-3 is a processor, 8-1゜8-2
．． 8-3 is a processing unit having means for indicating processing priority; 9-
1.9-2.9-3 is an interrupt control unit as a comparison means,
INT is a signal indicating an interrupt request or interrupt occurrence, EN
B is a bit indicating the interrupt enable/disable state, LEVEL is a bit indicating the priority level of the task being executed, and PRl. 7. is a signal representing the processing priority, and XPRIo-t* is a signal for comparing the processing priority. "1": Interruption allowed rllllllJ: The task with the lowest priority is running
Figure 7 Detailed explanation of task priority level

Claims (1)

[Claims] In an interrupt control method for a multiprocessor system that controls interrupt requests to a plurality of processors, the interrupt control method is determined by combining processing priority factors of the processors, including the interrupt enable/disable state of each processor and the priority level of the task being executed. An interrupt control method comprising: means for indicating the processing priority of each processor; and comparison means for comparing the processing priorities among the processors and transmitting an interrupt request to a processor with a lower priority.