JPH0345946B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a processor processing capacity distribution method for dynamically distributing the processing capacity of a control system of a digital exchange for immediate exchange and storage/exchange according to traffic load fluctuations. It is.

Background of the Technology Conventionally, the configuration of a switch control system in a switching system in which calls for immediate switching and calls for store and forward switching are accommodated in a switch via the same time division multiplex transmission path is as follows.
It is generally considered that for users who receive an immediate exchange service, an immediate exchange processor performs exchange processing, while for users who receive a store-and-forward service, a store-and-forward processor performs exchange processing. As a conventional technique that is actually in practical use, it is common to use a single processor to control both the immediate and store-and-exchange modes. (For example, Nippon Telegraph and Telephone Public Corporation Telecommunications Research Institute,
Research practical application report, V _OL 23 No. 9, Ikeda and 2 others DDX-
1 Data Exchange System Pages 1760-1761 (Fig. 5) Prior Art and Problems In the conventional conventional method in which a processor for immediate exchange and a processor for store-and-forward are provided independently, calls for immediate exchange and processors for store-and-forward are separated. When call traffic is biased to one side, the processors that process the other switching mode are almost always unused, resulting in a drawback that the processors cannot be used effectively. In addition, in the latter processor method, which has been used in practice in the past and processes both the immediate exchange and store-and-forward exchange modes, conventionally, the exchange processing is performed by distributing the processing ratio of both exchange modes to a constant level. Alternatively, it was common to allocate call processing to processors in the order of call arrival. However, when the processing ratio is distributed at a constant rate, there is a drawback that if the traffic balance between immediate calls and stored calls is biased to one side, the ability of the processor cannot be used effectively.
When short message stored calls arrive with high traffic, the processing of immediate calls is significantly delayed, resulting in the drawback that the quality of service in both exchange modes cannot be guaranteed.
For this reason, there has been a demand for a system that can dynamically allocate the processing capacity of an exchange control system that simultaneously processes different communication modes in accordance with traffic fluctuations.

Purpose of the Invention The present invention aims to eliminate the above-mentioned drawbacks.
In a digital switching system that simultaneously exchanges multiple communication forms, such as immediate calls and stored calls, it is necessary to provide a means for instructing the control processor about the current status of traffic fluctuations, or to monitor the above-mentioned traffic fluctuation status. It is characterized by being able to variably allocate memory access cycles that can be used by programs for immediate exchange and store and exchange using instruction information, and its purpose is to use multiple exchange modes such as immediate exchange and store and exchange. It is an object of the present invention to provide a processor processing capacity allocation method that dynamically controls the capacity of processors for processing in accordance with fluctuations in incoming traffic. The drawings will be explained in detail below.

Embodiment of the Invention FIG. 1 shows a first embodiment of the invention. In the present invention, an immediate call means that the exchange selects the line to be connected based on the selection signal sent from the calling party, holds the call route during the call setup period, and directly receives data information between terminals. A general term for immediate calls based on the instant switching system that has the characteristics of
A storage device that temporarily stores the selection signal and data information sent from the calling party, and sequentially transfers the stored data information to other exchanges in the network according to the destination determined by the selection signal, thereby sequentially delivering it to the destination terminal. A general term for stored calls based on the switching system. Hereinafter, each will be referred to as an immediate call and a stored call.

Reference numeral 100 in FIG. 1 is a register array having entries containing information necessary for each write control access cycle of each time slot on the transmission path in order to import the transmission path information into the exchange. This is a diagram showing the usage. In Figure 1, 100 for data write access from the transmission path.
Indicated by 1. The information stored in the register array 100 includes a flag for identifying whether the call is an immediate call or a stored call for each channel, and information regarding the immediate call address and the stored call address. These pieces of information are initialized by the control processor at the time of call setup, and are held at the corresponding address in register array 100 until the call is disconnected. 101 is a counter 10 that operates in synchronization with the transmission line clock.
a decoder 10 that generates an address for accessing the register array 100 according to the contents of 2;
3 and 104 are counters for counting the number of stored calls and immediate calls that existed in one data frame, respectively, and 105 and 106 are counters for counting the number of stored calls and immediate calls that were counted for each data frame by counters 103 and 104, respectively. Number of calls (register array 100
This is an addition circuit for adding, over N data frames, the number of entries in which the contents of flags indicating the occurrence of stored calls and immediate calls are "1". The count results of the counters 103 and 104 are reset by the signal indicating the head of one data frame, and the addition circuits 105 and 106 are enabled for addition operation for each data frame by the signal indicating the head of one data frame.
It is reset every N data frames. 107,
108 is a 1/N arithmetic circuit for averaging the count values of the adder circuits 105 and 106 over N data frames (however, the decimal part is rounded up and only the integer part is output); It will be reset. 109 is a 1/N calculation circuit 10
These are registers for storing the calculation results of 7,108, and F# ¹ and F# ² are the first field and F# 2, respectively.
The second field is updated every N data frames. 120 is the register array 1 from the processor.
This is a selector for selecting the input address to be input and the output of the counter 102 in order to perform initial setting of 00 or maintenance reading. The output of the register 109 is connected to the input port of the processor, and the processor can grasp the traffic fluctuation situation by reading the contents of the register 109 from the input port to the internal register via the data bus in response to an input command. can. Therefore, if the processor executes the above input command periodically (for example, every 1/N data frame), the execution priorities of the immediate exchange program and the store and exchange program can be adjusted in real time according to traffic fluctuations. Therefore, it is possible to provide a criterion for optimally allocating the processing power of the processor to the execution of various exchange programs.

Also, as shown in FIG. 1, instead of directly reporting the output of the register 109 to the processor, the output of the register 109 is subjected to the calculation results shown in the flowchart of FIG. 2 and then reported to the processor. It is also possible to take In Figure 2,
The type of information to be notified to the processor is 0, A, B,
There are five types, C and D, and they are classified as follows.

0... Value of first field = Second field: Immediate calls and stored calls occur at the same rate, A... Value of first field > 3 x (value of second field), value of second field ≠ 0: Immediate When call generation is predominant, B... Value of second field > 3 × (value of first field), value of first field ≠ 0: When call generation is predominant, C... Only accumulation call generation D...If only an immediate call occurs, the information type shown here is only an example, and the average number of dynamics of the immediate call switching program and stored call switching program is also taken into consideration. It is also easy to notify the processor as more detailed information. This algorithm can be applied to existing hardware logic circuits, read-only memory (ROM),
This can be realized using a well-known technique using a content addressable memory (CAM).

FIG. 3 shows a second embodiment of the present invention showing the relationship among a time division multiplex transmission line, a transmission line data storage unit, and a processor. 301 is a storage cycle allocation control unit that can variably allocate memory access cycles that can be used by programs for immediate exchange and storage and exchange according to traffic fluctuations; 302 is a signal line for indicating an address for immediate calls; and 303 is a signal line for indicating an immediate call address. stored call address generator,
304 is a control processor that processes exchange programs and the like. 305 is a selection for switching the immediate call address instruction signal input via the immediate call address instruction signal line 302, the output signal of the stored call address generator 303, and the output of the processor 304 based on the control of the storage cycle allocation control section 301; 306 is a control unit, and 306 is a storage control unit that includes a directory used in a normal storage system to perform virtual address → real address conversion mechanism and cache address conversion, etc.; 307 is a storage control unit that stores transmission path data and programs; A storage unit 308 for storing data is a time division multiplex transmission line.

A fourth embodiment of the storage cycle allocation control unit 301 is described below.
As shown in the figure. Reference numeral 402 in FIG. 4 is a register array having entries containing necessary information for each access cycle corresponding to transmission line access among the access cycles of the storage unit 307, and 402 for writing data from the transmission line. Two surfaces are prepared for reading data to the transmission path and 4002 for reading data to the transmission path. n is the number of channels within one data frame. 102
108 and 120 are circuit blocks having the same functions as those shown in FIG. The output from the ROM412 is W for transmission line data write control, R
is a control signal for transmission line data read control, C is for immediate exchange program execution, P is for storage program execution, and M is for management program execution.
C, P, and M are allocation control signals for executing various programs. 409 is a 1/N calculation circuit 107,1
410 is a latch circuit for latching the output of the associative memory 409 with the identification signal of the Nth data frame and holding the same information until the next Nth data frame; 411 412 is a ROM whose input address is the output of the addition circuit 411; 413 and 414 are storage units for immediate calls and stored calls, respectively. This is a selection circuit for selecting a write/read address to ROM 412 based on a write/read control signal of ROM 412.

By using the storage cycle allocation control section having the configuration shown in FIG. ,107
It can be calculated by This information can thus be used to determine the number of memory access cycles available for execution of various switching programs for immediate call processing and stored call processing.

The algorithm shown in FIG. 2 can be easily realized using the associative memory 409. For example, FIG. 5a shows a specific example of the associative memory 409, and FIG. A general block of memory is shown. Figure 6 shows ROM412
A specific example is shown below.

The associative memory 409 in FIG. 5a is an example divided into three fields, and in this embodiment, the first and second fields
Fields F#1 and F#2 each have 1/N
The average value (integer part) of the number of calls over N data frames of immediate calls and accumulated calls output by the arithmetic circuits 108 and 107 is stored in advance. In the example of FIG. 5a, all possible states are expressed in the first and second fields, so if the number of channels in one data frame is n, then
The number of entries for 9 is n(n+1)/2. The number of bits M required for the first and second fields is [l _pg2
n]+1 (however, [ ] is a Gauss symbol). In general, the associative memory memory 409 stores input search data (the first,
If content matching the content of the second field (corresponding to the content of the second field) is found in the associative memory memory, other data included in the address where the content is stored (corresponding to the content of the third field F#3 in Figure 5a) is found in the associative memory memory. (corresponds to the content)
This function is also used in the present invention. In the example shown in FIG. 5a, the third field is used to access the ROM 412 in accordance with the average number of immediate calls and stored calls within the N consecutive data frames indicated in the first and second fields. Stores the start address of. In this example, the types of start addresses are 0, α, β, γ,
There are five types of δ and five types of memory access cycle allocation methods that can be used by various programs, but this number can be expanded arbitrarily if it is necessary to finely control each allocation cycle. be. The basic concept of how to allocate the start addresses 0, α, β, γ, and δ in this embodiment is that when the ratio of immediate calls and stored calls is almost the same (the processing ratio of calls for immediate switching and stored switching,
In other words, set it to 0 if the ratio of immediate calls to stored calls is about 1:1), and set α if the ratio of immediate calls is significantly higher than the ratio of stored calls (the ratio of immediate calls to stored calls is 3:1 or more). ,) If the ratio of stored calls is significantly higher than the ratio of immediate calls (ratio of stored calls:immediate calls is 3:1 or more), β is set, and when only immediate calls are occurring, γ is stored. If only a call is occurring, δ is assigned. Addition circuit 411 in FIG.
As a result, the output of the content addressable memory 409 (the same information is held within the time period of N consecutive data frames) and the output of the counter 102 that counts the channel number within one data frame are added, and the result of this addition is Access ROM412.

Figure 6 shows the case where the number of allocated cycles for executing the exchange program in one data frame is 4.
This shows an example of the ROM412. In this embodiment, as in the case of FIG. Only the processing of , the processing ratio of immediate exchange and storage and exchange is about 1:3, the processing ratio of immediate exchange and storage and exchange is about 3:1, and the processing ratio of immediate exchange and storage and exchange is about 1:1, This diagram schematically shows the allocation status of δ, γ, β, α, and 0 to each. C, P, W, R, and M are the same control signals as in FIG. 4, and C, P, and M are used for assignment control for executing various programs. Depending on the ratio of the number of immediate calls and stored calls, the ROM412
address (output of content addressable memory 409) +
(output of the counter 102), the contents of the ROM 412 corresponding to the address are read out, and it is possible to specify how memory access cycles of the storage unit 307 are to be allocated.

FIG. 7 shows an example of an allocation cycle for accessing the storage unit 307 within one transmission cycle, that is, the duration of one channel on the time division multiplex transmission line 308. T307 is storage unit 3
07 cycle time is shown. The transmission line data write cycle W and the transmission line data read cycle R are cycles that are constantly accessed periodically, and the management program execution cycle M is used for running the OS (operating system), etc., one cycle per transmission cycle. This cycle is reserved for memory access, and the remaining cycles can be distributed to the exchange program processing cycle P for running the storage and exchange program or the immediate exchange program. The method of distributing memory access cycles for each program execution can be specified by the output signal of the ROM 412.

Although four cycles were assumed as the number of memory access cycles for executing the program shown in FIGS. 6 and 7, this value can actually be increased by increasing the operating speed of the storage section. For example, when one transmission cycle time = 600 _osec and the operation cycle time of the storage unit = 30 _osec , the number of memory access cycles allocated for running the immediate exchange and storage/exchange program is 600/30-3 = 17. Cycles can be distributed optimally in both exchange programs according to the number of calls that occur.

FIG. 8 shows in detail the embodiment of the present invention shown in FIG. 3 using the storage cycle allocation control section 301 shown in FIG. 4. 800, 801, 80
2,803,804 are stored call address generators 30
3, and 800 is a processor 304.
801 is a decoder; 802 is a selection circuit for selecting an address signal for initial setting from the register array 402 or a stored call address signal from the register array 402;
is a register array for selecting an entry from stored call addresses. This register array 8
02 stores an address increment value for the stored call storage unit 307, and the increment value is used to calculate the first address to be accessed next time of the area where the data of the stored call is stored in the storage unit 307. The address in the current entry is added to the address in the current entry for each access using the adder circuit 804, and the result is replaced with the old address value and stored in the same entry. Reference numeral 803 denotes a selection circuit for selecting from the output of the adder circuit 804 or the initial setting data signal from the processor 304. In FIG. 8, when the storage cycle allocation control unit 301 is outputting the signals W and R for accessing the transmission path, it is possible to control writing/reading from the transmission path to the storage unit 307, and the W, R When no signal is output (i.e. C for program execution,
When the P and M signals are being output), the processor is configured to be able to write to/read from the memory section 307. AB is address bus,
DB indicates data bus. Note that the processor 304
The ROM 412 output signal, which is the allocation control signal (indicated by ○* in Figure 8) for executing various programs, is constantly taken into the internal register from the specified input port, thereby allowing the execution of various exchange programs. The memory access cycles to be used can be arbitrarily allocated according to traffic fluctuations. An embodiment of a processor for implementing this method is shown in FIG.

In FIG. 9, 301 to 308 are the same as those shown in FIG. The processor 304 uses program counter #1 of 901, internal register group #1 of 902, etc. to execute a program for immediate call exchange,
This method uses program counter #2 of 903, internal register group #2 of 904, etc. to execute a program for exchanging stored calls, and controls switching of these hardwares using decoder 900 which receives the output of ROM 412 as input. This is an aspect of the invention, and shows the configuration when the arithmetic circuit 905 is used in common. Note that in the storage unit 307 of FIG.
0 indicates transmission path data, 311 indicates an immediate call exchange program, and 312 indicates a stored call exchange program.

In the description of the present invention so far, the method uses the average value of the number of calls generated over N consecutive data frames as a criterion when allocating memory access cycles for executing an immediate exchange program and a store-and-forward program. However, this judgment criterion is
The present invention is not limited to those obtained by the above method. For example, the difference in the number of calls that occur between two consecutive data frames (that is, the number of newly generated calls within one data frame) may be used as the determination criterion. An embodiment of a storage cycle allocation control section based on this concept is shown in FIG. The same reference numerals as in FIG. 4 indicate the same parts. 11,1 in Figure 10
2 is a latch circuit for storing the number of calls counted one data frame before the number of calls counted by the counters 103 and 104; 103 count value), (the count value of the latch circuit 12) and (the count value of the counter 104). (treated as 0).
The subtraction circuits 13 and 14 access the associative memory 409 with their contents updated every data frame. The latch circuit 410 holds the output of the content addressable memory 409 for one data frame period until the next one data frame ends. Therefore, the 10th
If the configuration shown in the figure is used, it becomes possible to allocate memory access cycles for executing various exchange programs in response to fluctuations in the number of generated calls for each data frame.

In the explanation so far, we have assumed that data always exists on the transmission path, and have allocated W cycles and R cycles for transmission path access within one transmission cycle, but this method can be easily modified as follows. It can be expanded to In other words, a circuit is installed on the incoming transmission line to detect that there is no data to be imported into the exchange (for example, 0 consecutive, 1 consecutive, continuous flag patterns, etc.), and this detection circuit detects valid data on the incoming transmission line. If it is detected that the program does not exist, the R cycle is allocated for program execution. Regarding the outgoing transmission path, even if there is no data to be read from the exchange to the channel position on the outgoing transmission path, it is also possible to allocate the R cycle as a memory access cycle for program execution. As a criterion for allocating this memory access cycle to execution of various programs,
The methods described so far are merely examples, and various modifications are possible, and the present invention is not limited to these embodiments.

Furthermore, when handling stored calls as a possible example, the number of arriving packets is counted for each data frame without using the number of generated calls as a parameter, and the difference between this counted value between two consecutive data frames or N data is calculated. A configuration in which the average count value over frames or the like is used as a parameter can also be easily realized. In addition, when there is a difference in the average number of dynamic steps run per call for the store-and-forward program and the immediate-switch program, the evaluation parameters are optimally weighted for each communication mode based on the evaluation criteria described above. It is also possible to decide the distribution of execution cycles to be allocated. Further, the present invention may be implemented by using a read-only memory ROM in place of the content addressable memory 409 shown in FIG. 5, and by configuring a logic circuit for following the flowchart shown in FIG.
FIG. 11 shows an example of a ROM 11 having the same function as the associative memory memory 409 shown in FIG. 5a.
An example of the configuration of 0 is shown below.

Effects of the Invention As explained above, according to the present invention, the ability of the processor to process multiple exchange modes such as immediate exchange and store-for-exchange can be dynamically adjusted to run both exchange programs in response to fluctuations in incoming traffic. This makes it possible to allocate the data in the optimum ratio for each use, and for example, it is possible to make maximum use of the processing capacity of the control system of an exchange that integrates line switching and packet switching.

In the description of the present invention, a case has been shown in which the storage unit 107 is composed of a single storage hierarchy, but as shown in Japanese Patent Application No. 58-99239 "Digital Exchange" The present invention has the advantage that it can be similarly applied even when the system is composed of hierarchies.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of the first embodiment of the present invention, FIG. 2 is a flowchart of arithmetic processing of the output of the register 109 of the present invention, FIG. 3 is a second embodiment of the present invention, and FIG. 4 5A is an embodiment of the storage cycle allocation control unit 301 of the system configured according to the present invention, FIG. 5A is an embodiment of the associative memory memory 409 of the present invention, FIG. Figure 6 shows the ROM 412 when the number of cycles allocated for executing the exchange program in one data frame is 4.
An example of FIG. 7 shows the storage unit 3 in one transmission cycle.
FIG. 8 shows an example of the detailed configuration of the second embodiment of the present invention, and FIG. 9 shows an example of the memory access cycles used when executing various exchange programs of the present invention according to traffic fluctuations. Example of arbitrarily allocating according to the
FIG. 0 shows an embodiment of the storage cycle allocation control section of the present invention, and FIG. 11 shows an embodiment of a ROM configuration corresponding to the content addressable memory 409 of the present invention. 11, 12... Latch circuit, 13, 14... Subtraction circuit, 100... Register array, 101...
Decoder, 102, 103, 104... Counter, 105, 106... Addition circuit, 107, 10
8...1/N arithmetic circuit, 109...Register, 1
20...Selector, 301...Storage cycle allocation control unit, 302...Immediate call address instruction signal line, 303...Stored call address generator, 304...
...Processor, 305...Selection control section, 306...
...Storage control unit, 307...Storage unit, 308...Time division multiplex transmission line, 310...Transmission line data, 31
DESCRIPTION OF SYMBOLS 1... Program for immediate call exchange, 312... Program for stored call exchange, 402... Register array, 409... Content addressable memory, 410... Latch circuit, 411... Addition circuit, 412...
ROM, 413, 414...Selection circuit, 800...
... selection circuit, 801 ... decoder, 802 ... register array, 803 ... selection circuit, 804 ... addition circuit, 900 ... degoder, 901, 903 ...
...Program counter, 902, 904...Internal register group, 905...Arithmetic circuit, 110...
ROM.

Claims (1)

[Scope of Claims] 1. A storage unit that receives access from a time division multiplex transmission path and from a program, and stores data from a calling terminal sent via the time division multiplex transmission path in the storage unit. Then, the control processor performs exchange processing on the accumulated data using a program stored in the storage unit, and sends the exchanged data to the receiving terminal to perform an immediate call by immediate exchange and a stored call by store and exchange. In a digital exchange that exchanges terminal groups with different communication formats, the number of generated instant calls and stored calls with different communication formats is calculated on the time division multiplex transmission path to which the instant calls and stored calls are assigned time slots. means for counting over a plurality of data frames; and inputting the counted results or the results of arithmetic operations on the counted results, and inputting the counted results or the number of generated calls over the counted consecutive data frames to the control processor. According to the calculation result of
storage means for instructing judgment criteria for variably allocating and distributing memory access cycles used by programs for immediate exchange and storage and exchange according to traffic fluctuations in the processing capacity of the control processor; 1. A processor processing capacity allocation system characterized in that the allocation of processing capacity of a processor is variably controlled in accordance with fluctuations in the number of generated calls in communication modes of the immediate calls and stored calls. 2. The storage means includes a first storage device that takes as an input address the counting result or a result of performing an arithmetic operation on the counting result, and a first storage device that uses the output of the first storage device as an input address and sends a message to the control processor. 2. A processor processing capacity allocation system according to claim 1, further comprising a second storage device for outputting execution cycle allocation information.