JPH0345409B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a small electronic device equipped with a rewritable nonvolatile memory circuit.

In recent years, as the operating voltage of rewritable nonvolatile memory elements such as MNOS memory elements has been decreasing, the use of these nonvolatile memory elements in small electronic devices such as electronic watches is being considered.

Application methods for these electronic watches include, for example, a storage device for storing the frequency division ratio set externally in a method that uses a variable frequency divider circuit to adjust the frequency, and a temperature compensation for the crystal oscillator circuit. In this method, the compensation level is used as a storage device to set and store the compensation level from the outside, and in both cases, writing is performed using a higher write power source than the external one. However, due to advances in technology, it has now become possible to fully rewrite the write voltage using the internal power supply of the electronic watch.

The present invention focuses on the above points, and provides a small electronic device with improved functionality by rewriting the nonvolatile memory built into the small electronic device such as an electronic watch using an internal power source. It is an object.

The gist of the present invention for achieving the above object is to provide an information setting circuit that allows information to be set from the outside in a small electronic device powered by a small battery, and a memory for setting information of the information setting circuit. A nonvolatile memory circuit for detecting a voltage drop in the battery and a voltage detection circuit for detecting a voltage drop in the battery are provided, and when the battery voltage drops, the output signal of the voltage detection circuit is used as a write signal to write information in the information setting circuit to the nonvolatile state. The purpose is to store it in a memory circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic timepiece which is an embodiment of the present invention will be described below with reference to the drawings.

First, before explaining the present invention, general characteristics of electrically rewritable nonvolatile memory will be explained.

FIG. 1 is a characteristic diagram showing the characteristics of a P-channel nonvolatile memory that performs electrical writing and erasing.
When a high positive voltage is applied to the gate electrode of a nonvolatile memory, the threshold voltage (hereinafter abbreviated as Vt) of the nonvolatile memory becomes in the depletion direction, and conversely, when a high negative voltage is applied to the gate electrode, the threshold voltage (hereinafter abbreviated as Vt) becomes in the depletion direction. Vt shows the characteristic of operating in the enhancement direction. Therefore, by determining whether Vt is high or low with respect to an appropriate reference potential _VR , the state of the nonvolatile memory can be defined as a binary value, and can be logically read as "1" or "0". .

In order to store data in the above-mentioned nonvolatile memory (hereinafter simply referred to as memory), there are two methods: selective writing or selective erasing.
There are two possible methods.

Writing here is defined as moving Vt in the depletion direction, and erasing is defined as moving Vt in the enhancement direction. Usually, a selective writing method is common. In this case, erasure is performed all at once. That is, erasing is performed unconditionally on a plurality of memories all at once, and then selectively writing is performed only on the necessary memories at the time of writing.

FIG. 2 shows an example of a non-volatile memory circuit, in which the source electrodes and substrate electrodes of the non-volatile memories 4a, 4b... are connected to the potential Vdd, and the drain electrodes are connected to the load resistors 3a, 3b, respectively.
The gate electrodes are connected to the write/erase voltage application terminal V _M through the resistors 1a, 1b _, respectively, and the drain electrodes of the control transistors 2a, 2b, etc. connected to. The source electrodes and substrate electrodes of the transistors 2a, 2b... are diodes 5a, 5b, respectively.
, and each gate electrode becomes _a data input line D ₁ , D ₂ . . . Erase this circuit
The writing procedure is as follows.

First, when the terminal V _M is pulled to a negative high voltage, no matter what state the transistors 2a, 2b... are in, they are blocked by the diodes 5a, 5b... and the resistors 1a, 1b... etc. In each case, no current flows. Therefore, the memories 4a, 4b
Since a negative high voltage is applied to each gate electrode of..., the memories 4a, 4b... are all in an enhancement state.

Next, when a positive high voltage is applied to the terminal V _M , if the potential of the data input line _D1 is at the Vdd level, the transistor 2a is in the on state, so the transistor 2a and the diode are Current flows through 5a and no high voltage is applied to the gate electrode of the memory 4a, so the memory 4a remains in the enhancement state.

Also, when a positive high voltage is applied to the terminal V _M ,
For example, when the potential of the data input line _D2 is V _SS , the transistor 2b is in an off state, so a high positive voltage is applied to the gate electrode of the memory 4b, and the memory 4b changes to a depletion state. .

Applying the actual voltage value to the nonvolatile memory circuit shown in FIG. 2 where selective writing has been performed through the above series of operations, we find that V _{DD is}
Assuming that memory 4a is written to with 1.5V and the voltage supplied to the write/erase voltage application terminal V _M is ±25V (write voltage +25V erase voltage -25V) and memory 4b is put into the erased state, the voltage of memory 4b is Vt is +4V, and Vt of the memory 4b is -4V. Therefore memory 4
By setting the gate electrodes of a and 4b to the reference potential of OV, memory 4a is turned on and memory 4b is turned on.
Since it is in the OFF state, a "1" signal at the _VDD level is output only to the output terminal _O1 of the memory 4a.

The general operation of the nonvolatile memory circuit has been described above, and the configuration of the electronic timepiece equipped with the nonvolatile memory of the present invention will be explained below with reference to FIG. 3, which is a block diagram of the electronic timepiece according to the present invention.

In FIG. 3, 10 is a clock circuit, 11 is a reference oscillation circuit, 12 is a frequency dividing circuit that generates a clock signal φ ₀ , 13 is a clock circuit that counts the clock signal φ ₀ and generates time information; 14 is a calendar circuit that generates calendar information; 15 is a display selection circuit; 1
6 is an exclusive OR gate 17 (hereinafter referred to as
18 is a frequency setting circuit that supplies a frequency setting signal to the _frequency adjustment circuit 16;
The frequency setting circuit 18 has a reversible counter configuration that performs addition and subtraction in accordance with pulse signals supplied to the U terminal and D terminal, and furthermore, the frequency setting circuit 18 has a reversible counter configuration that performs addition and subtraction in accordance with pulse signals supplied to the U terminal and D terminal, and furthermore, the frequency setting circuit 18 has a reversible counter configuration that performs addition and subtraction according to pulse signals supplied to the U terminal and D terminal, and furthermore, the frequency setting circuit ₁₈ has a reversible counter configuration that performs addition and subtraction in accordance with the pulse signals supplied to the U terminal and the D terminal. The conditions of the output terminals Q ₁ to Qn can be forcibly specified according to the information signal input in parallel to In. Reference numerals 19, 20, and 21 denote waveform shaping circuits, which input operation signals for an up switch 22 for frequency adjustment, a down switch 23, and a time adjustment switch 24, and generate addition pulses P _U , subtraction pulses _PD , and correction pulses P _C. Output. 25 is a digital display device, into which information signals from the timekeeping circuit 13 and calendar circuit 14 constituting the clock circuit 10 and setting information of the frequency setting circuit 18 are input;
Switch and display time and calendar information and frequency setting information. 26 is a battery for power supply; 27 is a voltage detection circuit for detecting a voltage drop of the battery 26;
When it is detected that the terminal voltage of the battery 26 has fallen below a predetermined value, a warning signal _EBD of logic "1" is generated at the BD terminal. A nonvolatile memory circuit 28 is composed of a nonvolatile memory 28a and a drive circuit 28b that generates a high voltage for writing and erasing the nonvolatile memory 28a.
Data terminals D ₁ to Dn of the nonvolatile memory 28a
is applied to each output terminal Q ₁ to Qn of the frequency setting circuit 18,
Further, the initial terminal _O0 is connected to the preset terminal PR, and the output terminals _O1 to On are connected to the input terminals _I1 to In, respectively.

Next, the operation of the electronic timepiece having the above configuration will be explained.

Frequency divider circuit 12 and frequency adjustment circuit 1 shown in Fig. 3
6, EX/OR gate 17, frequency setting circuit 18
The variable frequency dividing device constituted by is a well-known frequency adjusting device that is generally employed in electronic watches. By inputting the clock signal φ ₀ having a period of seconds, the clock circuit 13 and the calendar circuit 14 generate time information and calendar information, and when this information is selected by the display selection circuit 15, the digital display device 25 Normally, the time is displayed.

Next, a description will be given of the operation when the wearer notices that the time accuracy of the electronic watch has deteriorated in this state and performs speed adjustment.

First, by operating a speed/speed adjustment mode designation switch (not shown), a speed/speed confidence signal FC is generated.
By setting the frequency setting circuit 18 to a reversibly operable state and simultaneously switching the display switching circuit 15 to a frequency setting information selection state, the digital display device 25
The setting information output from the M terminal of the frequency setting circuit 18 is displayed.

In this state, the frequency setting circuit 18 counts up according to the addition pulse P _U supplied to the U terminal, and also counts up according to the subtraction pulse P _D supplied to the D terminal.
By counting down according to the output terminal
Change the output signals of Q ₁ to Qn. And the frequency adjustment circuit 1 connected to these output terminals Q ₁ to Qn
The clock signal φ ₀ is readjusted to the correct 1-second period by controlling the frequency division ratio according to No. 6, and the amount of readjustment in this case can be confirmed by the change in the display on the digital display device 25.

Therefore, if the electronic watch has an error in time delay, the wearer operates the up switch 22 to adjust the speed and speed, and confirms the amount of adjustment on the digital display device 25. Similarly, the speed and speed can be adjusted by operating the down switch 23. When the adjustment is completed, the adjustment mode designation switch is operated to cancel the adjustment signal FC, thereby returning to the normal time display state.

Next, the nonvolatile memory circuit 2 which is a feature of the present invention
The operation of No. 8 will be explained.

During the normal operating state of the electronic watch, that is, while the voltage of the battery 26 is higher than a predetermined detection level, the output terminal BD of the voltage detection circuit 27 is held at logic "0" and thus constitutes a non-volatile memory circuit 28. The drive circuit 28b is in an inactive state, and the nonvolatile memory 28a is in an erased state, so no preset signal is output. The preset signal is not output, so the clock circuit 10
No state setting is performed for .

When the terminal voltage gradually decreases as the battery 26 is exhausted from this normal operating state and approaches the operating limit voltage value of the clock circuit 10, the voltage detection circuit 27 operates at a predetermined detection level and outputs Outputs warning signal E _BD to terminal BD. The drive circuit 28B, which is supplied with this warning signal E _BD as a write signal to the write terminal W, is a write/erase voltage application terminal.
A write voltage of +25V is generated at V _M to put the nonvolatile memory 28a into a write state. As a result, the nonvolatile memory 28a stores the information of the frequency setting circuit 18 supplied to the data terminals _D1 to Dn.

When the life of the battery 26 ends in this state, the electronic timepiece stops operating, but the nonvolatile memory 28a continues to store the written information.

Therefore, when replacing the battery and installing a new battery 26, the clock circuit 10 resumes operation and at the same time the frequency setting circuit 18 receives a preset signal from the _O0 terminal of the non-volatile memory 28a to the PR terminal. The storage information of the nonvolatile memory 28a supplied to the input terminals _I1 to In is preset again, and the variable frequency division operation is restarted. Then, in order to set the time, the person carrying the phone presses the time adjustment switch 24.
When the first operation signal P _C is supplied as an erase signal to the erase terminal E of the drive circuit 28b constituting the nonvolatile memory circuit 28, the drive circuit 28
b generates an erase voltage of -25V at the write/erase voltage application terminal _VM to put the nonvolatile memory 28a in an erased state. As a result, the output terminals O ₀ and O ₁ to On of the nonvolatile memory 28a all become logic "0", so the frequency setting circuit 18 is released from the preset state, and the up switch 22 and the down switch 23 can again perform slow and fast adjustment operations. Become.

Next, an example of a specific configuration of the nonvolatile memory circuit 28 shown in FIG. 3 will be explained with reference to the block diagram shown in FIG.

The drive circuit 28b includes a booster circuit 30 that generates a high voltage V _DDH of 25V, a capacitor 31 for storing the high voltage V _DDH , and a voltage application terminal V for writing and erasing the high voltage V _DDH stored in the capacitor 31. 6 for switching output to _M as write voltage or erase voltage
switches 32a to 32f, the booster circuit 30
a timer 33 that controls the operating time of the switch, a timer 34 that controls the switches 32a to 32f, and two set-reset type flip-flops (hereinafter referred to as
(abbreviated as RS/FF) 35, 36, two AND gates 37, 38, OR gate 39, inverter 4
0 and a pulse generator 41, and the nonvolatile memory 28a is also provided with a write/erase voltage application terminal V _M , a ground terminal G, each data terminal D, and each output terminal O, as shown in FIG. It is a P-channel type nonvolatile memory.

Next, the nonvolatile memory circuit 28 having the above configuration
The write and erase operations will be explained.

First, the write operation of the nonvolatile memory 28a in the erased state will be explained.As explained in FIG.
When E _BD is supplied, it is a drive mode storage means.
By setting RS・FF35, the output Q becomes "1" and the output becomes "0", and the AND gate 3
7 is turned ON and AND gate 38 is turned OFF.

Also, the rising signal of RS/FF35 is sent to OR gate 39.
After passing through, it becomes a pulse by the pulse generator 41 and sets the RS/FF 36. As a result
When the output Q of the RS・FF36 becomes "1", the booster circuit 30 starts operating, and the generated high voltage
While charging the capacitor 31 via the switches 32a and 32b with V _DDH in the ON state,
When the output terminal of the RS/FF 36 becomes "0", the reset of the timer 33 is released and the counting operation of the clock φc is started.

When the predetermined operating time of the timer 33 has elapsed, an output signal φt is generated from its output terminal Q to reset the RS/FF 36, thereby stopping the operation of the booster circuit 30 and the timer 33, and at the same time starting the timer 34. .

The timer 34 generates a “1” level signal φa at its output terminal Q for a certain period of time from its start;
This signal φa turns off the switches 34a and 34b via the inverter 40, and also turns off the switches 34a and 34b.
The signal passes through the AND gate 37, which is turned on by the output terminal Q of 5, and switches 32c and 32e.
Turn it on. As a result, the high voltage V _DDH charged in the capacitor 31 is supplied to the write/erase voltage application terminal V _M as a write voltage of +25V via the switches 32c and 32e, so that the data terminal D
The nonvolatile memory 28a whose logic is "1" is put into a write state. Then, when the operation of the timer 34 ends and the signal φa disappears, the drive circuit 28b turns off the switches 32c and 32e and turns on the switches 32a and 32b, becoming ready for a write/erase operation.

The P channel type nonvolatile memory of the nonvolatile memory 28a which has been put into the write state by the above write operation is turned on by holding its gate at the reference potential of OV via a resistor, and the output terminal O
Outputs a “1” level signal to

Next, the erasing operation of the nonvolatile memory 28a in the write state will be explained.

As explained in FIG. 3, the correction pulse Pc from the waveform shaping circuit 21 is used as an erase signal by the drive circuit
When supplied to the erase terminal E of 8b, the RS・FF 35 is reset, so that the output Q becomes "0", the output Q becomes "1", and the AND gate 37 is turned off.
Turn on AND gate 38.

Similarly to the write operation described above, the RS/FF 36 is set by the rising signal of the RS/FF 35, and after a series of step-up operations are performed, the signal φa from the timer 34 is output. φa
is in ON state due to the output of RS・FF35
Passes through AND gate 38 and switches 32d, 3
Turn 2f ON. As a result, capacitor 31
The high voltage V _DDH charged to switch 32d, 32
By supplying it in the opposite direction to the terminal V _M through f, the erase voltage becomes -25V and the non-volatile memory 28
Delete a.

Note that the operating time of the timer 33 is the same as that of the booster circuit 30.
The operation time of the timer 34 is the time required for the high voltage V _DDH generated by the operation of the capacitor 31 to sufficiently charge the capacitor 31, and the operation time of the timer 34 is the time required for the high voltage V _DDH generated by the operation of the non-volatile memory. This is a suitable time for writing and erasing data 28a.

In this embodiment, a variable frequency division type configuration is shown as the frequency adjustment device, but the configuration is not limited to this. A switching capacitor may be provided in the oscillation circuit, and the capacitor may be connected according to information from the frequency setting circuit. A similar effect can be obtained in frequency adjustment using the so-called time-division oscillation method, in which switching is performed by
Furthermore, the setting information of the frequency setting circuit is not limited to only the speed and speed information provided by the external operation switch shown in the embodiment, but also applies to temperature conversion information that converts the signal from the temperature detection circuit into frequency adjustment information. be.

As described above, according to the present invention, the frequency setting section in the frequency adjustment device of an electronic watch can be easily rewritten.
- By providing a frequency setting circuit with a MOS configuration and a non-volatile memory circuit for temporarily storing setting information of this frequency setting circuit, setting values can be changed by external operating members etc. during normal watch operation. You can make changes as you like, and
Setting information can be temporarily stored in a non-volatile memory circuit only when the frequency setting circuit becomes inoperable, such as when replacing a battery, making it easy to rewrite the setting value and setting a frequency that does not cause information destruction. It has become possible to provide an electronic clock equipped with an adjustment device.

Furthermore, since the present invention is a system in which non-volatile memory is used as a short-term memory until battery replacement, the conditions for the non-volatile memory used include the noise margin and aging characteristics required for conventional non-volatile memory. Since it is possible to significantly loosen the voltage, a non-volatile memory with low write and erase voltages can be used, and the non-volatile memory and write power supply can be easily built into small devices.

Furthermore, by using the setting circuit and storage circuit based on the C-MOS configuration of the present invention, arbitrary information settings and information changes can be made, and when the operation is disabled such as when replacing the battery,
It is obvious that the technical idea of temporarily storing the setting information in a non-volatile memory to prevent information destruction can be applied to things other than the above-mentioned embodiments. It is effective for many kinds of information that should be prevented from being destroyed, such as musical note information of melodies that the bearer has independently memorized, as well as memo information such as the bearer's initial information and telephone number.

[Brief explanation of drawings]

Fig. 1 is a characteristic diagram of a general P-channel type non-volatile memory, Fig. 2 is a circuit diagram of a non-volatile memory circuit, Fig. 3 is a block diagram of an electronic clock according to the present invention, and Fig. 4 is a diagram of a non-volatile memory circuit. FIG. 2 is a block diagram showing a specific example of the nonvolatile memory circuit shown in the figure. 10... Clock circuit, 16... Frequency adjustment circuit,
18...Frequency setting circuit, 28...Nonvolatile memory circuit.

Claims (1)

[Claims] 1 Powered by a small battery, an external operating member for function control, an information setting circuit that allows information to be set from the outside, a non-volatile memory for storing setting information of the information setting circuit, and a non-volatile memory for storing setting information of the information setting circuit. A drive circuit for controlling the memory and a voltage detection circuit for detecting a voltage drop of the battery are provided, and when the battery voltage drops, the output signal of the voltage detection circuit is used as a write signal to write information in the information setting circuit to a non-volatile state. In a small electronic device that stores data in a memory, the drive circuit includes a boost circuit that boosts the voltage of the small battery to a high voltage that can control the nonvolatile memory, and a write voltage and an erase voltage that convert the high voltage to different polarities. and a drive mode storage means for controlling the operation of the booster circuit and the switching means, and the drive mode storage means operates the booster circuit and switches the booster circuit according to the output signal of the voltage detection circuit. A small electronic device, characterized in that it outputs a write voltage through a means, operates the booster circuit in response to an operation signal from the external operation member, and outputs an erase voltage through a switching means.