JPH0345073A - Original reader - Google Patents

Abstract

PURPOSE:To save number of transmission lines for timing signal by sending a timing signal in common except line shift signal deciding a storage time and sharing the signal with a timing signal processing circuit loaded on a carriage. CONSTITUTION:A timing signal generated from a timing signal generating section 27 and sent through a transmission line 28 consists of seven signals as a shift clock SH, drive clocks phi1, phi2, a clock pulse phiCLK, a reset pulse RS, and basic line shift clocks phiVo, phiV1E for deciding the storage time of a CCD11. In this case, the timing signal except the line shift clocks phiVo, phiV1E by groups deciding the storage time of a CCD 11 is sent in common and shared with each group. That is, the signals SH, phi1, phi2, phiCLK, RS, phiVo, phiV1E. inputted from a timing signal connector 32 are shared to each CCD 11 by a timing signal processing circuit 33 on a carriage 8. Thus, number of transmission lines 28 is saved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a document reading device such as a digital copying machine or a facsimile machine that uses a CCD-configured line image sensor as a reading element.

2. Description of the Related Art In general, in document reading devices, an image sensor and part of the processing section necessary for the image sensor are mounted on a carriage that moves to scan and read the document in the sub-scanning direction. In this case, a line image sensor of equal magnification is generally used as an image sensor.

According to such a same-magnification sensor, the configuration of the optical system can be simplified compared to the case of a normal small CCD that requires a large reduction optical system, and the entire device can be made smaller. , there are advantages such as less optical positional deviation.

FIG. 3 shows an example of an A3 size document reading device using such a same-magnification line image sensor 1. First, the contact glass and lath 3 on the top of the device main body 2.
Two fluorescent lamps 5 are provided as light sources for slit exposure of a document (not shown) placed thereon and pressed by a document pressure plate 4.

Reflected light from the original is imaged on the image sensor 1 through the SELFOC lens array 6 and photoelectrically converted. These image sensor l, fluorescent lamp 5 and lens array 6 are
It is mounted on a carriage 8 that is guided by a guide shaft 7 and scans in the sub-scanning direction. Here, the carriage 8 is driven by a drive wire 10 partially connected to the carriage 8 via a plurality of pulleys 9 using a drive motor (not shown) as a drive source.

In the case of such a same-size sensor, there is a limit to the reading length with only one chip CCD, so it is common to increase the reading length by mounting multiple chip CCDs on the same board and reading them separately. be. Furthermore, in order to continue reading by each CCD chip at the same pixel pitch in the main scanning direction, it is also common to arrange a plurality of CCD chips in two rows in a staggered manner, not on the same line, but slightly overlapping each other. FIG. 4 shows an example of a line image sensor 1 having such a two-row staggered arrangement structure (for example, a CCD linear image sensor TCD 1 manufactured by Toshiba Corporation).
16 DC). This is A
Five CCDs 11 are arranged in two rows in a staggered manner on the same substrate 12 for reading three short-side sizes. Each C
C:D11 is capable of reading 2928 pixels at a time as shown by S1 to 52928. Here, in the case of a staggered arrangement, the reading timing of the same line differs depending on the column position in the sub-scanning direction, and the two C, The CCD 11oD is divided into three CCDs: a CCD II, and an odd-numbered column group (rear row group) that scans backward.

FIG. 5 is a block diagram showing the electrical circuit configuration of each chip of such CGDII. First, 31-329
The photodiode cell 13 portion indicated by 28 is Do-D7.
It is provided linearly together with the dummy photodiode cell 14 portion indicated by 1 and connected to the barrier electrode 15 . Below this barrier electrode 15 , a storage electrode 16 , first to seventh line shift gates 17 to 23 , and a shift gate 24 are provided in this order, and are finally connected to a horizontal CCD register 25 . These gates 17 to 24 and register 25 serve as a shift register.

Such a CCD 11 generates line shift signals φV5 to φV9 for each line shift gate 17 to 23, shift pulse SH1 for the shift gate 24, and drive clocks φIA and φ2A for the horizontal CCD register 25, as well as a reset pulse R3 and the like.

It is driven by φ28 or the like. First, the image for l lines irradiated onto the light receiving surface of the photodiode cell 13 is converted into an amount of charge and passes through the barrier electrode 15, and then a pulse of the line shift signal φV1 is input to the first line shift gate 17. The data starts to be stored in the storage electrode 16 from the time when the data is stored, and is completed by the next pulse of the line shift signal φV. In other words, the optical signal accumulation time that determines the amount of light received by one CGDII is determined by the first line shift signal φ as shown in FIG.
V, depends on the output interval. At the same time as the accumulation is completed, the charges accumulated in the accumulation electrode 16 up to now are shifted to the first line shift gate 17, and the accumulation electrode 16 starts accumulating charges for the next line. The signal shifted to the first line shift gate 17 is transferred to the second line shift gate 17 by the next line shift signal φV.
The signal is shifted to the line shift gate 18. A similar shift operation is performed for the following line shift gates i9 to i23, and the line shift gates i9 to i23 are shifted to the seventh line shift gate 23. Then, the signal of the seventh line shift gate 23 passes through the shift gate 24 by the shift pulse SH, and then is shifted to the horizontal CCD register 25, and the drive clock φI
A, φ2A, and φ2B are sequentially output as an image signal O8 (CCD drive).

Here, looking at an example of the timing of outputting the image signal O8, for example, as shown in FIG.
The original V is after the dummy signal (72 pixels) consisting of 48 pixels (48 pixels) and 12 pixels (D60 to D71). IVBIVR color effective pixel signal (2928
The reading range is (pixels). Therefore, one line output period consists of 3000 pixels.

In order for the image sensor l to read the document in this way, a certain predetermined timing signal is required for each C and C in addition to the power supply.
The image signal O8 must be input to the GDII, and the read image signal O8 must undergo processing such as analog-to-digital conversion. At this time, as shown in FIG. 3, the image sensor l is mounted on the carriage 8,
It moves along with the sub-scanning operation, and the power supply section 26 and timing signal generation section 27 side of the apparatus main body 2 and the carriage 8 side are made of flexible materials that can follow the movement of the carriage 8, as shown in FIG. It is necessary to electrically connect by a transmission line 28 having a length.

Here, the transmission line 28 consists of a power supply line, various timing signal lines, image signal output lines, etc., but if these lines are arranged separately, the lines may become tangled or twisted when the carriage 8 runs. This is not preferable because it impedes the smooth running of the carriage 8 and also causes failures such as wire breakage and short circuits.

For this reason, a ribbon-shaped structure in which a plurality of transmission lines 28 are grouped together was proposed in Japanese Patent Application Laid-Open No. 62-86611, and has actually been commercialized. Here, in the ribbon-shaped transmission line 28, the power supply line must be thick to some extent, and the timing signal line and the image signal output line are preferably coaxial lines. For this reason, as the number of wires increases, the bending force increases, although not so much on each wire side, and the load on the carriage 8 and its drive motor increases. Further, even if a plurality of transmission lines 28 are formed into a ribbon shape, a decrease in reliability of the moving parts cannot be avoided, and the greater the number, the higher the probability that problems due to twisting or entanglement will occur. Moreover, a large number of parts is disadvantageous in terms of cost. In particular, coaxial lines are expensive. Therefore, it is preferable that the number of transmission lines 28 connecting the apparatus main body 2 side and the carriage 8 side be as small as possible.

Problem to be Solved by the Invention However, when we look at the actual circuit configuration in which the ribbon-shaped transmission line system as described above is implemented, the configuration is as shown in FIG. It is. That is,
FIG. 8 shows a part of the drive circuit etc. for the line image sensor 1. Even considering only the timing signal lines, they are all generated on the timing signal generation section 27 side of the device main body 2 and transmitted individually. Therefore, 22 transmission lines are required for the timing signal connector 29.

This point will be explained in more detail. The five CGDIIs that make up the line image sensor 1 are, as described above, the even-numbered column group CGDII which is scanned in advance, and the odd-numbered column group CGDII which is scanned later. Consists of 0.

In this way, even in two groups with different scanning timings, the timing signal generation unit 27 generates line shift signals φV, , V to φV v for the even column groups so that the image signal outputs are simultaneous for the same line. E V, shift pulse SHgv, drive clock φ111V, φ2E
V and reset pulse RSEV are generated and transmitted, and line shift signal φV + OD~φV for odd column groups is generated and transmitted.
*Q D s shift pulse 5HoI), drive clocks φ10D, φ2oD, and reset pulse R3oo are generated and transmitted.

This requires a total of 22 transmission lines 28. After passing through the timing signal connector 29, the matrix wiring circuit 30. Each CGD via the drive circuit 31
II.

Therefore, according to the conventional method, although measures such as making the transmission line 28 ribbon-like have been taken, there are a large number of transmission lines 28,
Countermeasures against transmission line troubles are insufficient.

Means for Solving the Problem A plurality of CCDs each having a light source that exposes the surface of the document and a shift register that is driven by a drive clock and outputs an output are arranged in two rows in a staggered manner in the main scanning direction to detect the light reflected from the surface of the document. A line image sensor that receives light and converts it photoelectrically is mounted on a carriage that moves in the sub-scanning direction with respect to the document surface, and the carriage side and the apparatus main body side equipped with a timing signal generation section are connected to a plurality of In a document reading device electrically connected by a transmission line, each C of the first matrix group in the sub-scanning direction in the line image sensor is connected by the transmission line.
A timing signal processing circuit is provided on the carriage for commonly transmitting timing signals for the CD and each CCD in the sub-scanning direction rear matrix group, except for a line shift signal for each group that determines the storage time of the CCD, and for distributing them to each group. It was established in

Furthermore, the timing signal processing circuit receives timing signals transmitted through the transmission line by the Glock pulse and group-specific line shift signals that determine the storage time of the CCDs, and shifts these timing signals to shift the timing signals of the two groups of CCDs. The configuration includes a shift signal generation section that generates the remaining line shift signals for the shift register.

When considering the operation of a plurality of CCDs configured in a staggered arrangement, the CCDs belonging to the front matrix group in the sub-scanning direction and the CCDs belonging to the rear matrix group in the sub-scanning direction use a line shift signal that determines the accumulation time for each group. As long as the timing signals can be secured separately, there is no problem even if the other timing signals are common. In other words, it is possible to reduce the number of transmission lines for timing signals. Therefore, there is no need to separately prepare transmission lines for two groups for timing signal transmission, and the timing signals are commonly transmitted except for the line shift signal that determines the accumulation time, and the tying signal mounted on the carriage is used. All you have to do is distribute it in the processing circuit,
The number of transmission lines for timing signals can be halved. Therefore, the occurrence of twists and entanglements in the transmission line is reduced, and the carriage travels smoothly, reducing its burden. Moreover, cost reduction is also possible.

Furthermore, regarding the timing signals, which are multiple line shift signals required for driving the CD shift register,
They have a predetermined shift timing relationship with each other, and can be easily generated without transmitting them individually through transmission lines. Therefore, by having a shift signal generation section in the timing signal processing circuit mounted on the carriage, it is possible to transmit only the line shift signal for each group, which determines the basic CCD accumulation time, along with the clock pulse, through the transmission line. , can generate the remaining necessary line shift signals. Therefore, the number of transmission lines can be further reduced.

Embodiment An embodiment of the present invention will be explained based on FIGS. 1 and 2. Components that are the same as those shown in FIGS. 3 to 8 are indicated using the same reference numerals. In this embodiment, the number of timing signal transmission lines in the transmission line 28 is significantly reduced from the conventional 22 to 7.

First, the timing signals generated by the timing signal generator 27 and transmitted through the transmission line 28 are the shift clock SH1 drive clock φ1. φ2, clock pulse φC
LK s Basic line shift clock φV□ for determining the accumulation time of reset pulse R3 and CGDII
, φV, and FL (shown in negative logic in the upper part of FIG. 1). Correspondingly, the timing signal connector 32 that receives the signal transmitted through the transmission line 28 has seven terminals. This timing signal connector 3
These seven signals input from CCD II are distributed to each CCDII by a timing signal processing circuit 33.

This timing signal processing circuit 33 generates φ2^ and φ2B from the drive clock φ2 and converts seven signals into eight signals, and a conversion processing circuit 34 having an IC configuration, and matrix wiring that distributes each signal to each CGDII. A circuit 35;
Two shift circuits are provided between the conversion processing circuit 34 and the matrix wiring circuit 35, and generate line shift signals φV1 to φV for each group by shift processing based on the line shift signals φVo, φV, and E on the clock pulse φCL. Shift signal generation unit 38 using registers 36 and 37
It becomes more.

Such a configuration is based on the following idea. First, a CCD with a staggered arrangement structure as shown in Figure 4.
Considering the operation of 1l, shift clock SH1 drive clock φl, φ
2 is common, that is, it can be used commonly for all CGDIIs without any problem.

Furthermore, for the seven line shift signals φV, ~φV, if the basic line shift signals for determining the accumulation time for each group are separate, the line shift signals φV, ~
φV can be used in common without any problem.

In other words, there is no problem even if most of the timing signals are shared between the even-numbered column groups and the odd-numbered column groups, and even if only the sharing of the two groups is considered, basically the transmission line 28 can be It is possible to reduce the number by almost half compared to 22 (12
Book).

Furthermore, considering the line shift signal, as described above, it is sufficient if the signals determining the accumulation time of each CGDII are separate for each group. Here, the line shift signal φv16 is used to determine the accumulation time for the CCD II EV of the even column group. As shown in FIG. 2, the phase changes depending on the magnification ratio, and the timing signal generating section 27 selects one of them depending on the magnification ratio. Other line shift signals, that is, line shift signals φV, ~φV for odd-numbered column groups, and line shift signals φv3-φV7 for even-numbered column groups shift the basic line shift signal φV, which is generated at a predetermined timing. It is not necessary to transmit all of them individually using the transmission line 28, and there is no problem in generating them by processing in the timing signal processing circuit 33 on the carriage 8.

Specifically, the signals φCLK, φV, B and φ
V.

Shift processing can be generated using shift registers 36 and 37. In the example shown in FIG. 2, the line shift signal φV, 1! The line shift signal φV, H
The line shift signal φ■ is generated at a predetermined timing, which is the falling edge of the first clock φl after the output of the line shift signal φV1 and is slightly earlier in phase than the first line shift signal φV1.
, are sequentially shifted at the timing of the clock pulse φCLK, line shift signals φV1 to φV for even column and odd column groups can be generated as shown in FIG. Therefore, the number of transmission lines 28 was not only reduced by half from the conventional 22 lines, but also significantly reduced to 7 lines.

Note that in this embodiment, no particular consideration was given to the power supply line in the transmission line 28, but for example, a +12V regulator I
C is mounted on the carriage 8, and this regulator IC
By generating +5V in addition to +12V and supplying power to the necessary locations, the number of power supply lines can also be reduced.

Effects of the Invention The present invention focuses on the staggered arrangement of a plurality of CCDs and the characteristics of the timing signals, and as described above, the timing signals are commonly transmitted except for the line shift signal that determines the accumulation time, and the CCDs are mounted on a carriage. Since the timing signal processing circuit distributes the signals, the number of transmission lines for timing signals can be halved, which reduces twisting and tangling of the transmission lines, and reduces the load on the carriage. Even if the transmission line for the timing signal is composed of coaxial lines, the cost can be reduced because the number of transmission lines is small, and it is also advantageous for a ribbon-like temporary structure. Furthermore, if we focus on the characteristics of the timing signal, which is the multiple line shift signals required for driving the CCD shift register, by having a shift signal generation section in the timing signal processing circuit mounted on the carriage,
By transmitting only the group-specific line shift signals that determine the basic CCD storage time together with the clock pulses over transmission lines, the remaining necessary line shift signals can be generated, thus reducing the number of transmission lines required. can be made even smaller and the above effects can be increased.

[Brief explanation of drawings]

Figures 1 and 2 show an embodiment of the present invention. Figure 1 is a schematic block diagram, Figure 2 is a timing chart of each signal indicating CCD drive, and Figure 3 is a typical document reading system. Schematic configuration diagram showing an example of the device, No. 48! I is a schematic plan view showing an example of the configuration of a line image sensor, FIG. 5 is a block diagram of a CCD, FIG. 6 is a timing chart of each signal showing CCD drive, FIG. 7 is a timing chart showing image signal output, and FIG. FIG. 8 is a schematic block diagram showing a conventional example. 1...Line image sensor, 2...Device main body, 5
... light source, 8 ... carriage, 11 ... CCD,
27... Timing signal generation section, 28... Transmission line,
33... Timing signal processing circuit, 38... Shift signal generation section, SH, φ1. φ2. R3...Timing signal, φCLK...Clock pulse (timing f word), φVO, φV4...Line shift signal (timing signal), φv1~φV,...Line shift signal Applicant Rico Co., Ltd.

Claims (1)

[Claims] 1. A plurality of CCs each having a light source that exposes the document surface and a shift register that is driven by a drive clock and outputs output.
A line image sensor D arranged in two rows in a staggered manner in the main scanning direction and receiving reflected light from the document surface and photoelectrically converting the received light is mounted on a carriage that moves in the sub-scanning direction with respect to the document surface. In a document reading device in which the carriage side and the device main body side including a timing signal generating section are electrically connected by a plurality of transmission lines, each of the sub-scanning direction leading matrix groups in the line image sensor is connected by the transmission lines. A timing signal processing circuit is provided on the carriage for transmitting timing signals for the CCD and each CCD in the sub-scanning direction rear matrix group in common and distributing them to each group, except for a line shift signal for each group that determines the accumulation time of the CCD. A document reading device characterized in that it is provided in. 2. The timing signal processing circuit uses clock pulses and CC
The line shift signals for each group that determine the accumulation time of D are transmitted through the transmission line, and the remaining line shift signals for the shift registers of the two groups of CCDs are generated by shifting these timing signals. The document reading device according to claim 1, further comprising a shift signal generating section.