JPH0548841A - Ccd line sensor - Google Patents

Abstract

PURPOSE:To increase the read speed, to suppress the occurrence of fixed pattern noise, and to realize the easiness of design or the like by increasing the degree of parallelism without restrictions due to the element constitution in an output buffer and uniformizing the distance between a photo diode array (PD array) and CCD analog shift registers (CCD-SR) with respect to the CCD line sensor which transfers and outputs the signal charge in parallel. CONSTITUTION:A PD array 1 is divided in the scanning direction, and shift gates 2-i (i=1 to 4), CCD-SRs 3-i, and output buffers 4-i provided correspondingly to respective divided sections (1) to (4) are arranged on opposite sides of the PD array 1 in adjacent divided sections to secure a sufficient space for output buffers 4-i, and the degree of parallelism is increased without hindrance on the element constitution, and the signal charge of the PD array 1 is transferred and outputted at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD line sensor for photoelectrically converting image information one-dimensionally and reading the same, which is a high density and highly integrated photodiode array (PD array).
The present invention relates to an element configuration capable of reading the signal charges of the above at high speed.

[0002]

2. Description of the Related Art A CCD line sensor is a solid-state image pickup device that converts one-dimensional image information into an analog electric signal by a PD array and outputs the signal as a time-series electric signal by a CCD. It is widely used for image input of OA equipment such as devices, digital copiers and image scanners, and sensors for AF cameras such as distance measuring sensors and consumer equipment such as bar code readers. In a G3 standard facsimile machine, which is currently a typical application, a CCD line sensor with a pixel number of 1728 or 2048 is used, and an A4 or B4 size document is printed at about 200 DPI (d
The main scanning line density is ot per inch).

However, a G4 standard facsimile machine using ISDN is required to have a linear density of 400 DPI, and a higher resolution digital copying machine has a higher density of 600 to 800.
In many cases, the linear density of DPI is required, and high density and high integration of CCD line sensors are becoming an increasingly important issue.
Along with this, how to transfer and output signals read from the PD array at high speed has become a problem.

Conventionally, the following structure has been adopted as a method for enabling high-speed reading in a CCD line sensor. First, as shown in FIG. 2, shift gates 52 and 53 and CCD analog shift registers (CCD-SR) 54 and 55 are provided on both sides of a linear PD array 51, respectively, and stored in odd-numbered PDs. The signal charge is transferred to the CCD-SR54 through one shift gate 52, and the transfer clock φ11 of the CCD-SR54,
While sequentially transferring by φ21, it is output to the output terminal OS1 via the output buffer 57, and the signal charge accumulated in the even-numbered PD is transferred to the CCD-SR55 via the other shift gate 53 and transferred to the CCD-SR55. There is a parallel transfer method in which data is output to the output terminal OS2 via the output buffer 57 while being sequentially transferred by the clocks φ12 and φ22. Now, assuming that the PD array 51 has a number of 5000 pixels and the signal is read using a shift gate and CCD-SR of a single configuration, assuming that the upper limit transfer frequency of the CCD-SR is 10 MHz, it takes 1 scan time. Becomes 500 μsec. However, according to the method shown in FIG. 2, the signal charges are transferred by the two CCD-SRs 54 and 55, so that the half
The scanning time (250 μsec) is sufficient. That is, it becomes possible to read at such high speed, and it becomes effective when the number of pixels of the PD array 51 becomes large. Since the signal processing unit connected to the output terminal OS2 can execute signal processing at a speed much higher than the reading speed of the CCD line sensor, a bottleneck does not occur due to the speeding up of the reading speed.

As another method, as shown in FIG. 3, a PD array 61 (the number of pixels: 2 m) is provided with a single shift gate 62 and two CCD-SRs 63, 64 on one side, and a PD array is provided. 61 of 1 ~ m
The signal charges stored in the 1st to mth PDs and the m + 1 to 2mth PDs are transferred to the two CCD-SRs 63 and 64 via the shift gates 62, respectively, and transferred from the 1st to mth PDs. Signal charge is
Transferred sequentially by transfer clock φ11 and φ21 of CCD-SR63 and output to output terminal OS1 via output buffer 65, m + 1
The signal charge transferred from the ~ 2mth PD is sequentially transferred by the transfer clocks φ12, φ22 of the CCD-SR64 and output buffer 6
There is a parallel transfer method that outputs to the output terminal OS2 via 6. This method is different from the above method in how to extract the signal charges from the PD array 61, but is similar to the above method in that the parallel transfer is performed, and the signal reading speed can be doubled. Further, in this method, the number of divisions can be set to two or more, and in principle, the reading speed can be increased by a reciprocal multiple of the number of divisions.

Furthermore, a system in which the above two systems are combined can also be adopted. That is, this is a method in which the PD array is divided into a plurality of sections, the odd-numbered and even-numbered signal charges in each section are distributed to CCD-SRs on both sides, and each CCD-SR sequentially transfers and outputs them.

[0007]

By the way, by adopting the above-mentioned parallel transfer system, the reading speed of the signal charges of the CCD line sensor can be increased, but the following problems are involved in each system. There is a point. First,
According to the method of FIG. 2, since the signals of the PD array 51 are divided into two types of odd-numbered and even-numbered and are transferred in parallel in two, the read speed is as compared with the case of transferring with one CCD-SR. In comparison, the speedup of 2 times is the limit.

In the system of FIG. 3, there is no limit in principle as in the above system, but both CCD-SRs 63 and 64 are PD array 61.
Output buffer 66 because it is aligned on one side with respect to
It becomes difficult to secure a space for incorporating the.
That is, the general structure of the output buffer applied to the CCD line sensor is shown in FIG. 4 (corresponding to the output buffer 66 of FIG. 3) and FIG. 5 (equivalent circuit diagram).
(FD) 71, reset gate unit 72, and reset voltage application unit 73
It is composed of an output control circuit 74 composed of and an amplifier circuit 75 composed of four FETs, and it is possible to secure a space for composing these circuit elements between the CCD-SR 63 and 64. This is difficult, and normally the above-mentioned space is secured by making the pitch of the CCD register of the CCD-SR 63, 64 smaller than the pitch of the PD of the PD array 61.

Therefore, if the PD pitch of the PD array 61 is further reduced in order to improve the image reading resolution, the device configuration space of the output buffer 66 becomes proportionally smaller, and the device manufacturing becomes difficult, and at the same time, There is a problem in signal amplification and transfer efficiency. Further, as is apparent from FIG. 3, since the PD array 61 and the CCD-SR 63, 64 have different lengths, the distance from each PD to the corresponding CCD register is also different, and the signal transfer speed via the shift gate 62 is different. Variations may occur and fixed pattern noise may appear in the image information. Further, for the same reason, there is also a disadvantage that the design procedure of the element / wiring becomes complicated and the design work becomes extremely complicated when the pitch or the number of pixels is changed. In addition, even in the method in which the two methods are combined, since the method in FIG. 3 is inherent, the same problem as described above occurs.

Therefore, according to the present invention, by devising the arrangement of the shift gate and CCD-SR for the PD array, a sufficient device configuration space for the output buffer can be secured even if the PD array is highly integrated and highly integrated. It was created for the purpose of providing a CCD line sensor which can be read at high speed by parallel transfer of signal charges.

[0011]

DISCLOSURE OF THE INVENTION The present invention is directed to a PD array in which PDs are aligned, a shift gate provided in the PD array, and a CCD gate provided in the shift gate. In the CCD line sensor in which the CCD-SR connected to each PD of the PD array and the output buffer provided in the output section of the CCD-SR are configured on the substrate, a section in the scanning direction of the PD array And the shift gate and CCD-SR provided corresponding to each divided section.
And the output buffer are arranged so as to be located on the opposite side to the PD array between the adjacent divided sections, according to a CCD line sensor.

[0012]

According to the present invention, the PD in each divided section of the PD array is
The signal charges generated in step S1 are read out by the shift gate and CCD-SR corresponding to the divided section. That is, the signal charge is transferred to the CCD-SR via the shift gate for each divided section, and sequentially output by the transfer clock input to the CCD-SR while being output via the output buffer. High-speed reading by the parallel transfer method becomes possible as in the prior art.

According to the present invention, in addition to the above-mentioned parallel transfer method, the shift gate corresponding to each divided section, the CCD-SR, and the output buffer are arranged on the opposite side of the PD array due to the relationship between the adjacent divided sections. I am letting you. Therefore, before and after the CCD-SR corresponding to each divided section, it always corresponds to the adjacent divided section.
An interval corresponding to the length of the CCD-SR in the scanning direction will be configured. As a result, sufficient space is secured in the output section of the PD array to configure the output buffer, and even if a transfer method that increases the number of divided sections and increases the parallelism is adopted, the limit is leapt. Can be improved. That is, in principle, the length in the scanning direction required for the element configuration of the output buffer can be used as the unit of the division section, and the parallelism can be increased within the range of the condition.

Further, according to the present invention, since the length of each division section of the PD array and the length of the shift gate and CCD-SR corresponding to the division section can be made the same,
The PD pitch and the CCD register pitch in the CCD-SR can be made the same, and inevitably the wiring length and the wiring pattern between each PD and the CCD register can be made uniform.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In this embodiment, the case where the PD array is divided into four sections is taken as an example. Fig. 1 is an overall configuration diagram of a CCD line sensor. 1 is a PD array, 2-1, 2-2, 2-3, 2-4 are shift gates, 3-1, 3-2, 3-3. , 3-4 are CCD-SR, 4-1,4-2,4-3,4
-4 indicates an output buffer, each of which is a single board
Composed on top of 10. Here, the PD array 1 corresponds to the number of pixels of 4n, and 4n PDs are aligned in the scanning direction, but regarding the output of the signal charge, each of the 4 sections is composed of n PD elements. It is divided into (to sections), and shift gates 2-1 and C for the divided sections.
The CD-SR3-1 and the output buffer 4-1 are the shift gate 2-2 for the divided section, the CCD-SR3-2 and the output buffer 4-2 are the shift gate 2-3 for the divided section. CCD-SR3-3 and output buffer 4-3 are shift gates 2-4 for divided sections
, CCD-SR3-4 and output buffer 4-4 are installed in association with each other.

As is apparent from the figure, the shift gates, CCD-SRs, and output buffers corresponding to the respective divided sections are located on the opposite side of the PD array between the adjacent divided sections. It is arranged. That is, the shift gate, the CCD-SR, and the output buffer are arranged below the PD array 1 for odd-numbered divided sections and above the PD array 1 for even-numbered divided sections.

Due to the above-mentioned arrangement, the lengths in the scanning direction of the respective divided sections of the PD array 1 to the shift gate 2-i, CCD-SR3-
i (i = 1 to 4) have the same scanning direction length,
When the output buffers 4-2, 4-3, and 4-4 corresponding to are configured on the front divided section ~ side, the divided section ~
Since no element is configured on the side, the output buffer 4-
The space for constructing 2,4-3,4-4 can be secured with a sufficient margin. Therefore, shift gate 2-i and CCD-SR3-i
It is not necessary to secure the configuration space of the output buffers 4-2, 4-3, 4-4 by configuring the PD array 1 to be shorter than the scanning direction length of each divided section to the output buffers as in the configuration of FIG. Four-
It is not necessary to make 2,4-3,4-4 smaller than necessary. As a result, it is possible to design a circuit that does not hinder the amplification of signals and transfer efficiency, and within the range, the device configuration of the entire CCD line sensor can be highly integrated and highly integrated.

Next, the operation of this CCD line sensor will be described. First, the reflected light from the original is one-dimensionally PD array 1
When the image is formed on the PD array 1, each PD (1 to 4n) of the PD array 1 accumulates the signal charge photoelectrically converted according to the light amount distribution of the image forming light, but the level of the shift gate control signal SH is changed. OFF
→ ON → OFF is switched to open each shift gate 2-1, 2-2, 2-3, 2-4 for a moment, and the signal charge of each PD (1 to 4n) is CCD-SR3-
Transfer to 1,3-2,3-3,3-4. In this example, PD array 1
Shift gates 2-1, 2-2, corresponding to
Since 2-3,2-4 and CCD-SR3-1,3-2,3-3,3-4 are provided, the signal charge of PD (1 to n) in the divided section is CCD-SR3-1. What,
The signal charge of PD (n + 1 to 2n) in the division section is to CCD-SR3-2, the signal charge of PD (2n + 1 to 3n) in the division section is to CCD-SR3-3, and the PD (3n of division section is The signal charge of (+1 to 4n) is transferred to the CCD-SR3-4.

The reset gate terminals φ1B, φ2B, φ
Set the reset voltage terminals RS1, RS2, RS3, and RS4 of 3B, φ4B and output buffers 4-1, 4-2, 4-3, and 4-4 to the set state, and set each CCD-SR3-1, 3
-Transfer clock φ11 input to -2,3-3,3-4
φ21 / φ12, φ22 / φ13, φ23 / φ14, φ24 each CCD
-Sequentially transfer the signal charges transferred to SR3-1, 3-2, 3-3, 3-4 to each output buffer 4-1, 4-2, 4-3, 4-4 side. Output buffer 4-
In 1,4-2,4-3,4-4, a voltage that changes in time series is output based on the transferred signal charge, and is output to each output terminal OS1, OS2, OS3, OS4. Output terminal OS1, O above
Output from S2, OS3, OS4 is an image processing system (not shown)
However, in this embodiment, it is 4
Since the parallel transfer method is adopted, in the image processing system, the input signals from the output terminals OS1, OS2, OS3 and OS4 are combined and processed so as to be a signal for one scan.

Thereafter, with the relative movement of the CCD line sensor and the read document in the sub-scanning direction, the CCD line sensor repeats the above-described operation procedure, and the one-dimensional image information of the document is sequentially sent to the image processing system side. Although transferred, the image processing system side assembles a two-dimensional image by sequentially arranging the one-dimensional image information in the sub-scanning direction. The CCD line sensor of this embodiment transfers four read signals in parallel, so one CCD-SR
It is possible to realize a read speed four times that of the case where data is transferred in the same way, and it is also possible to read at a speed twice as high as the read speed based on the configuration of the CCD line sensor shown in FIGS. 2 and 3. become.

By the way, based on the design concept of this CCD line sensor, in principle, it is possible to further increase the number of division sections of the PD array 1 within a range in which the element configuration space of the output buffer can be secured. The read speed can be increased in proportion to the reciprocal of the number of divided sections, and the read speed can be dramatically improved without lowering the transfer function or the amplifier function.

Further, in this embodiment, each CCD-SR3-1, 3-2, 3-3,
Output buffers 4-1, 4-2, 4-3, 4-4 are arranged in the same direction with respect to 3-4, but the arranging direction is arbitrary, and the division section ~ is further divided. It is also possible to provide output buffers on both sides. Further, in the present embodiment, the section lengths of the divided sections are made equal so as to be composed of the same number of PDs, but they may be made non-uniform in some cases, and the number of pixels of one scanning line and the image processing system may be set. It suffices to set each divided section length in consideration of the specifications on the side.

[0023]

EFFECTS OF THE INVENTION The present invention having the above-mentioned structure has the following effects. Since the shift gate corresponding to each division section of the PD array, the CCD-SR, and the output buffer are arranged on the opposite side of the PD array in relation to the adjacent division sections, the element configuration space of the output buffer is reduced. It is possible to increase the number of division sections while securing enough,
A transfer method with a higher degree of parallelism is realized to dramatically improve the read speed. In addition, the PD array
It is no longer necessary to make the CCD register pitch of the CCD-SR smaller than the PD pitch, eliminating difficulties in design and manufacturing, and realizing a CCD line sensor that does not reduce the transfer signal amount or transfer efficiency. In addition, each PD in the PD array to each CCD-SR
Since the wiring distance to the CCD register can be made uniform, the initial design is easy, and it is also possible to easily cope with design changes due to changes in pitch or the number of pixels. Further, for the same reason, it is possible to eliminate fixed pattern noise due to variations in the transfer time of signal charges.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a CCD line sensor according to an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a CCD line sensor in a conventional technique.

FIG. 3 is an overall configuration diagram of a CCD line sensor in the related art.

FIG. 4 is a diagram showing a device configuration of an output buffer.

FIG. 5 is an equivalent circuit diagram of an output buffer.

[Explanation of symbols]

1 ... PD array, 2-1,2-2,2-3,2-4 ... shift gate, 3-1,3-
2,3-3,3-4 ... CCD-SR, 4-1,4-2,4-3,4-4 ... Output buffer,
10 ... Substrate ..., Divided section of PD array.

Claims (1)

[Claims] 1. A photodiode array in which photodiodes are aligned, a shift gate provided in the photodiode array, and a CCD gate provided in the shift gate, and each CCD register is provided through the shift gate. In a CCD line sensor in which a CCD analog shift register connected to each photodiode of the array and an output buffer provided at the output part of the CCD analog shift register are formed on a substrate, a section in the scanning direction of the photodiode array And a shift gate, a CCD analog shift register, and an output buffer provided corresponding to each divided section are arranged so as to be located on the opposite side to the photodiode array between adjacent divided sections. A CCD line sensor characterized in that