JPH0344965A - Semiconductor memory device and manufacture - Google Patents

Abstract

PURPOSE:To facilitate the processes and to improve reliability by digging up the substrate of a memory cell array forming region compared with its peripheral circuit forming region in order to neutralize the difference in level between the memory cell array and the peripheral circuit. CONSTITUTION:A resist pattern 2 is formed on a silicon substrate 1 and then the substrate 1 is subjected to isotropic etching using the resist 2 as a mask to form a recessed part substrate 3. Next; the resist 2 and a surface of the substrate 1 are removed and field oxide films 5 and 6 for isolating elements are formed on a substrate 4 except the recessed part of the substrate 1. Furthermore, transistors 7, bit lines 8, memory nodes 9, capacitor dielectrics 10, and plate electrodes 11 are formed in order, after which an aluminum wiring 12 is formed through an insulating film. At this time, the unevenness in level of the boundary part between a memory cell array part 13 and the peripheral part 14 is diminished by a digging process so that the aluminum wiring 12 can be formed easily, resulting in the improvement in reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device and its manufacturing method.The present invention relates to a semiconductor memory device and its manufacturing method. ) has also been devised in various ways to increase the degree of integration.Among them, the so-called stacked memory cell, which stacks the capacitive part for charge storage on a silicon substrate, is easy to manufacture and has soft error resistance. It is considered to be a promising candidate due to its height.

Various structures have been proposed.In order to obtain sufficient capacity, it is necessary to stack the capacitive parts high.In other words, to obtain large capacity, the side walls of storage nodes stacked high should also be used as capacitive parts. A cross-sectional view of an example is shown in FIG. 5 indicates the first field oxidation wL; 8 indicates the bit line. In order to obtain a large capacitance on switching transistor 7, storage node 9 is formed high, and cell plate 11 is formed via dielectric film IO. With such a structure, the difference in level at the boundary portion 15 between the memory cell array portion 13 and the peripheral circuit portion 14 becomes considerably large. Such a large step may cause problems such as pattern breakage during the photolithography process and dry etching process during the formation of the aluminum wiring 12. Figure 7 shows the formation state of the aluminum wiring 12 when viewed from above in Figure 6. Shown schematically. As shown in FIG. 7, at the boundary 15 between the memory cell array section 13 and the peripheral circuit section 14, the aluminum wiring 12 is locally thinned due to the step, and in severe cases, the aluminum wiring 12 may become completely disconnected. When patterning the photoresist that serves as an etching mask, the pattern becomes thinner due to effects such as light reflection due to the large step difference.The problem that the invention aims to solve is the use of stacked cells in this way. In DRAM, a large step is formed at the boundary between the memory cell array and the peripheral circuitry, and in order to obtain a large capacity, it is necessary to form an even larger step. Patterning becomes difficult, resulting in lower wiring yield and reliability.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, which facilitates the wiring formation process and improves the reliability of the wiring even when the capacitance portion becomes high. do.

Means for Solving the Problems The present invention provides a semiconductor memory device including a memory cell array formed in a recessed region of a silicon substrate and a peripheral circuit formed on a substrate other than the recessed portion, and a method for manufacturing the same. According to the present invention, by forming a memory cell array on a concave substrate formed in a silicon substrate, the storage nodes are formed high in order to obtain a large capacity. Embodiment (Example 1) FIG. 1 shows the first embodiment of the present invention. As shown in FIG. 1(a), a resist pattern 2 is formed on a silicon substrate l by a photolithography process. Next, as shown in FIG. 1(b), Using the resist 2 as a mask, place the silicon substrate 1 on a CF
After removing the resist 2 and etching the substrate surface with a mixed aqueous solution of ammonia and hydrogen peroxide, the recessed substrate 3 was formed by isotropic etching using a mixed gas plasma of 4 and 02. As shown in FIG. 1d), field oxide films 5 and 6 for element isolation are formed on the concave substrate 3 and on the substrate 4 other than the concave portion, respectively, and a switching transistor 7 is formed by a conventional method. As shown in FIG. 1(e), the bit line 8 and the storage node 9 are formed one after another, and then the aluminum wiring 12 is formed through the resistive insulating film on which the capacitive dielectric film 10 and plate electrode 11 are formed, as shown in FIG. 1(f). form. In this case, the level difference in the boundary part 15 between the memory cell array part 13 and the peripheral circuit part 14 can be kept small, and aluminum wiring can be easily formed.A top view at this time is schematically shown in FIG. 2.

In the boundary portion 15 between the memory cell array portion 13 and the peripheral circuit portion 14, the L aluminum wiring 12 is formed neatly without thinning.In this embodiment, the etching of the silicon substrate 1 is performed using isotropic etching. It is also possible to use anisotropic etching or a combination of isotropic etching and anisotropic etching (Example 2). Fig. 3(a) is a cross-sectional view of the process.
As shown in FIG. 1, a silicon oxide film 16 and a silicon nitride film 17 are formed on a silicon substrate 1, and a resist pattern 2 is formed thereon by a photolithography process. Next, as shown in FIG. 3(b), the silicon nitride film 1 is coated using the resist pattern 2 as a mask.
Etch 7. After removing the resist pattern 2, the silicon substrate 1 is oxidized using the silicon nitride film 17 as a mask to form a second silicon oxide film 18, as shown in FIG. 3(c). Thereafter, as shown in FIG. 3(d), the silicon nitride film 17, the silicon oxide film 16, and the second silicon oxide film 18 are removed to form the concave substrate 3 and the substrate 4 other than the concave portions. Thereafter, a memory cell array and peripheral circuits are formed according to the first embodiment described above to form a semiconductor memory device. According to this embodiment, the stepped portion 21 between the concave substrate 3 and the substrate 4 other than the concave portion is formed smoothly, which not only facilitates patterning in the photolithography process when forming the switching transistor 7, but also facilitates patterning for subsequent gate electrode formation. Even when polysilicon is etched, it is easily etched without any remaining polysilicon. Further, the depth and angle of this stepped portion 2 can be arbitrarily selected by the combination of the film thicknesses of the silicon oxide film 16 and the silicon nitride film 17, and the oxidation time. Although it is possible to form the node sufficiently high and obtain a large capacity, it is possible to reduce the height difference between the memory cell array part and the peripheral circuit part, making it possible to form high-yield and highly reliable aluminum wiring. can.

(Embodiment 3) FIG. 4 is a process cross-sectional view of a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention. As shown in FIG. After forming the pattern 2, as shown in FIG. 4(b), the silicon substrate 1 is coated with, for example, C.
A shallow concave substrate 19 is formed by isotropic etching using a mixed gas plasma of F4 and 02. After that, the second resist pattern 2 is applied again as shown in FIG. 4(C).
0 is formed, and the silicon substrate 1 is further subjected to isotropic etching using the second resist pattern 20 as a mask to form a recessed substrate 3 (FIG. 4(d)). Thereafter, as shown in FIG. 4(e), the second resist pattern 20 is removed and the surface of the substrate is etched with a mixed aqueous solution of ammonia and hydrogen peroxide to form the concave substrate 3 and the substrate 4 other than the concave portions. Thereafter, a memory cell array and a peripheral circuit are formed according to the first embodiment described above to form a semiconductor memory device.According to this embodiment, the stepped portion 21 between the concave substrate 3 and the substrate 4 other than the concave portion is small. Even if the height difference between the recessed substrate 3 and the substrate 4 other than the recessed portion becomes large, patterning is not only easy in the photolithography process when forming the switching transistor 7, but also facilitates patterning. , the polysilicon can be easily etched without any remaining polysilicon during subsequent polysilicon etching. Furthermore, this step 21 makes it possible to form the memory node of the memory cell array sufficiently high, and although a large capacity can be obtained, the step difference between the memory cell array part and the peripheral circuit part can be reduced, resulting in high yield and high reliability. It is possible to form flexible aluminum wiring.

(Embodiment 4) FIG. 5 is a process cross-sectional view of a method for manufacturing a semiconductor memory device according to a fourth embodiment of the present invention. First, as shown in FIG. 5(a), a silicon oxide film 16 is formed on a silicon substrate 1. , a silicon nitride film 17 is formed, and a resist pattern 2 is formed thereon by a photolithography process. Next, as shown in FIG. 5(b), a silicon nitride film 17 is formed using the resist pattern 2 as a mask.
Etching Sumo Resist pattern 2 removal machine 5th
As shown in FIG. 5(C), the silicon substrate 1 is oxidized using the silicon nitride film 17 as a mask to form a second silicon oxide film 18.Next, a second resist pattern is formed as shown in FIG. 5(d). 20 to form the second resist pattern 20.
Then, as shown in FIG. 5(e), the silicon nitride film 17 is used as a mask to oxidize the silicon substrate 1 again to make the second silicon oxide film 18 thicker. A silicon oxide film 22 of No. 3 is formed.

Thereafter, as shown in FIG. 5(f), the silicon nitride film 17, the silicon oxide film 16, and the third silicon oxide film 22 are removed to form the recessed substrate 3 and the substrate 4 other than the recessed portions. A memory cell array and peripheral circuits are formed according to the embodiment to form a semiconductor memory device. According to this embodiment, the stepped portion 21 between the concave substrate 3 and the non-concave substrate 4 is formed by a small, smooth two-step difference.△ When the step difference between the concave substrate 3 and the non-concave substrate 4 becomes large However, not only is buttering easy in the photolithography process for forming the switching transistor 7 later, but also the polysilicon can be easily etched without any remaining polysilicon in the subsequent polysilicon etching. Furthermore, this step 21 makes it possible to form the memory node of the memory cell array sufficiently high, and although a large capacity can be obtained, the step difference between the memory cell array part and the peripheral circuit part can be reduced, resulting in high yield and high reliability. In Examples 1 to 4, the force t used to form the memory array portion on the recessed substrate and the peripheral circuit portion on the substrate other than the recessed portion is not limited to this. A similar effect can be obtained by forming a region with a high aspect ratio on a concave substrate and a region with a low aspect ratio on a substrate other than the concave portion. However, as is clear from the above explanation of the effects of the invention, according to the present invention, a large capacitance can be achieved. Even in stacked cells in which storage nodes are piled up high to achieve the desired results, by digging the substrate in the memory cell array formation area deeper than the peripheral circuit formation area, it is possible to absorb the level difference between the memory cell array and the peripheral circuitry, making the wiring formation process easier and reducing the wiring. It is possible to increase reliability.

Furthermore, even if it is necessary to deeply dig into the substrate, by forming the stepped portion in multiple stages, it is possible to prevent difficulty in patterning in the first half of the memory cell forming process.

[Brief explanation of drawings]

FIG. 1 is a process cross-section of a first embodiment of the method for manufacturing a semiconductor memory device according to the present invention. FIG. 2 is a schematic top view of the first embodiment of the method for manufacturing a semiconductor memory device according to the present invention. The figure shows a second method of manufacturing a semiconductor memory device according to the present invention.
FIG. 4 shows a process cross-section of the third embodiment of the method for manufacturing a semiconductor memory device according to the present invention.
The figure shows a process cross-section of the fourth embodiment of the method for manufacturing a semiconductor memory device according to the present invention. FIG. 3... Concave part substrate 4... Base plate other than the concave part 7...
・Switching transistor Hisashi 8...Bit weave 9・
...Storage node, 10...Dielectric! 11...
Plate siege 12...Aluminum air distribution 13...Memory cell array part, 14...Peripheral circuit part, 15
...Boundary part.

Claims (3)

[Claims] (1) A semiconductor memory device including a memory cell array formed in a recessed region of a silicon substrate and a peripheral circuit formed on a substrate other than the recessed region (2) A method for manufacturing a semiconductor memory device comprising the steps of forming a recess in a part of a silicon substrate, forming a memory cell array at least on the recess, and forming a peripheral circuit on the substrate other than the recess. . (3) The method of manufacturing a semiconductor memory device according to claim 2, characterized in that when forming the recessed portion, the step portion is formed in a plurality of steps to reduce the step difference per step.