JPH0344426B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] This invention realizes an efficient IC pattern when converting a binary signal delay circuit using a CMOS gate circuit into an IC, and also reduces waveform distortion ( This invention relates to a CMOS integrated circuit for signal delay which reduces delay time distortion. [Prior art] As shown in Figure 2, the CMOS gate circuit
Channel MOS-FET12 and N-channel MOS
- Connect the gates of the FETs 14 and the drains thereof, apply the power supply voltages V _DD and V _SS to the sources, input a signal to the gate via the input terminal 13, and invert the input signal from the drain to the output terminal 15. It is designed to extract signals. In this CMOS gate circuit 10, a delay time occurs between input and output. This delay time is
As shown in FIG. 3, it depends on the power supply voltage V _DD -V _SS , and the smaller the power supply voltage V _DD -V _SS is, the larger the delay time and the larger the rate of change thereof. This is the power supply voltage
This is because the conductance of the element changes depending on V _DD −V _SS . Therefore, by utilizing this property, it is possible to control the delay time to an arbitrary value by adjusting the magnitude of the power supply voltage V _DD −V _SS . According to a signal delay circuit using such a CMOS gate circuit 10, for example, a technique for delaying a pulse frequency modulation signal containing analog information on the time axis (for example, a technique for delaying a pulse frequency modulation signal containing analog information on the time axis (for example, a method for delaying jitter (time) in a reproduced video signal in a video disc retransmission device) It can be used to absorb shaft fluctuations). This inputs the reproduced video signal containing jitter to a CMOS gate circuit, extracts the color burst signal from the video signal output from there, and converts it to a 3.58MHz crystal oscillation clock that supports the color burst subcarrier. Phase comparison and CMOS according to its phase error
By controlling the power supply voltage V _DD −V _SS of the gate circuit, a video signal with jitter absorbed is output from the CMOS gate circuit. By the way, if you need a long delay time,
As shown in FIG. 4, it is sufficient to connect the CMOS gate circuits 10 in multiple stages, but when converting this into an IC,
The power lines 15 and 16 must be routed over a long distance. However, when integrated circuits are used, the width of the power supply lines 15 and 16 decreases, and the impedance of the power supply lines increases accordingly.
This results in unexpected power supply voltage changes, making delay time control inaccurate. Therefore, in this invention, as described later,
This problem is solved by folding a continuous pattern of CMOS gate circuits connected in multiple stages. However, the folded configuration may cause the following inconveniences. If you bend it carelessly, the delay time of the entire circuit for the rising and falling parts of the input waveform will decrease.
This tends to cause a difference in T _r and T _f , resulting in distortion of the output waveform (change in duty), making it unusable when handling the aforementioned video disc playback signal that has information on the time axis. I end up. The upper limit of the operating input frequency is lowered at the bent portion. For periodic input signals, many
The CMOS gate operates, causing an unexpected voltage drop due to concentration of operating current, making delay time control inaccurate. [Problems to be Solved by the Invention] This invention attempts to solve the problems in the conventional technology, and shortens the power supply line by folding the continuous pattern formed by multi-stage connection of CMOS gate circuits. The present invention aims to provide a CMOS integrated circuit for signal delay, which can prevent an increase in the impedance of the same line by making it possible to reduce the number of lines, and also prevent output waveform distortion caused by a folded configuration. [Means for Solving the Problems] The present invention arranges a multi-stage connection configuration of CMOS gate circuits as a folded pattern on an integrated circuit board, and each column forming this folded pattern is connected to an odd number of stages of CMOS gate circuits. It is configured with a gate circuit. [Operation] According to the solution of the present invention, the power supply lines (V _DD , V _SS ) are
It is now possible to route the power supply lines in a comb-like manner and alternately facing each other, thereby minimizing the adverse effects of an increase in the impedance of the power supply line. In addition, by configuring each column with an odd number of CMOS gate circuits, it is possible to effectively cancel out the delay time variations that occur in the folding section, and the rise and fall delay times (T _R , T _F ) can be made equal, and generation of output waveform distortion can be prevented. In the example below, by placing a CMOS gate circuit with a large current supply capacity at the final stage of each column, it is possible to prevent the operation speed of the CMOS gate from decreasing due to an increase in the load capacity of the folding section, and to increase the speed of input signals. Prevents deterioration in followability to changes. In other words, the maximum operable frequency does not drop, and high-speed input can be transmitted without waveform distortion. Furthermore, by dividing each column into an odd number of blocks each having an odd number of stages, and placing a CMOS gate circuit with a large current supply capacity at the final stage of each block, the period of the input signal can be adjusted to each stage. Even for periodic inputs, whether or not they are an integral multiple of the delay time, the operating timings of each CMOS gate element will be shifted from each other, making it difficult for concentration of operating current to occur. Therefore, the supply voltage
There is no change in V _DD or V _SS , preventing unexpected changes in delay time, and enabling transmission without waveform distortion between input and output. Further, in this case, by setting the number of stages of each block to a different odd number, this effect is brought about for all input frequencies within a predetermined band. [Embodiment] FIG. 1 shows an example of a chip pattern of a CMOS integrated circuit for signal delay according to the present invention. This chip pattern consists of small pieces shown in strips.
20 are individual CMOS gate circuits. Each column 22 is
It is constructed by connecting an odd number of CMOS gate circuits 20 in series, and is folded back at the end and connected to the next column, thereby forming a continuous pattern of one delay circuit as a whole. When a binary signal is input from the input terminal 24, its delayed output is taken out from the output terminal 26. The power line 28 is drawn out from the bus bar 28a through a comb-shaped branch line 28b, and is connected to each row from the terminal 28c.
22 is supplied with the power supply voltage V _SS . The power supply line 30 is drawn out from the bus bar 30a so that comb-like branch wires 30b alternately face the branch wires 38b, and supplies a power supply voltage V _DD to each column 22 from a terminal 30c. The delay time is controlled by these power supply voltages V _DD and V _SS . The number of stages of CMOS gate circuits 20 in each column 22 is an odd number, and is 231 stages in this embodiment.
Further, the number of columns 22 is 44 in this embodiment. Here, the chip patterns of the individual CMOS gate circuits 20 constituting each column 22 will be explained.
Here, two types of chip patterns for the CMOS gate circuit 20 are prepared: type A (for small current) and type B (for large current).
The B type is arranged at the last stage of each column and the last stage of a block obtained by dividing each column into an odd number of stages, and the A type is arranged at the other parts. In addition, the chip pattern here is composed of two CMOS gate circuits as one set. As for the combination of two pieces, A-A (a combination of A types), A-B
(Combination where B type comes after A type), B-A
(a combination in which type A comes after type B).
Note that since each column is composed of an odd number of stages of CMOS gate circuits, one B type pattern is prepared and used in the final stage of each column. An example of an A-B type chip pattern is shown in FIG. Moreover, the electric circuit is shown in FIG. This CMOS gate circuit is constructed by cascading an A-type CMOS gate circuit 20-1 and a B-type CMOS gate circuit 20-2. The chip pattern of a conventional CMOS gate circuit is
The P channel side and the N channel side were constructed symmetrically, but in the one shown in FIG. 5, the P channel side and the N channel side are different from each other in the gate and beyond. This is because if the shape is symmetrical, the difference in the characteristics of the P channel and N channel will cause a difference in the rise and fall characteristics of the output. In this case, the duty ratio of the input/output pulse waveform changes, making it difficult to faithfully reproduce the disc recorded information. Therefore, in Fig. 5, the width and length of the gate pattern of each channel element N and P are adjusted, and when the same external voltage condition is applied to each channel element, the operating current value of each channel element is equal. It is set so that The CMOS gate circuit 20-1 is a P channel
It is composed of a MOS-FET1 and an N-channel MOS-FET2. The input signal is input from the terminal 22 and applied to the gates G _p1 and _Go1 of the first stage 20-1 via the wiring 24. Power supply V _DD is connected to electrode 26
is applied to the source S _p1 via. The electrode V _SS is
It is applied to the source S _o1 via the electrode 28 . Then, the output signals of the drains D _p1 and D _o1 are the terminal 3
0 to the gate of the second stage 20-2 via the wiring 31
Applied to G _p2 and G _o2 . In the second stage 20-2, the power supply V _DD is applied to the source S _p2 via the electrode 26. A power source V _SS is applied to the source S _o2 via the electrode 28 . and,
The output signals of the drains D _p2 and D _o2 are outputted via the terminal 32. The A type CMOS gate circuit 20-1 is P
Channel MOS-FET1 and N-channel MOS-
When a common power supply V _DD and V _SS are applied to FET2, the width (W)/length (L) of the gates G _p1 and G _o1 are determined by adjusting the structure and material characteristics of each channel element so that I _D is equal. It is set according to the value of the constant K' determined from and the threshold voltage V _th . the result,
W/L of N-channel MOSFET 1 is smaller than W/L of P-channel MOSFET 2. An example of the dimensions of gates G _p1 and G _o1 is shown in the table below.

[Table] However, w and l are effective lengths, which become shorter than the set values W and l depending on the manufacturing process as shown by the following equation. w=W-1.5 l=L-1.0 B type CMOS gate circuit 20-2 is P
Channel MOS-FET3 and N-channel MOS-
When a common power supply V _DD , V _SS is applied to FET4, the width (W)/length (L) of the gate G _p2 , G _o2 is set to K′, K′ of each channel element, so that _ID is equal.
Set according to the value of V _th . As a result, the W/L of N-channel MOS-FET3 is
It becomes smaller than W/L of MOS-FET4. An example of the dimensions of gates G _p2 and G _o2 is shown in the table below.

[Table] In the above design, the B type has a current supply capacity 1.6 times that of the A type. Next, details of the chip pattern shown in FIG. 1 using these CMOS gate circuits 20 will be explained. (1) Arrangement of CMOS gate circuit 20 and configuration of power supply line The electric circuit of the chip pattern shown in FIG. 1 is shown in FIG. This chip pattern is constructed by folding back an odd number of continuous patterns in which CMOS gate circuits 20 are connected in multiple stages.
A signal inputted from the circuit is delayed at each stage and output from the output terminal 26. This allows a large number of CMOS gate circuits 2 to be mounted on a limited chip board.
0 can be placed efficiently. In the power supply line 28, a comb-like branch line 28b is drawn out from the bus bar 28a, and supplies a power supply voltage V _SS to each CMOS gate circuit 20. Also,
In the power supply line 30, a comb-like branch line 28b is drawn out from the bus bar 30a, and supplies a power supply voltage V _DD to each CMOS gate circuit 20. According to the configuration of the power supply lines 28 and 30, a plurality of branch lines 28b and 30b are drawn out from the bus bars 28a and 30a, so that the power supply voltage V is applied to all the CMOS gate circuits 20 by the two power supply lines. Compared to supplying _SS and V _DD , the amount of wiring of the power supply line can be efficiently shortened, and an increase in the impedance of the power supply line can be prevented. Therefore, unexpected power supply voltage changes are eliminated, and delay time controllability is improved. Moreover, since one branch line 28b, 30b is involved only in two columns of the CMOS gate circuit 20, a voltage change in one part is less likely to spread to other parts. (2) CMOS gate circuit 20 in one column 22
As described above, the gate width (W)/length (L) of each CMOS gate circuit 20 itself is adjusted so that the current characteristics of the P channel and the N channel are the same. However, even with this adjustment, there may be a slight difference in t _r (delay time associated with rising inversion operation) and t _f (delay time associated with falling inversion operation) of each CMOS gate circuit 20. is quite conceivable. Consider a delay time (T _r , T _f ) of 22 minutes for one row. (A) When one column 22 is composed of an even number of stages of CMOS gate circuits 20 First, let us simply consider the linearly arranged portion. In this case, it is assumed that there are 200 stages as shown in FIG. One row 22 for the rising part a of the input signal
Total delay time T _r and total delay time of one column 22 for the falling part b of the input signal
T _f becomes T _r =100t _f +100t _r T _f =100t _r +100t _f . Assuming that the rise delay time t _r of the CMOS gate circuit 20 in each stage is equal for all stages, and the fall delay time t _f is also equal for all stages, T _r = T _f even if t _r = t _f. (=T ₀ ), and the difference between the rising and falling delay times ΔT
becomes ΔT=T _r −T _f =0. That is, there is no change in duty (delay time distortion) between the input waveform and the output waveform. Next, considering the folded part 36, in the final stage (200th stage), due to the pattern routing of the folded part 36, if the load capacity of other normal parts is taken as the standard 1, the load capacity of this folded part is (1+K ), that is, the load capacity increases by K, so the delay times T _r and T _f are T _r = 100t _f + (100 + K) t _r = T ₀ + Kt _r T _f = 100t _r + (100 + K) t _f = T ₀ +Kt _r , and if the delay time of each stage is t _r =t _f , then ΔT = T _r −T _f =0. However, this is difficult to achieve in practice. Therefore, normally t _r = t _f , and in that case, the difference ΔT between the rising and falling delay times is ΔT = |T _r −T _f |=K|(t _r −t _f )| If there are n columns, nΔT=nK|(t _r −t _f )| for the entire chip. For example, if n=40 and K=0.2, nΔT=8|(t _r −t _f )|. Therefore, if one column is made up of an even number of stages, there will be a difference between each column by (difference between t _r and t _f of the last stage gate of each column) x K, and these differences will be added to each column. The difference in delay time between the rise and fall of the chip as a whole becomes large. Therefore, the duty ratio of the input and output waveforms changes, causing delay time distortion.
In a pulse frequency modulated signal, this leads to a change in the modulation component (time axis distortion). (B) When one column 22 is composed of an odd number of stages of CMOS gate circuits 20 As shown in FIG. 9, it is assumed that one column 22 is composed of 201 stages. One row 22 for the rising part a of the input signal
Total delay time T _r1 and total delay time of one column 22 for the falling part b of the input signal
T _f1 is T _r1 = 100t _f +100t _r +t _f (1+K) T _f1 = 100t _r +100t _f +t _r (1+K), and the difference in delay time between rising and falling edges ΔT ₁
is ΔT ₁ = T _r1 − T _f1 = t _f (1+K) − t _r (1+K) Since one row 22 is composed of an odd group, 1
If the input on one column is a rising edge, the input on the next column will be a falling edge. Therefore, the delay times T _r2 and T _f2 in the next row are: T _r2 = 100t _r + 100t _f + t _r (1+K) T _f2 = 100t _f + 100t _r + t _f (1+K) Difference between rising and falling delay times ΔT ₂ is ΔT ₂ = T _r2 −T _f2 = t _r (1+K) − t _f (1+K) Therefore, when considering the two columns as a whole, the difference in delay time between the rise and fall is ΔT ₁ +ΔT ₂ = It becomes 0 and is cancelled. Therefore, one column 22
consists of an odd number of stages, and the number of rows of one chip is n
If is an even number, the difference between the rise and fall delay times of the entire chip is zero. In other words, no delay time distortion occurs in the output waveform. Also, n
Even if is an odd number, only a delay time difference ΔT ₁ or ΔT ₂ of 22 minutes per column occurs. In the embodiment shown in Fig. 1, the number of stages in one row of 22 is 231,
By setting the number of columns in the entire chip to 44, delay time distortion of the output waveform is completely canceled. (3) Increase in current supply capacity at the folding portion 36 of each column In (2) above, by setting the number of stages in one column 22 to an odd number, the delay time difference between the rising and falling portions of the input signal is canceled out. However, if each column is configured to cancel out the increase in load capacity K at the folded portion 36, the delay time difference can be more completely eliminated for the chip as a whole (regardless of whether the even-numbered columns or odd-numbered columns). can. To this end, as shown in FIG. 10, the current supply capability of the CMOS gate circuit 20 at the final stage of each column may be increased in accordance with the increased load capacitance K. That is, the B type 20- shown in FIG.
2, the drive capacity of the CMOS gate circuit is made 1+K times that of type A in accordance with the increased load capacitance K. Further, by adopting such a configuration, there is an effect that the upper limit frequency of the input signal, which may be delayed, is not lowered. That is, folded part 3
Assuming that the current supply capacity of the CMOS gate circuit No. 6 is the same as the others, it takes time to charge and discharge as the load capacitance increases by K, and the delay time of that portion is longer than the others. Another way to look at this is that it takes time to invert the signal, and it is not possible to follow high frequency input changes. That is, unless the folding portion 36 is strengthened, that portion will become a link, lowering the overall operable upper limit frequency, and in the worst case, the signal will disappear midway. Therefore, as mentioned above, a B-type CMOS gate circuit with a large current supply capacity is installed at the final stage of each column.
If 0-2 is used, this problem can also be solved. (5) Block division within column 22 A periodic input signal is input to a delay circuit formed by cascading a number of CMOS gate circuits having the same delay time, and this period is an integer multiple of the delay time. , the CMOS gate circuits for each integer number always operate at the same timing. CMOS
When the gate circuit operates, the operating current shown in Figure 11 flows through the power supply line, so in this case, the current for the number of gate circuits that operate at the same timing will concentrate at that timing and flow through the power supply line. . And since there is naturally a certain amount of impedance in the power line,
Depending on the degree of current concentration, an unexpected drop in power supply voltage may occur at each cycle, which may adversely affect the delay time control operation of the delay circuit. In particular, pulse frequency modulation signals from video discs, etc., have various periods varying between 7.6 and 9.3 MHz according to the standard, so no matter what the value of the delay time is, if it is uniform, it will always be one of the following. The operation current concentration phenomenon described above occurs at a frequency of . By the way, these operating current concentration phenomena occur when the CMOS gate circuits a, b,
This is due to the rise and fall of c, . As shown in Figure 12b,
The delay times between the CMOS gate circuits a, b, and c are set to be appropriately different. Figure 13 shows how one branch line of the current line 28 corresponds to the period of the input signal when the A type 20-1, which has a delay time of 2.9 ns per stage, is configured with 231 stages per column. This figure shows how the operating current for two columns related to the change changes. Here, the range from 7.6 to 9.3 MHz mentioned above is shown, and the DC component of the operating current is cut out and only the changing component is shown. The sloped line shown in the upper part of the figure shows the maximum number of stages of current concentration that can theoretically occur within two rows (when the operating current value of one stage is taken as reference 1, this number of stages corresponds to the total current value). . According to this, the period of the input signal is 110.2ns, which is an integer multiple of 2.9ns.
(equivalent to 38 stages of delay time), 113.1ns (39 stages),
116.0ns (40 steps), 118.9ns (41 steps), 121.8ns
Operating current concentration occurs at (42 stages), 124.7ns (43 stages), 127.6ns (44 stages), and 130.5ns (45 stages). Therefore, as shown in FIG. 14, each column 22 is divided into an odd number of blocks each consisting of an odd number of CMOS gates 20, and the last gate of each block is connected to the gate shown in FIG. By arranging the type 20-2 to form an aperiodic structure, the operation timing within each column 22 can be changed appropriately, and concentration of operation current can be prevented. In particular, if the number of stages within a block is different, distribution over the entire frequency range can be achieved. In this case, the idea of selecting the number of stages is to consider the cycle change width of the input signal up to two cycles each, and decide the stage whose timing is difficult to match. For example, in the case of a video disc, assuming the delay time for one stage is 2.9ns, the number of stages shown in the following table is 2.
This is the number of stages with matching timing up to a period.

〔Effect of the invention〕

As explained above, according to the solving means of the present invention, by using the folded structure, the power lines are also arranged in a comb-like shape and staggered.
It becomes possible to route the wires so that they face each other, and the negative effects of increased impedance can be minimized. In addition, by configuring each column with an odd number of CMOS gate circuits, it is possible to effectively cancel out the elements of delay time variation that occur in the turning portion, and to equalize the rise and fall delay times of the entire circuit. This makes it possible to prevent output waveform distortion from occurring.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an IC chip pattern showing an embodiment of the present invention. Figure 2 shows CMOS
FIG. 2 is a circuit diagram showing a gate circuit. Figure 3 shows
FIG. 3 is a diagram showing delay characteristics of a CMOS gate circuit.
FIG. 4 is a circuit diagram showing a cascade connection of CMOS gate circuits. FIG. 5 is a diagram showing a chip pattern of two CMOS gate circuits used in the IC chip pattern of FIG. 1. Figure 6 shows the fifth
FIG. 3 is an electrical circuit diagram of the chip pattern shown in FIG. FIG. 7 is an electrical circuit diagram of the chip pattern of FIG. FIG. 8 is a diagram showing the operation of each stage when the number of stages in one column 22 is an even number. FIG. 9 is a diagram showing the operation of each stage when the number of stages in one column 22 is an odd number. 1st
FIG. 0 is a circuit diagram in which a B-type CMOS gate circuit 20-2 having a large current supply capacity is arranged at the final stage of the column 22. FIG. 11 is a waveform diagram showing the operation of the CMOS gate circuit. FIG. 12 is an explanatory diagram of the current concentration phenomenon. Figure 13 shows an A-type CMOS gate circuit 20 in which the delay time of one stage is 2.9 ns.
FIG. 7 is a diagram showing how the overall operating current changes with respect to the cycle of the input signal when all stages are configured with -1. In FIG. 14, each column 22 is divided into an odd number of blocks each consisting of an odd number of CMOS gates 20, and a B-type CMOS gate circuit 20-2 with a large current supply capacity is arranged at the last gate of each block. This is what I did. Figure 15 shows
13 is a diagram showing changes in the overall operating current with respect to the period of the input signal according to the configuration of FIG. 12. FIG. Figure 16 shows two rows of the chip pattern in Figure 1.
FIG. 3 is a diagram showing the arrangement of a CMOS gate circuit. 20...CMOS gate circuit, 20-1...A
Type CMOS gate circuit, 20-2... B type CMOS gate circuit, 28, 30... Power line, 28a, 30a... Bus bar, 28b, 30b...
...branch line.

Claims (1)

[Claims] 1 Consists of a multi-stage connection configuration of CMOS gate circuits,
In these CMOS integrated circuits for signal delay, which delay and output an input consisting of a binary signal by a predetermined time in accordance with the power supply voltage control of the CMOS gate circuit, the multi-stage connection configuration of the CMOS gate circuit has a folding pattern. 1. A CMOS integrated circuit for signal delay disposed on an integrated circuit board, wherein each column forming the folded pattern is comprised of an odd number of stages of CMOS gate circuits. 2 The last stage of each row has a large current supply capacity.
For signal delay according to claim 1, characterized in that a CMOS gate circuit is arranged.
CMOS gate circuit. 3. Claims characterized in that each column is divided into an odd number of blocks each having an odd number of stages, and a CMOS gate circuit with a large current supply capacity is arranged at the final stage of each of these blocks. The CMOS gate circuit for signal delay according to item 1. 4. The CMOS gate circuit for signal delay according to claim 3, wherein the number of stages of each block is a different odd number.