JPH0344228A - Data collection method - Google Patents

Abstract

PURPOSE:To read a data stably at a data change point by providing a counter section counting an error pulse, a buffer register, a processing section, a timing section and a clear pulse generating section. CONSTITUTION:A monitor circuit 1 checks a monitor signal in a main signal to send an error pulse to a counter section 2, performance monitor information sent from the counter section 2 is inputted to a buffer register 4 and a shift data is sent to a processing section 3. The processing section 3 inputs a 1sec timer to a timing section 5 and a shift pulse is sent from the timing section 5 to the buffer register 4 with a clock signal synchronously with the main signal. A clear pulse generating section 6 uses the shift pulse from the timing section 5 and the clock signal synchronously with the main signal to send the clear signal to the counter section 2 to clear the count in the counter section 2. Thus, the data between the counter, 2 and a CPU 3 is read accurately.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method of collecting monitor information for checking the quality of digital transmission lines and monitoring errors. A monitor circuit that checks monitor information for performance monitoring, a counter unit that counts error pulses checked by the monitor circuit, a buffer register that shifts the count value, and a processing unit that processes data from the buffer register. a timing section that detects a one-second timer from the processing section and generates a shift pulse; and a clearing section that sends a clear signal to the counter section using the shift pulse from the timing section and a clock signal synchronized with the main signal. the buffer register is shifted by a shift pulse from the timing section, and a clear signal is sent to the counter section.

[Industrial application field]

The present invention relates to a method for collecting monitor information for quality checking and error monitoring of digital transmission lines.

Monitor information for checking the quality of data on the digital transmission line and monitoring errors, that is, performance information includes code error information (C■), bipolar error information (BP
V), parity check result information (PTY), information on the number of errors per second (ES), information on the number of special errors per second (SES), etc. These performance information are stored for about 1 second for each parameter. By monitoring and checking how many bits of error information have occurred in the data, we aim to improve transmission quality.

A data collection method has conventionally been used in digital transmission lines in which error pulses of this monitor information are counted and processed by a CPU as performance monitor information, and an alarm or the like is generated based on the count result to notify maintenance personnel.

[Conventional technology]

A block diagram of a conventional data reading circuit for performance monitor information, etc. is shown in FIG. In the figure, 21 is a monitor circuit, 22 is a counter, and 23 is a CPU.

The monitor circuit 21 monitors the monitor information from the digital signal line.
and checks whether the information monitored by the monitor circuit 21 is incorrect. If the information is incorrect, an error pulse is output to the counter 22 at a timing synchronized with the main signal, and the counter 22 outputs the error pulse. Count the numbers. This count result becomes performance monitor information.

After the performance monitor information is read by the CPU 23 at a 1 second cycle, the performance monitor information is immediately sent from the CPU 23 to the counter 22.
A clear signal is output to clear the . However, when the error pulse is read by the CPU 23, the error pulse is synchronized with the main signal, and the read timing is synchronized with the clock that operates the CPU 23, so the error pulse is asynchronous. For this reason, there was a possibility that data could be read at a change point in the output data (performance information) of the counter 22.

In addition, performance monitor information accumulates the results of monitoring for one second as performance monitor information.
When monitoring multiple main signals, one for each main signal.
Managing the second timer was difficult.

[Problem to be solved by the invention]

Since the error pulse output to the counter and the performance monitor information read by the CPU are asynchronous,
There is a possibility that the CPU reads data at a change point in the output data of the counter, and in that case, there is a problem that the data lacks accuracy.

Also, since performance monitor information is based on cumulative data of each parameter such as errors that occur during a 1-second monitoring time unit, the 1-second timer is extremely important, but if there are multiple main signals to monitor, the conventional With this method, it was difficult to manage a one-second timer for each main signal.

In the present invention, a buffer register is provided between the counter and the CPU to ensure accurate data reading, and timer management is performed by synchronizing the one-second timer from the CPU with a clock that is synchronized with the main signal. purpose.

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, 1 is a monitor circuit, 2 is a counter section, and 3 is a processing section (CPU).
, 4 is a buffer register, 5 is a timing section, and 6 is a clear pulse generating section.

The monitor circuit 1 checks the monitor signal from the main signal, sends an error pulse to the counter section 2, and outputs an error pulse to the counter section 2.
The performance monitor information sent from the controller 4 is input to the buffer register 4, and shift data is sent to the processing section 3. The processing section 3 inputs a one-second timer to the timing section 5, and sends a shift pulse from the timing section 5 to the buffer register 4 using a clock signal synchronized with the main signal. The clear pulse generating section 6 sends a clear signal to the counter section 2 using a shift pulse from the timing section 5 and a clock signal synchronized with the main signal, and clears the count value of the counter section 2.

[Effect]

A timing chart for explaining the present invention in detail is shown in FIG. In the figure, ■ is a shift pulse sent from the timing section 5 to the buffer register 4, ■ is a clear signal sent from the clear pulse generating section to the emptying section 2, and ■ is a clear signal sent from the buffer register 4 to the processing section 3. This shows the shift data.

(2) When a one-second timer is inserted into the timing section 5 from the processing section 3, pulses of several μs are sent from the timing section 5 at the beginning and end of the one-second timer. The buffer register 4 is shifted by the fall of this signal, and the performance information from the counter section 2 input to the buffer register 4 is shifted to fix the count value.

(2) The clear pulse generating section 6 receives this shift pulse and sends a clear pulse to the counter section 2 using a clock signal synchronized with the main signal, thereby clearing the count value of the counter section 2 to zero.

(2) Regarding the counter information shifted by the buffer register 4, the count value of the period (1 second - several μs) from the rising signal to the falling signal from the timing section 5 is read as performance information by the processing section 3.

〔Example〕

A block diagram of an embodiment of the present invention is shown in FIG. In the figure, ■ is a monitor circuit, 12 is a counter section, and 13 is a C
PU, 14 is a buffer register, 15 is a timing section,
16 indicates a clear pulse generating section.

The counter section 12, buffer register 14, and timing section 15 each include a plurality of flip-flop circuits.

The counter unit 12 inputs the error pulse from the monitor circuit 11 to the CLK terminal, inputs the count output from the Q terminal to the D terminal of the buffer register 14, and inputs the clear signal type from the clear pulse generator 16 to the LR terminal. do. The buffer register 14 receives a shift pulse from the timing section at its CLK terminal, and sends the shifted performance information data from its Q terminal to the CPU 13. The timing unit 15 inputs the 1-second timer from the CPU 13 to the 1〇 terminal, inputs a clock signal synchronized with the main signal to the CL terminal, and sends a shift pulse from the Q terminal to the buffer register 14 and the clear pulse generator 16. do. The clear pulse generating section 16 ANDs the clock signal synchronized with the main signal and the shift pulse from the timing section 15, and sends a clear signal to the counter section 12.

The monitored error pulse from the monitor circuit 11 is separated for each parameter and input to the flip-flop of the counter section 22, and each output is sent to the buffer register 14.
The CPU 13 can read the performance information data of count values inputted to the CPU 13 and shifted by shift pulses of the same timing, and separated for each parameter. Since the count value for each parameter starts counting after being cleared by the same clear signal, it can be counted using a clock signal synchronized with the main signal.

With the above circuit, the count value can be shifted by the same shift pulse, and the counter can be cleared by the same clear pulse. Further, after the performance monitor information is shifted to the buffer register 14, the timing section 15
Based on the shift pulse generated, a clear pulse for clearing the counter section 12 is generated in the clear pulse generating section 16, and the counter is cleared by this pulse.

The period during which the CPU 13 reads data is about 1 second.

〔Effect of the invention〕

As explained above, even when multiple signals are monitored, sufficient time can be obtained for the CPU, etc. to read the data, so a large amount of data can be handled just by managing one timer. Furthermore, since the data read by the CPU does not change during a period other than when the CPU or the like is outputting the timer, it is possible to always read stable data.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing the principle of a timing chart of the present invention, FIG. 3 is a block diagram of an embodiment, and FIG. 4 is a diagram of a conventional program. In the figure, 1. IL 21 is a monitor circuit, 2, 12° 22 is a counter section, 3.13.23 is a processing section (CPU)
, 4.14 is a buffer register, 5.15 is a timing section, and 6 and 16 are clear pulse generation sections. Principle configuration diagram of the present invention's1 Figure 1 - Clearing the counter -------; - Shifting information to the buffer register Timing chart principle diagram of the present invention Figure 2

Claims (1)

[Claims] A monitor circuit (1) that checks monitor information for monitoring the performance of digital signals, and a counter unit (2) that counts error pulses checked by the monitor circuit (1).
and a buffer register (4) that shifts the count value.
, a processing section (3) that processes data from the buffer register (4), a timing section (5) that detects a one-second timer from the processing section (3) and generates a shift pulse, and a timing section (5) that processes data from the buffer register (4). a clear pulse generating section (6) that sends a clear signal to the counter section (2) using a shift pulse from the timing section (5) and a clock signal synchronized with the main signal; A data collection method characterized in that the buffer register (4) is shifted by a pulse and a clear signal is sent to the counter section (2).