JPH0344066A - Laminating method of semiconductor substrate - Google Patents
Laminating method of semiconductor substrateInfo
- Publication number
- JPH0344066A JPH0344066A JP17926789A JP17926789A JPH0344066A JP H0344066 A JPH0344066 A JP H0344066A JP 17926789 A JP17926789 A JP 17926789A JP 17926789 A JP17926789 A JP 17926789A JP H0344066 A JPH0344066 A JP H0344066A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- layer
- melting point
- semiconductor substrate
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000010030 laminating Methods 0.000 title abstract description 5
- 239000010409 thin film Substances 0.000 claims description 14
- 239000010408 film Substances 0.000 claims description 13
- 238000002844 melting Methods 0.000 abstract description 21
- 229910052751 metal Inorganic materials 0.000 abstract description 21
- 239000002184 metal Substances 0.000 abstract description 21
- 230000008018 melting Effects 0.000 abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052710 silicon Inorganic materials 0.000 abstract description 18
- 239000010703 silicon Substances 0.000 abstract description 18
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 238000003475 lamination Methods 0.000 abstract description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- 239000010937 tungsten Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体基板の積層方法に関するものであり、詳
しくはデバイスがすでに形成された複数の半導体基板の
積層方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for laminating semiconductor substrates, and more particularly to a method for laminating a plurality of semiconductor substrates on which devices have already been formed.
（従来の技術）
ＭＯＳトランジスター等から構成されるデバイス層が縦
方向に積層されている３次元ＬＳＩの製造方法として、
シリコン基板上に１層目デバイスを形成した後、層間絶
縁膜形成工程、レーザアニール法等によるＳＯＩ結晶形
成形成およびＳＯＩデバイス形成工程とを逐次繰り返す
積層法が知られている。(Prior Art) As a method for manufacturing a three-dimensional LSI in which device layers composed of MOS transistors and the like are stacked vertically,
A lamination method is known in which, after forming a first layer device on a silicon substrate, an interlayer insulating film forming step, SOI crystal formation by a laser annealing method, etc., and an SOI device forming step are sequentially repeated.
（発明が解決しようとする課題）
しかしながら、」二連した積層法の場合、デバイスを形
成するための要素プロセス（たとえば、イオン注入工程
、リングラフ工程等）が層間絶縁膜形成工程およびＳＯ
Ｉ結晶形成工程を介して直列状に並ぶため、積層数に比
例して総工程数が増加し、ＴＡＴ（Ｔｕｒｎ−Ａｒｏｕ
ｎｄ−Ｔｉｍｅ）が著しく長期化するといったプロセス
上の課題があった。(Problem to be Solved by the Invention) However, in the case of the double stacking method, the elemental processes for forming a device (for example, ion implantation process, phosphorus process, etc.) are interlayer insulating film formation process and SO
Because they are arranged in series through the I crystal formation process, the total number of processes increases in proportion to the number of laminated layers, and TAT (Turn-Arou
There were process issues such as extremely long lead times (nd-time).
本発明の目的は３次元ＬＳＩ製造のＴＡＴを短縮化する
方法を提供することにある。An object of the present invention is to provide a method for shortening the TAT of three-dimensional LSI manufacturing.
（課題を解決するための手段）
以下の（ア）に示す積層用デバイス形成プロセスにより
テ゛バイス上に接続電極を形成し、さらに以下の（イ）
に示すデバイス積層プロセスにより第１−の半導体基板
に形成された第１層目デバイス上にデバイスを順次積層
することを特徴とする半導体基板の積層方法。(Means for solving the problem) Connecting electrodes are formed on the device by the stacking device forming process shown in (a) below, and then (b)
A method for stacking semiconductor substrates, comprising sequentially stacking devices on a first layer device formed on a first semiconductor substrate by the device stacking process shown in FIG.
（ア）積層用デバイス形成プロセス
半導体基板にデバイスを形成する工程と、前記デバイス
上に表面側接続電極を形成する工程により半導体基板上
に表面側接続電極の形成されたデバイスを形成するプロ
セス。(A) Stacking device formation process A process of forming a device on a semiconductor substrate with a front-side connection electrode formed by a step of forming a device on a semiconductor substrate and a step of forming a front-side connection electrode on the device.
（イン デバイス積層プロセス
第１の半導体基板に形成されている第１−層目デバイス
上の表面側接続電極と第２の半導体基板に形成されてい
る第２層目デバイス上の表面側接続電極とを位置合わせ
して接続する工程と、前記第２の半導体基板の裏面より
薄膜化する工程と、前記薄膜化工程により得られた第２
層目薄膜状デバイスの裏面に裏面絶縁膜を形成する工程
と、前記第２層目薄膜状デバイスの裏面に裏面側接続電
極を形成する工程と、第３の半導体基板に形成されてい
る第３層目デバイス上の表面側接続電極と前記第２層目
薄膜状デバイスの裏面側接続電極とを位置合わせをして
接続する工程と、前記第３の半導体基板の裏面より薄膜
化することにより第３層目薄膜状デバイスを形成する工
程と、前記第３層目薄膜状デバイスの裏面に裏面絶縁膜
を形成する工程と、前記第３の薄膜状デバイスの裏面に
裏面側電極を形成する工程。(In-device stacking process) The front side connection electrode on the first layer device formed on the first semiconductor substrate and the front side connection electrode on the second layer device formed on the second semiconductor substrate. a step of aligning and connecting the second semiconductor substrate, a step of thinning the second semiconductor substrate from the back surface of the second semiconductor substrate, and a step of thinning the second semiconductor substrate obtained by the thinning step.
forming a back insulating film on the back surface of the second layer thin film device; forming a back side connection electrode on the back surface of the second layer thin film device; a step of aligning and connecting the front side connection electrode on the second layer device and the back side connection electrode of the second layer thin film device; and a step of thinning the third semiconductor substrate from the back side. A step of forming a third layer thin film device, a step of forming a back insulating film on the back surface of the third layer thin film device, and a step of forming a back side electrode on the back surface of the third thin film device.
（作用）
上述した半導体基板の積層方法は、積層用デバイス形成
プロセスとデバイス積層プロセスとが分離されているこ
とが特徴である。このため、予め複数のデバイスをシス
テム・回路・マスクの設計からデバイス形成さらにデバ
イスの回路動作テストまで並列処理で用意しておいて後
、デバイスを順次積層するといった一部並列工程処理が
可能となり、積層数が増加してもＴＡＴが著しく長期化
するといった恐れはない。(Function) The above-described semiconductor substrate stacking method is characterized in that the stacking device forming process and the device stacking process are separated. For this reason, it is possible to perform partially parallel process processing, such as preparing multiple devices in advance in parallel from system/circuit/mask design, device formation, and device circuit operation testing, and then sequentially stacking the devices. Even if the number of laminated layers increases, there is no fear that the TAT will become significantly longer.
（実施例）
以下、この発明の実施例としてシリコン基板に形成され
たデバイスを３層積層する場合を例にとって説明する。(Example) Hereinafter, as an example of the present invention, a case in which three layers of devices formed on a silicon substrate are stacked will be described.
本発明による半導体基板の積層方法は積層用デバイス形
成プロセスとデバイス積層プロセスからなる。The method for laminating semiconductor substrates according to the present invention includes a lamination device forming process and a device lamination process.
第１図に積層用デバイス形成プロセスを説明するための
製造工程断面図を示す。積層用デバイス形成プロセスで
は、まず通常のＬＳＩ製造工程により回路機能の異なる
デバイス（１０１）をシリコン基板（１０２）に形成し
た後（第１図（ａ））、第１のシリコン基板（ｉｏａ）
に形成された第１層目デバイス（１０４）上の絶縁膜（
１０５）開口部にＩｎ等の低融点金属を埋め込んだ低融
点金属プール（１０６）を形成しく第１図（ｂ））、第
２のシリコン基板（１０７）に形成された第２層目デバ
イス上（１０８）にタングステン等の高融点金属バンプ
（１０９）を形成しく第１図（Ｃ））、さらに第３のシ
リコン基板（１１０）に形成された第３層目デバイス（
１１１）上に高融点金属バンプ（１０９）を形成する（
第１図（ｄ））。FIG. 1 shows a manufacturing process cross-sectional view for explaining the process of forming a stacked device. In the stacking device formation process, devices (101) with different circuit functions are first formed on a silicon substrate (102) by a normal LSI manufacturing process (Fig. 1(a)), and then a first silicon substrate (IOA) is formed.
The insulating film (
105) To form a low melting point metal pool (106) in which a low melting point metal such as In is embedded in the opening (Fig. 1(b)), on the second layer device formed on the second silicon substrate (107). A refractory metal bump (109) such as tungsten is formed on (108) (Fig. 1(C)), and a third layer device (109) is formed on a third silicon substrate (110).
forming a high melting point metal bump (109) on (111) (
Figure 1(d)).
上述した積層用デバイス形成プロセスにより得られた接
続電極付きデバイスを以下に説明するデバイス積層プロ
セスにより順次積層する。第２図に、デバイス積層プロ
セスを説明するための製造工程断面図を示す。デバイス
積層プロセスでは、まず第１層目デバイス（１０４）上
に形成した低融点金属プール（１０６）と第２層目デバ
イス（１０８）上の高融点金属バンプ（１０９）とが向
かい合うように位置合わせを行なう（第２図（ａ））。The devices with connection electrodes obtained by the above-described stacking device forming process are sequentially stacked by the device stacking process described below. FIG. 2 shows a manufacturing process cross-sectional view for explaining the device stacking process. In the device stacking process, first, the low melting point metal pool (106) formed on the first layer device (104) and the high melting point metal bump (109) on the second layer device (108) are aligned so that they face each other. (Figure 2(a)).
なお、上述したデバイスの位置合わせにはシリコンを透
過する赤外線顕微鏡を使用する。しかる後、１−層目デ
バイス（１０４）上の低融点金属プール（１０６）に２
層目デバイス上（１０８）の高融点金属バンプ（１０９
）が挿入されるまで１層目デバイスと２層目デバイスと
を密着することにより１層目デバイス（１０４）と２層
目デバイス（１０８）とを接続する（第２図（ｂ））。Note that an infrared microscope that transmits through silicon is used for positioning the above-described device. Thereafter, the low melting point metal pool (106) on the first layer device (104) is
Refractory metal bumps (109) on layered devices (108)
) is inserted, the first layer device (104) and the second layer device (108) are connected by bringing the first layer device and second layer device into close contact with each other (FIG. 2(b)).
上述したデバイス接続温度は低融点金属の溶融するより
も高い温度、すなわちインジュウムを埋め込んだ場合に
は２００°Ｃ〜３０００Ｃである。次に、第２層目デバ
イス（１０８）が形成されている第２のシリコン基板（
１０７）の裏面より選択ポリッシング（浜口恒夫ら、応
用物理、５６［１１］ｐｐ１４８０）を行い、薄膜状の
第２層目デバイス（２０１，）を得る（第２図（Ｃ））
。しかる後、薄膜状の２層目デバイス（２０１）裏面に
ＳｉＯ２等の裏面絶縁膜（２０２）を形成し、さらに前
記裏面絶縁膜（２０２）の開口部に低融点金属を埋め込
んだ低融点金属プール（１０６）を形成する（第２図（
ｄ））。しかる後、前記薄膜状の２層目デバイス（２０
１）の裏面に形成された低融点金属プール（１０６）と
第３層目デバイス（１１０）上の高融点金属バンプ（１
０９）とが向かい合うように位置合わせした後（第２図
（ｅ））、薄膜状の２層目デバイス上の低融点金属プー
ル（１０６）に３層目デバイス（１１１）上の高融点金
属バンプ（１０９）が挿入されるまで薄膜状の２層目デ
バイス（２０１）と３層目デバイス（１１１）とを密着
することにより２層目デバイスと３層目デバイスを電気
的に接続する（第２図（０）。しかる後、第３層目デバ
イス（１１１）が形成されている第３のシリコン基板（
１１０）の裏面より選択ポリッシングを行い薄膜状の第
３層目デバイス（２０３）を得る（第２図（ｇ））。し
かる後、薄膜状の３層目デバイス（２０３）裏面に裏面
絶縁膜（２０２）を形成し、さらに前記裏面絶縁膜（２
０２）の開口部に低融点金属を埋めこんだ低融点金属プ
ール（１０６）を形成する（第２図（ｈ））。上述した
一連の工程により１層目デバイスと２層目デバイスと３
層目デバイスとが接続された構造を有する積層デバイス
を得る。The above-mentioned device connection temperature is higher than the melting temperature of a low-melting point metal, that is, 200° C. to 3000° C. when indium is embedded. Next, the second silicon substrate (on which the second layer device (108) is formed) is removed.
Selective polishing (Tsuneo Hamaguchi et al., Applied Physics, 56[11] pp1480) is performed from the back side of 107) to obtain a thin film-like second layer device (201,) (Fig. 2 (C)).
. After that, a back insulating film (202) such as SiO2 is formed on the back surface of the thin second layer device (201), and a low melting point metal pool is formed by filling the opening of the back insulating film (202) with a low melting point metal. (106) (Fig. 2 (
d)). After that, the thin film-like second layer device (20
1) and the high melting point metal bump (106) on the third layer device (110).
09) so that they face each other (FIG. 2(e)), the high melting point metal bump on the third layer device (111) is placed in the low melting point metal pool (106) on the thin film-like second layer device. The second layer device and the third layer device (111) are electrically connected by closely contacting the thin film-like second layer device (201) and the third layer device (111) until the thin film (109) is inserted. Figure (0). After that, the third silicon substrate (111) on which the third layer device (111) is formed
110) is selectively polished from the back side to obtain a thin film-like third layer device (203) (FIG. 2(g)). After that, a back insulating film (202) is formed on the back of the thin third layer device (203), and further the back insulating film (202) is
A low melting point metal pool (106) is formed in which a low melting point metal is embedded in the opening of 02) (FIG. 2(h)). Through the series of steps described above, the first layer device, second layer device, and 3
A laminated device having a structure in which layer devices are connected is obtained.
なお、上述した実施例では３層構造の積層デバイスを得
る場合を説明したが、本発明により半導体デバイスの積
層方法により４層以上のデバイスを積層しうろことは自
明である。また、上述した実施例ではデバイスを接続す
るためには高融点金属バンプ・低融点金属プール間の“
ろう着″を利用したが、その他の接続電極間の接続、た
とえば金属バンプ・金属バンプ間のパ熱圧着′”等を利
用できることも自明である。In the above-described embodiments, a case has been described in which a stacked device with a three-layer structure is obtained, but it is obvious that a device with four or more layers can be stacked using the semiconductor device stacking method according to the present invention. In addition, in the above-described embodiment, in order to connect the device, it is necessary to “
Although "brazing" is used in this embodiment, it is obvious that other connections between the connection electrodes, such as heat compression bonding between metal bumps and the like, can also be used.
さらに、本発明によればシリコン基板以外の半導体基板
に形成されたデバイスを積層しうることも説明するまで
もない。Furthermore, it is needless to explain that according to the present invention, devices formed on semiconductor substrates other than silicon substrates can be stacked.
（発明の効果）
以上許述したように、この発明によれば、予め複数のデ
バイスをシステム・回路・マスクの設計からデバイス形
成さらにデバイスの回路動作テストまで並列処理で用意
しておいた後、デバイスを順次積層するといった一部並
列工程処理が可能となり、積層数が増加してもＴＡＴが
著しく長期化するといった恐れはない。(Effects of the Invention) As described above, according to the present invention, after a plurality of devices are prepared in advance through parallel processing from system/circuit/mask design to device formation to device circuit operation testing, Partly parallel process processing such as sequentially stacking devices becomes possible, and even if the number of stacked layers increases, there is no fear that the TAT will become significantly longer.
第１図は本発明に係る半導体デバイスの積層方法のうち
積層用デバイス形成プロセスの一実施例を説明するため
の製造工程断面図、第２図は本発明に係る半導体デバイ
スの積層方法のうちデバイス積層プロセスの一実施例を
説明するための製造工程断面図である。
１０１・・・デバイス、１０２・・・シリコン基板、１
０３・・・第１のシリコン基板、１０４・・・第１層目
デバイス、１０５・・・絶縁膜、１０６・・・低融点金
属プール、１０７・・・第２のシリコン基板、１０８・
・・第２層目デバイス、１０９・・・高融点金属バンプ
、１１０・・・第３のシリコン基板、１１１・・・第３
層目デバイス、２０１・・・薄膜状の第２層目デバイス
、２０２・・・裏面絶縁膜、２０３・・・河膜状の第３
層目デバイス。FIG. 1 is a cross-sectional view of the manufacturing process for explaining an embodiment of the process for forming a stacked device in the method for stacking semiconductor devices according to the present invention, and FIG. FIG. 3 is a manufacturing process cross-sectional view for explaining an example of a lamination process. 101... Device, 102... Silicon substrate, 1
03... First silicon substrate, 104... First layer device, 105... Insulating film, 106... Low melting point metal pool, 107... Second silicon substrate, 108...
...Second layer device, 109...High melting point metal bump, 110...Third silicon substrate, 111...Third
Layer device, 201... Thin film-like second layer device, 202... Back insulating film, 203... River film-like third layer device.
layer device.
Claims (1)
デバイス上に接続電極を形成し、さらに以下の（イ）に
示すデバイス積層プロセスにより第１の半導体基板に形
成された第１層目デバイス上にデバイスを順次積層する
ことを特徴とする半導体基板の積層方法。 （ア）半導体基板にデバイスを形成する工程と、前記デ
バイス上に表面側接続電極を形成する工程により半導体
基板上に表面側接続電極の形成されたデバイスを形成す
るプロセス。 （イ）第１の半導体基板に形成されている第１層目デバ
イス上の表面側接続電極と第２の半導体基板に形成され
ている第２層目デバイス上の表面側接続電極とを位置合
わせして接続する工程と、前記第２の半導体基板の裏面
より薄膜化する工程と、前記薄膜化工程により得られた
第２層目薄膜状デバイスの裏面に裏面絶縁膜を形成する
工程と、前記第２層目薄膜状デバイスの裏面に裏面側接
続電極を形成する工程と、第３の半導体基板に形成され
ている第３層目デバイス上の表面側接続電極と前記第２
層目薄膜状デバイスの裏面側接続電極とを位置合わせを
して接続する工程と、前記第３の半導体基板の裏面より
薄膜化することにより第３層目薄膜状デバイスを形成す
る工程と、前記第３層目薄膜状デバイスの裏面に裏面絶
縁膜を形成する工程と、前記第３の薄膜状デバイスの裏
面に裏面側電極を形成する工程。[Claims] A connection electrode is formed on the device by the stacking device forming process shown in (a) below, and a connecting electrode is formed on the first semiconductor substrate by the device stacking process shown in (b) below. A method for stacking semiconductor substrates, comprising sequentially stacking devices on a first layer device. (a) A process of forming a device on a semiconductor substrate with a front-side connection electrode formed by a step of forming a device on a semiconductor substrate and a step of forming a front-side connection electrode on the device. (B) Align the front side connection electrode on the first layer device formed on the first semiconductor substrate and the front side connection electrode on the second layer device formed on the second semiconductor substrate. a step of thinning the second semiconductor substrate from the back surface thereof; a step of forming a back insulating film on the back surface of the second layer thin film device obtained by the thin film forming step; forming a back side connection electrode on the back side of the second layer thin film device;
a step of aligning and connecting the back surface side connection electrode of the layered thin film device; a step of forming a third layer thin film device by thinning the layer from the back surface of the third semiconductor substrate; A step of forming a back insulating film on the back surface of the third layer thin film device, and a step of forming a back side electrode on the back surface of the third thin film device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17926789A JPH0344066A (en) | 1989-07-11 | 1989-07-11 | Laminating method of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17926789A JPH0344066A (en) | 1989-07-11 | 1989-07-11 | Laminating method of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0344066A true JPH0344066A (en) | 1991-02-25 |
Family
ID=16062860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17926789A Pending JPH0344066A (en) | 1989-07-11 | 1989-07-11 | Laminating method of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0344066A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5948950A (en) * | 1982-09-13 | 1984-03-21 | Agency Of Ind Science & Technol | Manufacture of three-dimensional integrated circuit structure |
-
1989
- 1989-07-11 JP JP17926789A patent/JPH0344066A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5948950A (en) * | 1982-09-13 | 1984-03-21 | Agency Of Ind Science & Technol | Manufacture of three-dimensional integrated circuit structure |
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